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TCAD News

June 2007

Contents
4
TCAD Distortion Analysis Based on the
TCAD for Electrostatic Discharge
Harmonic Balance Method
5 Introduction I process and device simulation model set in
An Efficient Simulation Environment for Trend for
1D and 2D. In a further step, ESD-related
Modeling Single Event Effects with the Electrostatic discharge (ESD) is a major threat Thinner Oxides
to the reliability of integrated circuits, where modeling shown in Figure 3 is addressed by:
Sentaurus Tool Suite VSUPPLY VBD
approximately 20% of total integrated circuit • High-temperature calibrated models: Impact
6 (IC) failures are due to ESD [1]. Discharge Latch-Up ionization and mobility (low-field, carrier-to-
Impact of Gettering Effects in Solar Cells of charged objects or human discharge into Margin carrier scattering, high-field saturation)
Device Damage
7 IC chip pins with very high currents (up to Margin
• Bipolar-specific models: Recombination
Simulation of 4H-SiC Vertical Junction FET 10 A) and short duration (1 ns to 200 ns)
and bandgap narrowing
in Sentaurus Device causes serious damage to the very sensitive
devices of the circuitry. This happens during Vh Vt1 V • Electrothermal effects: Self-heating
manufacturing, assembly, shipment, and in the Figure 1. Typical ESD design window for mechanisms and heat flows
field. protection devices. • Information about layout and measurement
This article demonstrates the successful use setup: Contact resistances and 3D layout
of TCAD for the simulation and investigation insights into the internal device behavior (such features

Latest Edition of ESD-related problems, as well as for


the development and optimization of ESD
as temperature and current distributions, and
electric fields) under ESD stress conditions, 100
Self-heating
protection devices and methodologies with which are generally not accessible by (mobility, impact ionization)
1500

respect to ESD robustness. The full range from measurement. In particular, TCAD can be Snapback
Welcome to the latest issue of TCAD ESD calibration, ESD device simulation, to used successfully for the study of 3D effects

Maximum Temperature [K]


10-1 (bipolar effect)

Drain Current [A]


News. Over the years, TCAD has proven to ESD compact modeling for circuit simulation arising from device layout or inhomogeneous
1000
be an enabling methodology for reducing is covered. current flow as shown in Figure 2. TCAD is
technology development costs and time. invaluable for modeling these complex ESD
Background 10-2
The use of TCAD, however, extends beyond effects [4][5], providing simulation results that Breakdown
nanoscale silicon CMOS devices. In this The operational regime of devices under complement expensive measurements and (impact ionization)
500

issue, I am delighted to present articles ESD stress is far beyond the range of normal reducing expensive experiments on wafers. 10-3
showing the wide application of TCAD operation conditions. Among the most 0 10 20 30 40

important effects to be considered within the From the device or TCAD engineering Drain Voltage [V]
tools for modeling and analyzing physical
ESD regime are self-heating, conductivity perspective, establishing a full-fledged Figure 3. Physical effects considered for
phenomena and effects beyond nanoscale
modulation due to high carrier injection, ESD TCAD workbench from process and successful ESD modeling. The example shows
silicon CMOS devices.
nonuniform operation (current filamentation), layout information, and from the calibration the high-current behavior of a power MOS device
As device features continue to scale down, of simulation models including the high obtained by simulation.
and avalanche breakdown at reverse-biased
the threat of device or circuit failures caused current/high temperature regime, allows the
junctions.
by reliability issues such as electrostatic evaluation of process variation influences, the Essential for correct device modeling and
discharge (ESD) and single event effects To characterize the device high-current determination of layout dependency, and the calibration is knowledge about the TLP tester
(SEEs) grows. For example, device engineers regime, mostly the transmission line pulsing optimization of ESD structures. The improved rise-time, the pulse duration, and the voltage
face difficult challenges of designing robust (TLP) technique is used [2]. This two-terminal understanding of the internal device failure extraction method used in measurements in
ESD protection and meeting the required technique consists of feeding a constant modes results in building better input/output order to implement the same conditions in
ESD levels in new designs. The first article current pulse into the device under test (DUT) protection structures and the possibility simulation. The HBM tester–equivalent circuit
outlines a TCAD-driven ESD approach and monitoring the voltage response. The of virtual testing and development of new model must be known if HBM robustness is to
that enables chipmakers to develop a pulse has a typical duration of 100 ns with a structures. TCAD also helps speed up ESD be simulated and compared to measurements.
comprehensive methodology to analyze rise-time of 10 ns. The characterization using design to keep pace with IC developments The mixed-mode simulation capability of
and treat ESD-related problems. Another TLP allows for obtaining device characteristics at reduced design-cycle times by reducing Sentaurus Device permits the integration
reliability issue is SEE, which can cause up to very high current levels, while preventing time-to-market and cost-to-market. of the HBM tester–equivalent circuit model
unwanted changes to semiconductor early destruction due to self-heating.
From the circuit or library design perspective, with the physical device model of the DUT
devices when highly energetic particles Within the device simulation environment, TCAD permits the development and in the simulation environment. A comparison
strike an IC chip. We include an article to TLP is used to calibrate high-current, high- application of physically based SPICE of TLP versus HBM measurement/simulation
show an efficient way of modeling the effects temperature regimes to measurements. For ESD compact models and parameter methodologies is shown in Figure 4.
of single event upset on CMOS devices. the qualification and specification of ESD extraction methodologies from simulation Methodology for ESD Device
This edition also includes articles on specialty robustness, other more realistic ESD stress and measurement. The SPICE ESD compact Calibration and Simulation
devices. For readers interested in analog models are used. The most prominent one models allow for simple and fast use within
RF devices, one article examines the use is the human body model (HBM), which circuit and analog design, and for optimization The junction breakdown characteristics due
of harmonic balance in Sentaurus Device reproduces the discharge of the body of a of protection configurations. The simulation- to impact ionization and tunneling should be
to analyze the distorting characteristics human being. Additional models used are based methodology allows checking of critical already in good agreement with measurements
of an SiGe BJT and Si NMOS RF device. the machine model (MM) and the charged input/output protection configurations before at room temperature. Nevertheless, in some
Recent progress in improving SiC material device model (CDM). Apart from the field of IC tape-out and avoiding redesigns. cases, a fine-tuning of model parameters
with zero micropipe defects is pushing application, they differ from the HBM due to a may be necessary. The onset of breakdown
different rise-time, peak current, duration, and Requirements for ESD Modeling is influenced mainly by the doping profile
SiC electronic devices for high-power and
high-temperature applications into the polarity [3]. The starting point for a successful calibration (gradient), the bending of material interfaces
mainstream. We include an article showing of the ESD characteristics of a device is a (for example, LOCOS bird’s beak), and the
In summary, the basic functionality of an ESD
the benefits of using TCAD to explore and well-calibrated, low-current and breakdown doping profile corner effects (3D).
protection device or circuit is to provide a
optimize an emerging technology such as low-resistivity discharge-current path, which
SiC. In addition, we highlight the impact of prevents the internal circuitry as well as the
gettering effects in solar cells. protection device/circuit itself from being
I trust that you will enjoy this edition of TCAD damaged during an ESD event. The ESD
News. Please contact us for your comments protection functionality is ‘transparent’ to
and feedback. the internal circuitry under normal operation
conditions. Figure 1 shows the most important
With best regards, Figure 2. Formation of
parameters of the so-called ESD design
window. current filament leading
Abs(TotalCurrentDensity)
1.0e+06 to temperature hot-spot in
TCAD-Driven ESD Optimization 6.3e+04 a device during an ESD
Terry Ma
4.0e+03
pulse using Sentaurus
TCAD is a powerful tool for identifying and 2.5e+02

Group Director, TCAD Business Unit Device 3D device


investigating ESD-relevant effects, providing 1.6e+01
simulation.
1.0e-00
TCAD News
HBM-equivalent Lumped Element Circuit 10-2
Voltage Response DCG = 1 µm
DCG = 2 µm
TLP Current Cs 10-3 Holding Point
Increasing Current Level
10-4
Ls Nonsalicide blocked Snapback Point
S1 S2 10-5
Rhbm

Id [A]
Vhbm 10-6

10-7
Chbm Ctb DUT 10-8
70% of tp
Time
Salicide blocked Drain 10-9

10-10
tr tp tf 0 2 4 6
Vd [V]

Current HBM Current Gate


DCG = 1 µm
Double Exponential Source 0.015
DCG = 2 µm
It2
Current Waveform
Bulk
0.01 Ron

Id [A]
Voltage Time
Figure 6. ESD failure signature: molten silicon
0.005 Holding Point
between drain and source contacts due to current
Figure 4. TLP versus HBM measurement/simulation methodologies. TLP is more suitable for calibration filaments.
purposes due to controlled current condition. HBM tries to reproduce the discharge through the human 0 2 4 6
body and is used for ESD robustness assessment. Both methods have comparable pulse energies, and Vd [V]

their ESD failure levels show a clear correlation [2].


Figure 8. (Top) Snapback I–V characteristics
of 3D NMOS in logarithmic current scale and
The temperature dependence of impact of the bandgap narrowing model may need simulation are found in literature [5][7][8]. They (bottom) linear current scale.
ionization must be calibrated as well to obtain to be adjusted in this case. Some influence all try to avoid the use of high-temperature
the correct behavior at high temperatures. of high-field saturation (carrier velocity device simulations because of expected lower leads to an inhomogeneous current flow. At
Ideally, breakdown voltage measurements saturation) may be seen as well. accuracy and convergence problems. the holding point, Id = 3 x 10–3 A, the current
at different temperatures are used for this A further increase of the collector (drain) In summary, the starting point is a well- flow is still inhomogeneous but starts to
purpose. current leads to an increase of the device calibrated simulation environment for normal homogenize. The current constriction during
For calibrating the snapback point (It1, Vt1), voltage due to its on-resistance Ron = collector operation conditions, and then models snapback cannot be modeled with 2D device
the most important quantity is the effective or drain resistance. Usually, the holding region required for modeling ESD behavior are simulations. Therefore, 2D simulations would
base resistance Rb of the bipolar device (or after snapback in TLP measurements is not added and calibrated step-by-step from lower predict too low a holding voltage because a
the inherent parasitic bipolar device between very well resolved due to the small load-line to higher current levels. In the end, the goal is larger effective device width is assumed.
the drain, body, and source in the case of resistance (50 W) of the equipment. For the to obtain one set of parameters that allow the Above the holding point, the current starts
MOS). Bipolar snapback is triggered after the calibration of Vh, such measurements may predictive simulation of ESD behavior and, at to flow more and more homogeneously
collector-base junction is driven into avalanche be sufficient because of the low Ron (almost the same time, that can be used for normal over the entire width of the device, and the
breakdown (see Figure 5). As a result, in the vertical characteristics) after the holding point. operation conditions. An accuracy of It1, Vt1, temperature starts to rise. The hot spot lies
case of NPN, the impact-generated hole At the current levels, after holding point, self- Vh, and Ron compared to TLP measurements at the drain junction towards the gate, and
current is conducted from the avalanche heating plays the predominant role. Therefore, of 10% is reasonable. For It2 using the the temperature is higher in the middle of the
region (G) through the p-region to the base the definition of suitable thermal boundary abovementioned method, 30% is feasible. device. This leads eventually to a destructive
contacts. Consequently, the hole current conditions for electrothermal simulation Example of 3D ESD Simulation current filament in the middle of the device
causes a voltage drop across the Rb, which is mandatory. The importance of these when the temperature approaches the intrinsic
induces a forward bias to the base‑emitter conditions even increases if the temperature Electrothermal ESD simulations of a 3D temperature of silicon.
junction. Eventually, a sufficient base-emitter hot-spot lies near the simulation boundary. NMOS structure are presented to demonstrate
current flow results in the triggering of the the capabilities of TCAD for ESD. Figure 7
The temperature distribution may become
Id = 3e-4 A Id = 3.4e-4 A Id = 3e-3 A

NPN transistor. The positive feedback loop shows the structure of the NMOS simulated.
inhomogeneous in the third dimension as Only half of the device has been modeled to
formed by increasing impact ionization and well. In that case, 3D simulation is needed.
increasing forward bias of the base-emitter save mesh points by taking advantage of the
Similar to the case of the snapback point, this symmetry plane in the middle of the device.
junction produces the well-known voltage situation can be considered in 2D by adding
snapback behavior with a negative differential The gate length is 0.35 mm, and the entire
an external series resistance extracted from simulation area is 6.3 x 3.5 x 10 mm. The
resistance (NDR) regime until a holding 3D simulation.
Id = 1e-2 A Id = 1.4e-2 A Id = 1.5e-2 A

voltage Vh is reached. distance between the drain-contact and gate


For tuning Ron in this regime, besides the has been varied as indicated.
temperature dependence of bulk mobility,
+
carrier–carrier scattering and high-field DopingConcentration
3.1e+20 TotalCurrentDensity

saturation model parameters can be used. The 9.8e+16 5.0e+06

B E B C voltage drop across the series resistances of


3.1e+13 9.1e+05
1.7e+05
e h
-2.6e+13
the measurement setup and across the device -8.3e+16
3.0e+04

h G 5.5e+03
contacts are taken into account; otherwise, -2.7e+20
1.0e+03
e
this can lead to erroneous calibration. At the
Figure 5. Schematic cross section of NPN point where the device becomes intrinsic (the DCG Id = 3e-4 A Id = 3.4e-4 A Id = 3e-3 A

transistor (or parasitic NPN transistor in MOS thermally generated carrier concentration
case) showing carrier flow in snapback operation. exceeds the doping concentration), the
so-called second breakdown or thermal
The calibration of the snapback current breakdown sets in. The device is damaged
level It1 may require some adjustment of the irreversibly by the melting of silicon as a Id = 1e-2 A Id = 1.4e-2 A Id = 1.5e-2 A

parameters of the low-field mobility model result of the fast thermal runaway caused Figure 7. Three-dimensional NMOS structure
for low- and medium-range temperatures by the positive feedback loop, consisting simulated; the DCG has been varied.
because self-heating may play a role. If of decreasing resistivity and increasing
evidence of inhomogeneous current flow is Figure 8 shows the typical snapback
temperature. The current level at which this LatticeTemperature

found (inhomogeneous triggering [6]), it is I–V characteristics during an ESD surge. The 1.3e+06
happens is called It2. By its nature, the second 1.1e+05
necessary to use 3D simulations to correctly structure with the smaller drain-contact to
breakdown is a 3D effect. The thermal runaway 9.0e+05

predict snapback behavior (see Example gate (DCG) spacing shows a lower resistivity 7.0e+04
instability occurs in a very confined region of 5.0e+03
of 3D ESD Simulation). In a later step, the in the high-current regime as expected. The
the device, drawing the total device current 3.0e+03

inhomogeneous triggering can be accounted important ESD quantities, snapback point,


into this region and causing the temperature
for in 2D simulations by adding an external holding point, and Ron, are shown also Figure 9. Contour plots of total current density
to exceed the melting temperature of silicon
base resistance Rbext extracted from 3D in Figure 8. Even It2 can be identified by a (upper six graphics) and temperature (lower six
locally. Analyzing the device after stressing
simulation. Rbext increases the total base sudden increase of the voltage due to current graphics) at the drain current level indicated.
by physical failure analysis reveals the molten
resistance and reproduces the effect of filament formation and the subsequent voltage
filament, as shown in Figure 6.
current constriction in a physically correct drop when the silicon becomes intrinsic.
manner. The most simple and direct criterion for
Figure 9 shows contour plots of the total In the last few years,  the transient
simulating the second breakdown is given
The snapback voltage Vt1 is, in general, more current density and the temperature at six interferometric mapping (TIM) characterization
by Tmax ≥ Tmelt. Using this criterion is
difficult to control. It depends mainly on the different current levels. technique from TU Vienna has proven to be
questionable because even the more
voltage drop across the portion of the device advanced simulation models are calibrated The first picture, at Id = 3 x 10–4 A, shows the invaluable in characterizing internal device
between the location of the maximum impact to measurements only up to T = 1000 K, a situation immediately before snapback. The behavior such as hot spots during high-
ionization and the base-collector (source- temperature that is much lower compared breakdown occurs at the drain-to-bulk junction current pulses [9].
drain) terminals. to the melting temperature of silicon (Tmelt towards the gate. The impact ionization is The quantity measured in a TIM measurement is
The holding voltage Vh depends on the bipolar = 1690 K). Nevertheless, an extrapolation homogeneous along the junction, indicated by the phase shift of the laser probe beam. Only a
transistor effective current gain and on the of the model into higher temperature ranges the homogeneous current density. The picture qualitative comparison of the measured phase
impact ionization as a function of the internal should not lead to dramatic errors and, at at Id = 3.4 x 10–4 A is taken immediately shift to simulation results (temperature, current
collector-base voltage and temperature. least, should preserve the trends. Other more after snapback. The parasitic NPN transistor density) has been possible. To compare TIM
Recombination lifetimes and the parameters sophisticated methods for extracting It2 from triggers first in the middle of the device, which measurements directly to simulation results,

 TCAD News June 2007


TCAD News
the tool Absorption and Phase shift Extraction Figure 11 shows an example of a protection
(APEX) was developed by Synopsys. APEX is NPN transistor ESD compact model. V_input ∆V_input
a postprocessor that extracts the phase shift Current- and temperature-dependent series VCC
from Sentaurus Device results so that it can resistors account for conductivity modulation
C
be compared to the measured phase shift effects and self-heating, and are modeled Protection ESD Vce
directly. An advanced example showing the externally. Thermal breakdown is modeled by Diode D2 Compact

Voltage [V]
V_D2 Model:
S
use of APEX is available from SolvNet [10]. R_Tc, which switches irreversibly from a very A Protection
Transistor
Compact Modeling for ESD high to a very low Ohmic state at a critical Input Internal
Circuitry
temperature. The modeling of avalanche HBM 2.0 kV C
There is a great need to include ESD compact breakdown at the collector-base junction is C B
Vce ∆Vh
Protection
models in circuit simulations to predict critical the key element for simulating the snapback Diode D1
S
Vinput
current paths and critical (I,V) node values, and behavior. To eliminate the singularity at Vcb Rbext E

to enhance input/output design quality [11]. V_D2


= BVcbo in the original Miller [13] formulation A
The insight gained by TCAD permits developing of the avalanche multiplication factor M, the
physically based compact model add-ons method reported in [4] is followed, with an 10-10 10-9 10-8 10-7
for ESD. Internal device characteristics not extension to account for weak avalanche Time [s]
Solid: Rbext = 0
accessible by measurements can be studied. current contribution. The resulting function Dashed: Rbext = 2.5 kΩ
Calibrated process and device simulation ∆t_trigger
is an approximation of the original M, but its
allows parameter extraction for ESD compact value is limited at Vcb = BVcbo and it shows a
models. Expensive, noisy, and destructive significantly better convergence behavior. Figure 12. Additional external base resistor Rbext increases the protection NPN triggering speed during
measurements can be avoided. an HBM stress simulation. Consequently, the effect of the D2 voltage overshoot peak on the voltage at
Apart from the core transistor itself, the
To keep the compact model development the input node is reduced. Rbext also leads to a reduction of the holding voltage. Time axis is plotted in
parasitic PNP between the source, collector,
effort to a reasonable level, a modular logarithmic scale to show the details of the protection NPN transistor triggering.
and base is included.
modeling strategy is chosen. This strategy
S
is often referred to as macro-modeling or Thermal Overload
subcircuit modeling in the literature [12]. The
Parasitic T
standard model of the corresponding device Rs
Tc
(for example, a Gummel–Poon or BSIM Protection Transistor
VCC Temperature
model) has been retained for normal operation C P→T Rc
T
Re E 1000
V_input
conditions, and it has been extended by ESD- C
Protection ESD

Temperature [°C]
specific add-on modules to form a full ESD V_D2
Diode D2 Compact

Voltage [V]
Model:
compact model. Avalanche
S
Protection
Source A
Transistor
The operational regime of devices under ESD Input Internal
Circuitry
stress is beyond the range in which standard HBM 4.5 kV C Vce 500
Vce
compact models have been tested and verified; Rb
C
Protection
B
S
whereas, the full ESD compact models allow Vinput Diode D1
Rbext E
for reproducing behavior under ESD stress B V_D2
A
in circuit simulation. Thermal effects are
R_Tc
included by establishing a feedback loop
0 1e-07 2e-07 3e-07
between electric and thermal domains. The Figure 11. Protection NPN transistor ESD Time [s]
thermal domain is modeled using first-order or compact model: (red) standard models, (black) Transition into permanent low
higher-order thermal RC networks, depending ESD compact model add-ons, and (green) Ohmic state (device damaged)
on the complexity of the temperature fields of coupling to thermal network.
the device (one or more highly localized hot Figure 13. Increasing the HBM stress voltage to 4.5 kV leads to damage of the protection NPN
transistor. This is modeled by an abrupt and irreversible voltage drop at a predefined critical temperature
spots or almost homogeneous distribution). The transient triggering behavior [14] is
Tc. Time axis is plotted in linear scale.
Figure 10 shows how the ESD compact influenced mainly by the junction capacitances
models are set up. (displacement current triggering), which
cause a decreasing trigger voltage peak for
increasing stress current rise-times, as well as reduced by increasing the triggering speed References
ESD Compact Model Subcircuit (T dependent)
Including Parasitic Devices
by the base forward transit time (finite amount of the protection NPN using an external base [1] “Fundamentals of ESD, Part One–An Introduction to ESD,”
Thermal RC Network

Standard Models
of time required by the carriers to traverse the resistance. The external base resistance Electrostatic Discharge Association. Article available at <http://
Electric Contacts

www.esda.org/basics/part1.cfm>, May 2007.


base region leading to base-emitter diffusion
Pel Rth1 Rth2 Rthn

decreases the amount of current needed to


Rthn+1

Cth1 Cth2 Cthn [2] J. E. Barth et al., “TLP Calibration, Correlation, Standards, and
ESD Add-ons capacitance), which reduces the triggering forward-bias the base-emitter junction and, New Techniques,” IEEE Transactions on Electronics Packaging
Tamb speed. Capacitances and base transit time therefore, the snapback occurs earlier. If the Manufacturing, vol. 24, no. 2, pp. 99–108, 2001.
[3] G. Notermans, P. de Jong, and F. Kuper, “Pitfalls when correlating
as well as the current gain of the bipolar HBM precharge voltage increases from 2 kV TLP, HBM and MM testing,” in Electrical Overstress/Electrostatic
transistors, which determines the holding
T1, T2, ..., Tn
to 4.5 kV, the protection NPN transistor is Discharge Symposium (EOS/ESD), pp. 170–176, 1998.
Figure 10. Modular setup of ESD compact models voltage Vh, are parameters belonging to the damaged by the second breakdown. In the [4] M. P. J. Mergens, On-Chip ESD Protection in Integrated Circuits:
including thermal network fed by dissipated Device Physics, Modeling, Circuit Simulation, Ph.D. thesis, ETH
standard compact model instances. Their circuit simulation shown in Figure 13, this Zurich, Switzerland, 2001.
power Pel. The resulting temperatures T1…Tn extraction is usually performed by simulations happens as soon as the protection NPN [5] K. Esmark, H. Gossner, and W. Stadler, Advanced Simulation
complete the feedback loop.
or measurements under normal operation temperature reaches a predefined critical Methods for ESD Protection Development, Amsterdam: Elsevier,
2003.
conditions. Their values in the very diverse temperature Tc.
A dedicated methodology for the extraction of ESD current regimes may differ considerably
[6] C. Russ et al., “Non-Uniform Triggering of gg-nMOSt Investigated
by Combined Emission Microscopy and Transmission Line
ESD compact model parameters is developed, Summary
compared to normal operation conditions. Pulsing,” in Electrical Overstress/Electrostatic Discharge
based on TCAD results and measurements. Therefore, a readjustment of these parameters ESD is a real threat to IC reliability; therefore,
Symposium (EOS/ESD), pp. 177–186, 1998.
[7] C. H. Díaz, S.-M. Kang, and C. Duvvury, “Simulation of Electrical
The calibrated ESD compact models can be may be necessary to obtain the correct meeting ESD robustness specifications is Overstress Thermal Failures in Integrated Circuits,” IEEE
used within circuit simulations to determine behavior under ESD stress conditions. mandatory. Treating ESD-related problems Transactions on Electron Devices, vol. 41, no. 3, pp. 359–366,
1994.
critical current paths, to identify endangered is a challenging task. The use of TCAD
ESD Circuit Simulation [8] C. Salaméro et al., “Accurate prediction of the ESD robustness
devices, and to optimize protection circuitry. to simulate and investigate ESD-related of semiconductor devices through physical simulation,” in 43rd
Circuit simulations with up to ten ESD In Figure 12, the ESD compact models for problems enables robust and reliable design Annual International Reliability Physics Symposium, San Jose,
CA, USA, pp. 106–111, 2005.
protection devices and 100 standard devices a protection NPN transistor and for two of ESD protection devices/circuits, thereby [9] D. Pogany et al., “Quantitative Internal Thermal Energy Mapping
are feasible. The limitation arises from the protection diodes are used within an input pin reducing IC development costs and cycle of Semiconductor Devices Under Short Current Stress Using

well-known convergence problems caused by protection HBM circuit simulation. time. Backside Laser Interferometry,” IEEE Transactions on Electron
Devices, vol. 49, no. 11, pp. 2070–2079, 2002.
the strong nonlinear behavior of the protection For simplicity, the internal circuitry comprising However, reliable modeling of devices and [10] “Simulation of Current Filament During Electrostatic Discharge
devices under ESD stress conditions and from the first stages of the circuit is sketched circuits under ESD stress conditions requires
Pulse (Z-2007.03),” available from SolvNet <https://solvnet.
synopsys.com/retrieve/020415.html>, May 2007.
their interaction with the rest of the circuit. by a box only. The protection diode ESD specialized knowledge and broad experience. [11] V. Vassilev et al., “A CAD assisted design and optimisation
The nonlinearities cannot be eliminated, but compact models include effects such as The TCAD-driven ESD methodology, which methodology for over-voltage ESD protection circuits,” in 15th
European Symposium on Reliability of Electron Devices, Failure
they can be reduced to an acceptable level voltage overshoot due to forward recovery has been developed by the Synopsys Physics and Analysis (ESREF), Zurich, Switzerland, 2004.
by giving particular attention to numeric [15], reverse breakdown, and conductivity Consulting and Engineering group and has [12] J. Li, S. Joshi, and E. Rosenbaum, “A Verilog-A Compact Model
issues. While nonlinear behavior (for example, modulation due to high injection. Applying been outlined in this article, has a proven for ESD Protection NMOSTs,” in Proceedings of the IEEE
Custom Integrated Circuits Conference, San Jose, CA, USA,
snapback devices) is one key issue to account a positive HBM stress between the input track record of success in helping customers pp. 253–256, September 2003.
for in ESD simulations, it makes the numeric pin and ground leads to a main current flow meet their challenges of treating ESD-related [13] S. L. Miller, “Ionization Rates for Holes and Electrons in Silicon,”

treatment extremely unstable and computing through D2 and the protection NPN, which problems. The two service offerings, TCAD Physical Review, vol. 105, no. 4, pp. 1246–1249, 1957.

goes into snapback and, therefore, limits the [14] H. Wolf, H. Gieser, and W. Wilkening, “Analyzing the
intensive. Nevertheless, the circuit complexity ESD Workbench and ESD Compact Model Switching Behavior of ESD - Protection Transistors by Very Fast
extends simple input/output pad protection voltage at the VCC line. The voltage at the Development, can be customized specifically Transmission Line Pulsing,” in Electrical Overstress/Electrostatic
input pin is given by the sum of the voltages Discharge Symposium (EOS/ESD), Orlando, FL, USA,
configurations, including large parts of the to protect your IC products from ESD pp. 28–37, September 1999.
internal circuit. For the implementation of at VCC and the voltage drop across D2. damage. [15] K. J. Tseng, “Modelling of diode forward recovery characteristics
the ESD add-on model equations, Verilog-A Due to voltage overshoot, the voltage drop using a modified charge-control equation,” International Journal
Contact tcad_team@synopsys.com for more of Electronics, vol. 84, no. 5, pp. 437–444, 1998.
behavioral modeling language can be used. across D2 can exceed the stationary DC
information on our ESD service offerings.
Verilog-A can be read by most common circuit voltage drop considerably. It is shown that
simulators such as HSPICE® and Spectre. the transient voltage peak at the input pin is

TCAD News June 2007 


TCAD News

TCAD Distortion Analysis Based on the Harmonic Balance Method


Introduction Input Input log(Output)
Output Output
The dynamic range of linearity is a critical First Harmonic
(10 dB/decade)
specification in most analog applications.
Even if the output signal changes almost
linearly with the input signal, intrinsic device IP3
distortion effects are present, and higher (IIP3)

harmonics draw power from the fundamental Third Harmonic


signal. (30 dB/decade)

Besides small-signal and noise characteristics, f1 2f1 3f1 4f1 2f1-f2 f1 f2 2f2-f1
Frequency Frequency log(Input)
these distortion effects are the most important
properties in analog radio frequency (RF) Figure 1. (Left) Input signal with modulation frequency f1 (black) results in output signal with spectral Figure 2. Schematic of third-order intercept point,
circuits such as power amplifiers, mixers, and components at f1 and integer multiples of f1 (harmonic distortion). (Right) Two-tone input signal at f1 which is defined by the extrapolated crossing
and f2 also generates spectral components at 2f1-f2 and 2f2-f1 (intermodulation distortion). point of the fundamental first and third harmonics
drivers. Although distortion is the fundamental
of the output signal.
mechanism of mixers to generate signals at
various frequencies, it must be as low as
possible for most other applications.
Distortion characteristics are divided typically The HBM can be used for 1D, 2D, or 3D transconductance and the input impedance. Figure 5 shows a generic NMOS with a
into two groups: simulation setups using drift-diffusion or The input impedance diffusion capacitance nominal gate length of 65 nm, width of 1 µm,
hydrodynamic frameworks. Arbitrary devices Cbe in BJTs is more nonlinear compared oxide thickness of 2 nm, and substrate doping
• Harmonic distortion: A sinusoidal input
and circuits can be simulated including various to the gate capacitance Cgs in MOSFETs, of 5 x 1017 cm–3. The device is biased to Vds
signal at frequency f (also called one-tone)
classes of FETs, (hetero) bipolar transistors, causing the strong frequency-dependent = 1.2 V and is modulated with a gate source
results in an output signal with spectral
HEMTs, as well as optoelectronic devices distortion characteristics in BJTs; whereas, voltage of 0.1 V at 1 MHz.
components at f (first harmonic), 2f (second
such as semiconductor lasers [2]. As a major the MOS devices feature a very low frequency Figure 6 shows the V_IP3 characteristics
harmonic), and 3f (third harmonic) (see
advantage of the HBM, arbitrary large-signal dependence of distortion. Figure 4 also as a function of the DC gate voltage Vgs for
Figure 1 (left)). The extrapolated crossing
modulation conditions can be captured within shows that the third harmonic of the collector different substrate dopings Ns and oxide
point of the first and third harmonics is
one single simulation using a ramping strategy. current features a second-order low-pass thicknesses tox. With increasing Vgs, the
called the third-order interception point
This is more efficient compared to transient characteristic, causing a strong decrease of linearity increases and features a sharp peak
(IP3) and is a typical metric to characterize
simulations, where a new simulation must be the third-order intercept voltage (V_IP3) in the around the threshold voltage, which originates
the linearity of a device or system (see
started for each modulation condition. GHz regime. from cancellation effects of the higher order
Figure 2).
As a consequence of the increased system harmonics [3][4].
• Intermodulation distortion: The input signal
size that must be solved during an HBM Figure 7 shows the first harmonic of the
comprises two sinusoidal signals with 102 Ic3 1
simulation, the memory requirements are Ic2
electron density in a cut through the channel
fundamental frequencies f1 and f2 (also Ic1
V_IP3
typically 5–20 times higher than for a classical 10 1

called two-tone) with equal amplitudes. as a function of the DC bias voltage Vgs. For
DC, AC, or transient simulation. However, on 100
0.5
low bias Vgs, the electron density towards the
The resulting, more complex, spectrum First Harmonic
shared-memory architectures, the simulation drain side is modulated remarkably stronger
of the output signal is shown in Figure 1

V_IP3 [V]
10-1
speeds up linearly with the number of
IC [mA]

0
(right). The typical quantity to characterize Second Harmonic than for high Vgs. This is one cause of the
processors. 10-2
higher distortion at low bias Vgs observed in
this situation is the extrapolated crossing
point of the fundamental signal at f1 with SiGe Bipolar Transistor Distortion 10-3
-0.5 Figure 6.
the amplitude at 2f1-f2, which is called the Analysis 10 -4
Third Harmonic The HBM can be used also to investigate
third-order intermodulation intercept point Silicon germanium (SiGe) is a key technology 10-5 -1 high-amplitude modulation conditions
(IIP3). for RF integrated-circuit design. In the first
108 109
Frequency [Hz]
1010
such as the 1-dB compression point or
In most applications, the intercept points are example, the frequency-dependent harmonic Figure 4. Frequency-dependent harmonic the saturation behavior of first-order and
not reached due to saturating signals at high distortion characteristics of a typical SiGe distortion characteristics of SiGe. Third-order third-order modulation products in two-tone
input amplitudes. Nevertheless, the intercept bipolar transistor (BJT) (see Figure 3) are voltage intercept point (V_IP3) strongly decreases experiments.
points serve as main figures of merit for analyzed using a 2D simulation setup. For in low GHz regime due to increasing third
distortion. the harmonic balance investigation, eight harmonic of collector current.
Gate
harmonics are taken into account.
Although distortion characteristics are
relatively easy to measure, little is known The device is biased (without matching circuit) 65 nm NMOS Distortion Analysis
about the physical origin at the device level. In to Vce = 1.5 V and Vbe = 0.9 V. The biasing
addition, most modeling activity has focused is chosen such that the transit frequency The scaling of CMOS technology offered a
on compact models, which inherently miss ft reaches its maximum value of 77 GHz. In significant improvement in RF performance in
the important physics behind distortion and addition, the base voltage is modulated with MOS devices. In view of the fast growth of the Source Drain

are often not scalable. 10 mV at varying frequencies. wireless communication market, designers DopingConcentration [cm-3]
1.2e+20
are exploring conventional CMOS instead
Figure 4 shows the frequency-dependent
1.2e+17
Harmonic Balance in Sentaurus Device of III–V or SiGe in RF circuits. Since system 1.3e+14

harmonic distortion characteristics for this requirements on linearity become more


-1.7e+12
Conventional TCAD time-domain analysis
device. BJTs feature very strong frequency-
-1.8e+15

could, in principle, be used to analyze stringent for future wideband RF applications, -1.7e+18

dependent distortion effects. the inherent superior linearity compared to the


distortion in semiconductor devices, but this
approach is often prohibitively expensive in For both bipolar and MOS transistors, the two faster SiGe BJTs is a significant advantage for Figure 5. Doping profile of 65 nm NMOS.
terms of computing resources: major nonlinear sources of distortion are the CMOS [3].
• The applied input signals in distortion
experiments are sinusoids that may have
very narrowly spaced frequencies. This Figure 8 shows the results of an intermodulation
requires a time integration over an enormous Emitter
Collector distortion simulation for the 65 nm NMOS
number of periods of the input frequencies. with a DC bias Vgs of 0.7 V and f1 = 1 MHz,
Base
• The steady-state behavior of the system is f2 = 1.001 MHz for increasing modulation
usually of primary interest. The presence amplitude Vg1. For gate voltage modulation
of filtering and matching circuitry around amplitudes higher than 0.2 V, saturation of
the primary device can introduce extremely both the fundamental harmonic and the third-
long time constants. This results, again, in a order modulation products of the drain current
huge number of necessary time steps. increases, limiting the maximum available
modulation power.
The harmonic balance module (HBM), the
DopingConcentration [cm-3] The examples without matching circuits
latest analysis technique implemented in
1.5e+20
Sentaurus Device Version Z-2007.03, uses investigated so far are used mainly for low-
a mixed frequency-domain time-domain 6.6e+16 frequency amplification applications with
method [1], which addresses the above 2.9e+13 modulation frequencies below 10% of the
problems. transit frequency of the device.
-1.9e+13
The HBM captures directly the large-signal For high-frequency amplification, a suitable
-4.4e+16
steady-state response of nonlinear systems matching circuit (reactive or resistive) must
-9.9e+19 be optimized for each specific application.
without tedious time-stepping algorithms.
In addition, the HBM exhibits an excellent This can be performed also using the HBM
dynamic range to resolve low-level distortion where the matching elements are added in a
products. Figure 3. Doping profile of npn SiGe bipolar transistor. SPICE-like manner.

 TCAD News June 2007


TCAD News
Conclusion 101 100
Vgs Low
In summary, the harmonic balance module 2e+11

available in Sentaurus Device opens the 10-1

possibility to analyze distortion effects at the 1.5e+11 Vgs High


device level in an efficient way. Applications 10-2

V_IP3 [V]
include harmonic distortion, intermodulation

n [cm–3]
10 0

Id [mA]
1e+11
distortion, and signal compression analysis 10-3
for a wide range of devices using a one-
dimensional, two-dimensional, or three- 5e+10
Ns = 5e17 cm-3, tox = 2.0 nm 10-4
dimensional geometry, and a mixed-mode Ns = 5e16 cm-3, tox = 2.0 nm
Ns = 5e17 cm-3, tox = 1.5 nm
simulation setup. Sentaurus Device is the ideal 10-1
Ns = 5e16 cm-3, tox = 1.5 nm
0
10-5
Id1 at f1
Id3 at 2f1−f2
0.2 0.4 0.6 0.8
simulation tool for optimization with respect to Vgs[V]
1
10 -2
10 -1
100
-0.1 -0.05 0 0.05
distortion effects already in the device design X [µm]
Vg1 [V]

phase.
Figure 6. Bias dependence of third-order voltage Figure 7. First harmonic component of electron Figure 8. NMOS saturation behavior of
References intercept point (V_IP3) for varying substrate density in NMOS channel. At low DC bias fundamental and third-order drain current
[1] B. Troyanovsky, Z. Yu, and R. W. Dutton, “Physics-based dopings and gate oxide thicknesses. Around the voltage Vgs, the electron density is modulated components for increasing modulation voltage.
simulation of nonlinear distortion in semiconductor devices using threshold voltage, V_IP3 features a peak due to more strongly at the drain side. For modulation amplitudes above 0.2 V, saturation
the harmonic balance method,” Computer Methods in Applied
Mechanics and Engineering, vol. 181, no. 4, pp. 467–482,
cancellation effects of higher order harmonics. effects start limiting the available current and
2000. power gain.
[2] S. Odermatt, B. Witzigmann, and B. Schmithüsen, “Harmonic
balance analysis for semiconductor lasers under large-signal
modulation,” Optical and Quantum Electronics, vol. 38, no. 12‑14,
pp. 1039–1044, 2006.
[3] B. Murmann et al., “Impact of Scaling on Analog Performance
and Associated Modeling Needs,” IEEE Transactions on Electron
Devices, vol. 53, no. 9, pp. 2160–2167, 2006.
[4] R. van Langevelde et al., “RF-Distortion in Deep-Submicron
CMOS Technologies,” in IEDM Technical Digest, San Francisco,
CA, USA, pp. 807–810, December 2000.

An Efficient Simulation Environment for Modeling Single Event Effects with the
Sentaurus Tool Suite

Introduction multiple devices using 3D TCAD. A six- 1.5

Single event effects (SEEs) in microelectronics transistor 90-nm SRAM cell has been modeled
are caused when highly energetic particles with the Sentaurus tool suite, as shown in 1

present in packaging materials, or in natural Figure 1. As device sizes shrink, memory Bit Line
cells are becoming much more compact in Bit Line Bar

Voltage [V]
space and terrestrial environments (for 0.5

example, protons, neutrons, alpha particles, size, with entire cell areas now comparable
or heavy ions), strike sensitive regions of a to single-transistor drain-node areas of only a 0

microelectronic circuit [1]. Similar effects can few generations ago.


occur also when an incident particle collides However, the size of the ion-induced charge -0.5
with an atom and produces a reaction product filament does not scale. In the past, with larger
10-12 10-11 10-10 10-9 10-8
capable of depositing a significant amount of size devices, the simulation of a cell using a
Time [s]
energy. Depending on a number of factors, the Figure 1. Six-transistor SRAM cell built in a single transistor in TCAD, while the others
particle strike can cause no observable effect, 90-nm process. Circuit schematic represents were represented using compact models Figure 2. Node voltages versus time for bit lines
mixed-mode connections for SRAM cell. Although of SRAM cell as a result of a single event strike.
or a transient disruption of circuit operation, all six devices are modeled in a single TCAD
(that is, mixed mode), provided a reasonably
or a change of logic state, or even permanent accurate representation of how the circuit In this case, the cell switched states.
structure, the nodes are wired up in mixed-mode
damage to the device or integrated circuit to allow for voltage perturbations. would respond to a single event. However,
(IC) [1]. SEEs have long been a consideration as we move towards more compact circuitry, of generated charge corresponding to a
for electronics applications in space systematic and rigorous simulation matrix with issues such as multi-node charge collection particular event, rather than an idealized
environments (where ionizing radiation is more than 100 simulations is needed. The and parasitic transistor action are important in description of an average event. Ions can
abundant) and for some terrestrial electronic new capabilities in the Sentaurus tool suite determining circuit responses [7]. interact with the Si substrate, dopant atoms,
applications. allow us to take advantage of a parallel high- The SRAM cell comprises two NMOS or materials above the active silicon and can
Scaling of CMOS device sizes to nanometer performance computing system at Vanderbilt transistors and two PMOS transistors as the cause nuclear reactions [5][8].
dimensions and low operating voltages mean University and to run the simulations cross-coupled inverter pair, and an additional
efficiently. The charge distributions generated by these
that the amount of charge associated with ‘bits’ set of two NMOS transistors that are access events do not necessarily look like single
of information, and circuit noise margins, is We use such simulation capabilities to examine transistors and are used to read or write the vector columns of charge. In many cases,
becoming extremely small. In addition, the high various aspects of SEEs, including charge- cell. The mesh consists of 85 000 vertices, the events actually have several ‘fingers’ of
transistor packing density means that a single sharing, the impact of nuclear reactions in the or 5000 2D elements and 450 000 3D charge, as seen in Figure 3.
ionizing particle potentially impacts multiple overlayers, and single event transients and elements. Each NMOS and PMOS transistor
transistors. All of this increases the challenge upsets [5]. The simulations presented in this is calibrated to SPICE and process data Having the capability to analyze these realistic
of using advanced CMOS technologies in article focus on the single event response of before building the SRAM cell. This ensures a events is vital to understanding how reaction
space and radiation environments and elevates a baseline (unhardened) 90-nm SRAM cell high level of fidelity in the SRAM cell model. products, including those originating in the
SEEs as a major reliability consideration in designed from a commercial 90-nm process. overlayer materials, can alter the response of
The simulations are all run in the mixed-mode the device or circuit.
commercial electronics. environment, as represented in Figure 1. In
Simulation Environment
Analysis of SEEs in advanced circuitry this case, the mixed-mode connections are Simulation Matrix and Parallel
involves the determination of the response of This work was conducted in part using the made to allow the cell to operate as it would in Simulations
multiple interactive devices, coupled with the resources of the Advanced Computing real conditions. All transistors are simulated in
Center for Research and Education To characterize and understand the single
application-specific overall circuit response, TCAD, but the mixed-mode connections allow event response of an SRAM cell, a large
to energy deposition by a particle using (ACCRE) at Vanderbilt University, Nashville, the node voltages to change in response to the
Tennessee [6]. The ACCRE high-performance simulation matrix is designed. The matrix
ionization or secondary reactions. TCAD ion-induced perturbation and potentially for includes various ion-strike locations, linear
and mixed-mode simulations can be used to computing system consists of approximately the cell to flip states, consistent with charge
1500 processors and has a capacity of energy transfer (LET) values, and incident
determine the device and circuit responses moving through the structure. If all nodes ion angles, resulting in more than 100
to radiation events. The characteristics of the approximately 6 TFLOPS. Each node is built were hardwired to a source, the cell would
with dual processors, and each processor simulations.
energy deposition produced by the events, as never change states due to a perturbation.
has at least 1-GB memory. The latest version Figure 2 shows the response of the bit lines Figure 4 shows an example of a matrix of
well as the event rates, can be simulated using
of the Sentaurus tools allows users to run a of the SRAM cell following a heavy ion strike hit locations, where X indicates the area on
Monte Carlo codes such as SEMM2 [2] and
TCAD simulation on a node, fully utilizing both to the drain of the off-state NMOS transistor. the surface of the structure where an ion will
Geant4-based codes such as MRED [3][4].
processors and all available memory on that impact the silicon. The Sentaurus Workbench
The increase in obtainable computing power Although many of the simulations use the
node for a single simulation. This provides software package allows us to set up these
per cost over recent years enables problems heavy ion statement inside the Sentaurus
a significant speedup in simulation time, complex matrices easily, to interface with the
of much larger computational complexity to be Device simulator, we have developed an
compared to running the same simulation on ACCRE computing cluster, and to utilize fully
examined using such simulations. alternative method of depositing charge
a single processor. the available processing power. This permits
In this article, a single-event simulation using the physical model interface (PMI) to many jobs to be run simultaneously, rather
methodology based on the use of the TCAD Device Simulation Sentaurus. Monte Carlo–based codes (such than one after another, greatly enhancing data
Sentaurus Version Z-2007.03 tool suite As noted, the small size and proximity of as Geant4) can provide a realistic distribution collection and simulation performance.
is presented. To fully characterize SEEs, a multiple devices requires the modeling of

TCAD News June 2007 


TCAD News
Currently, all of the nodes on ACCRE consist significant amounts of computing power. Figure 3. References
of dual processors. Parallelization of the device TCAD Sentaurus Version Z-2007.03 gives Representation of [1] P. E. Dodd and L. W. Massengill, “Basic Mechanisms and
solver allows the use of both processors and users the ability to design and build these charge generated Modeling of Single-Event Upset in Digital Microelectronics,” IEEE
by a Monte Carlo– Transactions on Nuclear Science, vol. 50, no. 3, pp. 583–602,
all the memory on a node, reducing the time for cells, and provides the flexibility needed to 2003.
based code in which
each simulation by up to 41%. Accounting for integrate into a high-performance computing an ion interacted
[2] P. C. Murley and G. R. Srinivasan, “Soft-error Monte Carlo
modeling program, SEMM,” IBM Journal of Research and
hit location, incident angle, ion species, and cluster environment such as ACCRE, for a with materials above Development, vol. 40, no. 1, pp. 109–118, 1996.
energy, characterization of the single event comprehensive characterization of complex the active silicon and [3] S. Agostinelli et al., “Geant4—a simulation toolkit,” Nuclear
response of the SRAM cell may involve more physical phenomena such as single event showered charge Instruments and Methods in Physics Research A, vol. 506, no. 3,
pp. 250–303, 2003.
than 100 simulations that take 4–5 days each effects. into the device. The
[4] C. L. Howe et al., “Role of Heavy-Ion Nuclear Reactions
to complete on a single processor; the time output of the Monte
About ISDE Carlo code was
in Determining On-Orbit Single Event Error Rates,” IEEE
savings obtained by using the multiprocessor Transactions on Nuclear Science, vol. 52, no. 6, pp. 2182–2188,
ISDE is the applied research division of the used as input to the 2005.
capability are significant.
Vanderbilt University School of Engineering Sentaurus Device [5] K. M. Warren et al., “The Contribution of Nuclear Reactions to
Heavy Ion Single Event Upset Cross-Section Measurements in
Conclusion Radiation Effects Group, which is the largest
simulation.
a High-Density SEU Hardened SRAM,” IEEE Transactions on
Nuclear Science, vol. 52, no. 6, pp. 2125–2131, 2005.
The high level of integration associated with program of its kind in the United States. ISDE
[6] For more information, go to <http://www.accre.vanderbilt.edu/>,
scaled devices requires multiple-device studies radiation effects in microelectronics May 2007.
3D simulations to characterize single event equipment by leveraging a combination of [7] O. A. Amusan et al., “Charge Collection and Charge Sharing in
effects. Such simulation capabilities allow experienced people, custom-developed Figure 4. Top view of a 130 nm CMOS Technology,” IEEE Transactions on Nuclear
Science, vol. 53, no. 6, pp. 3253–3258, 2006.
the prediction of the performance of design software, commercially available software, six-transistor SRAM
[8] D. R. Ball et al., “Simulating Nuclear Events in a TCAD Model
variants operating in different radiation and the Vanderbilt University ACCRE high- cell; X indicates the of a High-Density SEU Hardened SRAM Technology,” IEEE
environments. However, these simulations performance computing facility. locations where Transactions on Nuclear Science, vol. 53, no. 4, pp. 1794–1798,
heavy ions with 2006.
are very complicated and can demand
varying LETs will
strike the device.

Impact of Gettering Effects in Solar Cells


In 2005, the photovoltaic market exceeded Plekhanov et al. developed a set of equations 10-2

US$10 billion, showing an exponential annual to describe the gettering of the impurities C,


growth of 30%. Consequently, the shortage of taking into account the decreasing size of
Shockley–Read–Hall Lifetime [s]

10-3
silicon feedstock has forced cell manufacturers metal precipitates C* in silicon:
to look for new sources. To satisfy the market
2 10-4
in the short-term to mid-term, extending ∂C ∂C
+ 4πrρD (C *– C)
Gettering Time [minute]
feedstock to low-quality materials such as = D 10
∂t ∂x 2 20
solar-graded silicon or thin film techniques 10-5
30
40
is feasible and has been widely discussed.
where D is the diffusivity of the impurity, r is
These approaches require a detailed 10-6
the radius of the metal precipitate, and ρ is the
understanding of not only the carrier transport
precipitate density.
mechanisms but also process physics,
10-7 Figure 2. Spatially varying SRH lifetimes
namely, diffusion and gettering processes. Sentaurus Process allows users to define new 0 20 40 60 80 100
Depth [µm] for the device simulation.
With its comprehensive capabilities in device species in silicon and to define new equations
and process simulation, TCAD can provide for the diffusion, segregation, and reactions of
solar cell engineers with valuable insights to these new species as simple text strings. For In the next step, the trap distribution passes propagation method, and the finite-difference
harness the last percentage of cell efficiency. example, the following line defines the partial to the device simulator Sentaurus Device. time-domain full-wave Maxwell solver.
differential diffusion-segregation equation for The trap density Ntrap together with a capture
Weber et al. [1] recently successfully Finally, the influence of process variation on
the impurity Fe in silicon: cross section σn translates to a spatially
reproduced Fe gettering experiments in device characteristics is evaluated. Figure 3
boron-doped diffusion processes using varying Shockley–Read–Hall (SRH) lifetime shows the influence of gettering time on solar
Sentaurus Process and Sentaurus Device. In  pdbSetString Silicon Fe Equation \  (see Figure 2): cell efficiency. In this setup, after 40 minutes,
this article, we illustrate the implementation of   “ddt(Fe)-$Dm*grad(Fe)-PrecDissol” all Fe atoms are gettered by the Al rearside,
an aluminum gettering process described by τ SRH, n = 1/Ntrapνthσn resulting in a strong increase of the short-
Plekhanov et al. [2]. circuit current efficiency.
For each time step, Sentaurus Process solves where νth is the thermal carrier velocity.
A crucial material parameter for solar cells to Figure 4 shows the dependency of the
this differential equation and provides the
achieve reasonable efficiency is the minority To calculate the white-light generation, the gettering time on external quantum efficiency
spatial distribution of the species.
carrier lifetime or diffusion length. A high transfer matrix method is used. Sentaurus (EQE). Due to a lower minority lifetime, the
lifetime is achieved by reducing the number of After the reactions and diffusion equations Device offers a variety of different optical EQE is lowered in the red part of the spectrum
recombination centers (traps) in the Si wafer. are set up, the process flow with arbitrary solvers such as raytracing, the beam as the carriers generated at the rear are unable
temperature ramps can be defined. Here,
Therefore, for the successful use of solar- to reach the p-n junction.
a 1D simulation with a very simple ramp,
graded materials, it is essential to consider 18
References
namely, a constant temperature at 900°C
defect engineering in the design of the
for four different gettering times (10, 20, 30, 17 [1] T. Weber et al., “Numerical Simulation of Gettering and
fabrication process. In particular, an optimized Recombination in Iron-Contaminated Boron Emitters,” in
and 40 minutes) is investigated. The rear of
design of gettering processes, which reduce Proceedings of the 21st European Photovoltaic Solar Energy
Efficiency [%]

16
the 100-μm thick silicon wafer is covered by Conference (EUPVSEC), Dresden, Germany, September 2006.
the amount and impact of impurities present
Al (at a depth of 100 μm). The main result of 15 [2] P. S. Plekhanov et al., “Modeling of gettering of precipitated
in the Si wafer, is vital to obtain high cell impurities from Si for carrier lifetime improvement in solar
the process simulation is the trap distribution cell applications,” Journal of Applied Physics, vol. 86, no. 5,
efficiencies. 14
shown in Figure 1. In addition to the trap pp. 2453–2458, 1999.
Aluminum gettering uses the fact that, distribution, the emitter doping profile can 13
above the eutectic temperature of 577°C, be modeled for use in subsequent device 12
the solubility of metals in Al is very high simulations, but this is not discussed further 0 20 40 60
(1021 cm–3) compared to their solubility in in this article. Gettering Time [minute]
Si (1017 cm–3). This provides a tremendous Figure 3. Dependency of cell efficiency on
driving force for metal atoms to segregate into gettering time.
the Al or Al–Si liquid layer. As the segregation
process occurs simultaneously with the
impurity diffusion, the gettering process can
be described by: 1
1013
• A segregation equation at the Al–Si material
External Quantum Efficiency [1]

boundary. 0.8
Traps [cm-3]

• A diffusion equation for the impurity diffusion 1012


Gettering Time [minute]
10
in bulk silicon. 20 0.6
30
40
• Reaction terms for cluster dissolution and 1011
Gettering Time [minute]
formation if impurity clusters such as metal 0.4 10
precipitates are taken into account in the 20
1010 30
model. 40
0 20 40 60 80 100 0.2
Depth [µm]
Basically, for impurity gettering, the same
physics can be applied as for dopant Figure 1. Depth-dependent trap distribution in die 400 600 800 1000 Figure 4. Influence of gettering time
diffusion. silicon wafer for different gettering times. Wavelength [nm] on EQE.

 TCAD News June 2007


TCAD News

Simulation of 4H-SiC Vertical Junction FET in Sentaurus Device


Introduction Another key aspect of exploring a new Source
Vg = Simulations (Measurements)
Vg = 2.954 V (5.0 V)
0.3 Measured

Silicon carbide (SiC) has long been semiconductor technology is understanding Simulated

recognized as a superior semiconductor for discrepancies between theoretical projections 0.25


Vg = 2.936 V (4.5 V)

high-power and high-temperature applications and experimental results. The challenges Gate Gate Vg = 2.914 V (4.0 V)
0.2
faced by SiC MOSFETs provide an important

Drain Current [A]


in view of its high breakdown electric field
and excellent thermal conductivity. Since the illustration of this point. Despite ongoing 0.15
Vg = 2.877 V (3.5 V)

pioneering work of Tairov and Tsvetkov [1] improvements, the inversion layer mobility is Vg = 2.781 V (3.0 V)

who developed the modified seed sublimation still too low for commercial-grade devices. 0.1

growth process that spearheaded today’s TCAD simulations suggest that a high number 0.05
Vg = 2.500 V (2.5 V)

SiC substrate technology, the industry of interface traps can explain the experimentally Vg = 0.000 V (0.0 V)

has improved steadily the quality, size, and extracted inversion layer mobility [7]. On the 0
0 1 2 3 4 5

cost of SiC substrates, all of which are key other hand, oxide reliability in SiC MOSFETs Drain Voltage [V]

manufacturability considerations in any is a topic of concern when targeting high- Figure 3. Measured (points) and simulated (lines)
semiconductor technology. voltage and high-temperature applications. Ids–Vds characteristics of VJFET. Gate voltages
SiC MOSFET design can lead to electric in parentheses are the actual gate voltages. The
A major quality concern has been the so-called fields in the oxide substantially higher than in discrepancy is due to gate contact resistance,
micropipe defects that are considered to be silicon devices, which combined with a lower which is not explicitly considered in the
associated with screw dislocations and to injection barrier for carriers due to the higher simulation [9].
align themselves along the c-axis of the crystal. band gap of SiC can lead to poor reliability. As 4H-SiC Measurement
Since a single micropipe defect in the device a consequence of these remaining challenges, 100
Impact Ionization Simulation

active area is sufficient to degrade or destroy SiC oxide-free power-switching devices have
the device, these defects have hindered the been investigated recently. An example is the Drain 80

Drain Current [A/Cm2]


realization of large-area power devices [2]. vertical junction field effect transistor (VJFET)
Over the last several years, significant progress Figure 2. Simulation mesh of VJFET. Inset shows 60
discussed in the next section. mesh refinement surrounding the critical regions
has been made in reducing micropipe defects,
Simulation of 4H-SiC VJFET at the bottom of the vertical channel. 40
and 100-mm diameter substrates are now
commercially available. While the substrate TCAD simulations rely on physical models 20

cost is approximately an order of magnitude describing the operational phenomena and Figure 2 shows the meshed VJFET structure. 0
higher than silicon, SiC technology has model parameters calibrated to the process The inset shows a finely meshed p-n junction 0 500 1000 1500 2000
Drain Voltage [V] at Vg = 0 V
already demonstrated commercial feasibility in and materials used to fabricate the devices. region and parts of the vertical channel. Such
high-voltage Schottky barrier diodes (SBDs), In a previous article, we compiled the key a refinement is needed to resolve properly Figure 4. Measured and simulated breakdown
and new devices and applications are being material and model parameters for the 4H- the space-charge regions and to capture voltage.
considered [3]. SiC polytype [8]. In this article, we perform accurately the impact ionization effects
simulations of a 4H-SiC trenched-and- References
Emerging Applications for SiC for breakdown simulation. These meshing [1] Y. M. Tairov and V. F. Tsvetkov, “Investigation of Growth Processes
Electronic Devices implanted VJFET, a type of device that holds constraints can be easily implemented in of Ingots of Silicon Carbide Single Crystals,” Journal of Crystal
commercial promise. The device structure and Sentaurus Structure Editor using either Growth, vol. 43, no. 2, pp. 209–212, 1978.
The recent commercial interest in hybrid experimental data are from Zhao et al. [9]. [2] P. G. Neudeck and J. A. Powell, “Performance Limiting Micropipe
its graphical user interface or its powerful
electric vehicles has extended the Defects in Silicon Carbide Wafers,” IEEE Electron Device Letters,
scripting capabilities. vol. 15, no. 2, pp. 63–65, 1994.
opportunities for electronic content in
Source [3] P. Friedrichs and R. Rupp, “Silicon Carbide Power Devices
automobiles. The high temperature and 0 Electrical simulations are performed with - Current Developments and Potential Applications,” in 11th
harsh environmental conditions prevalent in Sentaurus Device using physical models European Conference on Power Electronics and Applications
(EPE), Dresden, Germany, September 2005.
automotive applications provide a natural Gate Gate incorporating:
2 [4] R. Kelley, M. S. Mazzola, and V. Bondarenko, “A Scalable SiC
medium for SiC relative to lower-temperature • Doping-dependent and temperature- Device for DC/DC Converters in Future Hybrid Electric Vehicles,”
in Twenty-First Annual IEEE Applied Power Electronics
rating semiconductors such as silicon. One dependent Shockley–Read–Hall (SRH) Conference and Exposition (APEC), pp. 460–463, March 2006.
of the most intriguing possibilities is the 4 recombination and Auger processes. [5] Y. Sugawara et al., “12.7kV Ultra High Voltage SiC Commutated
simplification of cooling requirements – for Gate Turn-off Thyristor: SICGT,” in 16th International Symposium
example, the elimination of secondary cooling • Doping-dependent mobility models with on Power Semiconductor Devices & ICs (ISPSD), Kitakyushu,
Japan, pp. 365–368, May 2004.
6 high-field velocity saturation effects.
loops necessary to maintain existing silicon-
Y [µm]

[6] X. Li et al., “Multistep junction termination extension for SiC power


Doping Concentration [cm-3]
based devices at 85ºC base plate temperature 6.0e+18
• Impact ionization (Okuto–Crowell model). devices,” Electronics Letters, vol. 37, no. 6, pp. 392–393, 2001.

– thereby reducing costs [4]. In this scenario, 8 [7] H. Linewih and S. Dimitrijev, “Channel-Carrier Mobility Parameters
5.8e+15 Sentaurus Device accounts for the anisotropic for 4H SiC MOSFETs,” in Proceedings of the 23rd International
the higher cost of SiC devices relative to Si Conference on Microelectronics (MIEL), Niš, Yugoslavia,
5.5e+12 properties of 4H-SiC resulting from the
devices is offset by the lower system costs. pp.  425–430, May 2002.
10 -4.7e+13 hexagonal crystal structure. Table 1 lists [8] “TCAD Simulation of Silicon Carbide Devices: Part I. Models and
Another high-visibility, potential application -5.0e+16 some important model parameters used in the Parameters,” TCAD News, pp. 3–5, September 2006.
is improving power grid efficiency. Wind and -5.2e+19 4H-SiC simulations for mobility and impact ionization. [9] J. H. Zhao et al., “3.6 mΩcm2, 1726 V 4H-SiC normally-off
solar energy sources produce direct current 12 trenched-and-implanted vertical JFETs and circuit applications,”
Simulation results for a single-cell VJFET with IEE Proceedings – Circuits, Devices and Systems, vol. 151,
and rely on inverter modules for conversion no. 3, pp. 231–237, 2004.
Drain an active area of 320 µm x 293 µm, showing
to alternating current used by the power grid. [10] W. J. Schaffer et al., “Conductivity Anisotropy in Epitaxial 6H and
Idrain versus Vdrain characteristics for various 4H SiC,” in Materials Research Society Symposia Proceedings,
Current inverter module technology is based 0 2 4 6 vol. 339, pp. 595–600, April 1994.
gate biases, are presented in Figure 3.
on silicon devices and operates at 90–96% X [µm] [11] T. T. Mnatsakanov et al., “Universal Analytical Approximation
efficiency. Though this efficiency seems high, Figure 4 shows the breakdown characteristics of the Carrier Mobility in Semiconductors for a Wide Range of
Temperatures and Doping Densities,” Semiconductors, vol. 38,
SiC devices offer the potential to increase the Figure 1. Device structure and doping profile of for the same device, as well as the region no. 1, pp. 56–60, 2004.
efficiencies of inverter modules to the 95–98% VJFET. of the device undergoing acute avalanche [12] T. Hatakeyama et al., “Physical Modeling and Scaling Properties
range, which is significant. An example of the generation. The simulated results show good of 4H-SiC Power Devices,” in International Conference on
Simulation of Semiconductor Processes and Devices (SISPAD),
potential for SiC in this application is the The VJFET structure allows the realization of agreement with experimental data. Tokyo, Japan, pp. 171–174, September 2005.
recent demonstration of a SiC commutated ‘normally off’ devices, which are desirable for
gate turn-off thyristor (GTO) with a blocking fail-safe protection. The device structure is
voltage of 12.7 kV [5]. defined in Sentaurus Structure Editor and is
shown in Figure 1. The device is created on Table 1. Important model parameters used in the simulations for mobility and impact ionization.
Motivation for Simulating SiC Devices the Si face of the 4H-SiC material and has Model Parameter Coefficients
As with other maturer semiconductor an n- vertical channel and drift region with a
Mobility
technologies, the early stages of process doping concentration of 6.5 x 1015 cm–3. The
definition, device design, and optimization p+ gate regions, with a doping concentration For Electrons For Holes Unit Reference

can greatly benefit from TCAD simulation. of 1.0 x 1018 cm–3, are created on the MuMax 947 124 cm2/(Vs) [10]
Arguably, the motivation for TCAD simulation sidewalls of the trenches. The p++ contact Anisotropic Mobility
of SiC devices is even higher than in other regions have a doping concentration of 5.0 x
MuMax 700 114 cm2/(Vs) [7][11]
technologies since SiC substrate cost is still 1019 cm–3.
Impact Ionization G = alpha * exp( -beta / E)
relatively high, making large-scale experimental The n+ substrate, above the drain contact,
wafer splits very costly. Moreover, the is doped with a concentration of 6.0 x
alpha 2.10e+07 2.96e+07 1/cm [12]
exceptional material attributes of SiC provide 1018 cm–3, and the n+ source region has a beta 1.70e+07 1.60e+07 V/cm
fertile ground for exploring truly novel device concentration of 1.0 x 1018 cm–3. The trench Anisotropic Impact
structures that transcend the operational region comprises a 50-nm thick thermal Ionization
principles and range of silicon-based devices. oxide, followed by a 200-nm thick silicon alpha 1.76e+07 3.41e+08 1/cm [12]
Since many of these device structures want nitride layer, and the remaining portion is filled beta 3.30e+07 2.50e+07 V/cm
to exploit the high breakdown field in SiC to with oxide. The vertical channel is designed to
realize high-blocking voltages, careful design have an opening of 0.63 µm, and the blocking
and simulation of junction terminations are layer or the n- drift region is designed to have
essential [6]. a thickness of approximately 9.4 µm.

TCAD News June 2007 


TCAD News

TCAD Events 2007


Conferences and Trade Shows

USA Europe

July 16–20 September 11–13


SEMICON West 37th European Solid-State Device
San Francisco, California, USA Research Conference (ESSDERC) /
33rd European Solid-State Circuits
Conference (ESSCIRC)
July 23–27 Munich, Germany
Nuclear and Space Radiation Effects
Conference (NSREC)
September 25–27
Honolulu, Hawaii, USA
12th International Conference
on Simulation of Semiconductor
September 17–21 Processes and Devices (SISPAD)
BACUS Photomask Technology TU Wien, Vienna, Austria
Monterey, California, USA

September 24–27 Asia-Pacific


7th International Conference on
Numerical Simulation of Optoelectronic September 7–14
Devices (NUSOD)
TCAD Asia-Pacific Seminar Series
University of Delaware, Newark, Delaware,
USA September 7 Hsinchu
September 10 Singapore

September 30 – October 3 September 12 Seoul

Bipolar/BiCMOS Circuits and September 14 Shanghai


Technology Meeting (BCTM)
Boston, Massachusetts, USA

December 10–12
International Electron Device Meeting
(IEDM)
Washington, DC, USA

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