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9th International Symposium on Quality Electronic Design

Statistical Data Stability and Leakage Evaluation of


FinFET SRAM Cells with Dynamic Threshold Voltage
Tuning under Process Parameter Fluctuations
Zhiyu Liu, Sherif A. Tawfik, and Volkan Kursun
Department of Electrical and Computer Engineering
University of Wisconsin – Madison
Madison, Wisconsin 53706 - 1691
Abstract – A new six transistor (6T) FinFET static memory effects, thereby suppressing the subthreshold leakage current.
cell with dynamic access transistor threshold voltage The suppressed short-channel effects and the enhanced gate
tuning is evaluated in this paper for statistical power and control over the channel area permit the use of a thicker gate
stability distributions under process parameter variations. oxide in a FinFET as compared to a conventional single-gate
The independent-gate (IG) FinFET SRAM cell activates transistor. The gate oxide leakage current is thereby
only one gate of the double-gate data access transistors significantly reduced in the FinFET technologies. FinFET is
during a read operation. The disturbance caused by the currently the most promising device candidate for continuing
direct data access mechanism of the standard 6T SRAM the CMOS technology scaling process to the 32nm technology
cell topology is significantly reduced by dynamically node and beyond [1]-[2].
increasing the threshold voltage of the access transistors. The FinFET technology provides a unique design flexibility
All the transistors in the presented SRAM cell are sized where the multiple gates can be tied or independently biased
minimum without producing any data stability concerns. [3]. An independent-gate (IG) FinFET resembles two single-
The average read static-noise-margin of the statistical gate-MOSFETs in parallel, sharing a common thin body. A
samples with the independent gate bias technique is 82% single IG-FinFET is, for instance, sufficient to implement
higher as compared to the standard tied-gate FinFET either the pull-up network of a two-input NAND gate or the
SRAM cells under process variations. Furthermore, the pull-down network of a two-input NOR gate [5]. Compact
IG-FinFET SRAM circuit reduces the average leakage CMOS circuits with reduced number of transistors based on
power and the cell area by up to 53.3% and 17.5%, IG-FinFET technologies have been reported in the literature
respectively, as compared to the standard tied-gate [4]-[5].
FinFET SRAM circuits sized for comparable data stability Lowering of voltages and smaller device dimensions lead to
in a 32nm FinFET technology. a significant degradation in SRAM cell data stability with the
scaling of CMOS technology. Maintaining the data stability of
Index Terms – Cache memory, static noise margin
SRAM cells is expected to become increasingly challenging
distribution, robust operation, active power, standby
as the device dimensions are scaled to the sub-45nm regime.
power distribution, double gate MOSFET, process
In addition to the data stability issues, SRAM arrays are also
variations.
an important source of leakage due to the enormous number of
I. INTRODUCTION transistors in the memory caches. The development of a new
The channel length of the conventional single-gate SRAM cell that can provide higher data stability and lower
transistors has been scaled from 2μm to 45nm over the past 20 leakage power characteristics with the emerging FinFET
years. The subthreshold and gate-dielectric leakage currents technologies is highly desirable.
and the enhanced device sensitivity to parameter fluctuations A new six-transistor (6T) SRAM cell exploiting the unique
are currently the primary barriers against further device threshold voltage modulation aspect of the independent-gate
scaling [1]. As the channel length of a conventional single- FinFETs for providing lower power consumption, higher
gate-MOSFET is reduced to the nanometer scale, the drain memory integration density, and enhanced data stability is
potential begins to strongly influence the channel potential, presented in this paper. The new IG-FinFET SRAM cell
thereby causing significant subthreshold leakage current. provides two separate data access mechanisms for the read
Furthermore, the gate dielectric thickness has been reduced to and write operations. During a read operation, the threshold
a point where the power drained by the gate tunneling current voltage of the access transistors is dynamically increased,
is comparable to the power consumed due to switching thereby suppressing the coupling between the data storage
activity [1]. nodes and the bitlines. The average read SNM of the new IG-
The multi-gate FinFETs offer significant advantages for FinFET SRAM cell is thereby enhanced by up to 82% as
suppressing the subthreshold and the gate dielectric leakage compared to the standard tied-gate FinFET SRAM cells under
currents in the deeply scaled nanometer technologies [1]-[2]. process parameter variations. Due to the enhanced data
The structure of a FinFET is shown in Fig. 1. The two stability, all of the six transistors of the new IG-FinFET
electrically coupled gates (front and back gates in Fig. 1b) and SRAM cell are sized minimum without causing any reliability
the thin silicon body of the FinFET reduce the short-channel concerns. The average leakage power consumption and area

0-7695-3117-2/08 $25.00 © 2008 IEEE 305


DOI 10.1109/ISQED.2008.97

Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 10:42 from IEEE Xplore. Restrictions apply.
of the IG-FinFET SRAM cell are thereby reduced by up to The maximum drain current produced at the DGM is therefore
53.3% and 17.5%, respectively, as compared to the 6T tied- 2.6 times higher as compared to the SGM, as illustrated in Fig.
gate FinFET SRAM cells. 2. The unique Vt modulation aspect of IG-FinFETs through
The paper is organized as follows. The FinFET operation is selective gate bias is exploited in this paper to dynamically
described in Section II. The new IG-FinFET SRAM cell is tune the read and write strength of the access transistors in
presented in Section III. Data stability, power, and delay SRAM circuits.
characteristics of the standard tied-gate and the new IG-
FinFET SRAM cells are compared under process parameter
variations in Section IV. Finally, some conclusions are offered
in Section V.

Fig. 2. Drain current density of an n-type IG-FinFET. VDS = 0.8V.

III. SRAM CELLS


The design considerations for the reliable operation of 6T
SRAM circuits with the standard single-gate MOSFETs and
the emerging FinFETs are provided in this section. The tied-
Fig. 1. The multi-gate FinFET structure. (a) 3D structure of the one-fin
FinFET. (b) Cross sectional top view of the FinFET.
gate FinFET SRAM cells are presented in Section III-A. The
new IG-FinFET SRAM circuit is described in Section III-B.
II. FINFET TECHNOLOGY A. Standard Tied-Gate FinFET SRAM Cells
The physical and electrical characteristics of the n-type and The operation of a 6T FinFET SRAM cell is similar to a
the p-type FinFETs are presented in this section. The FinFETs conventional 6T single-gate-FET SRAM circuit [6]. Similar to
used in this paper have a symmetrical structure, as shown in the SRAM circuits with standard single-gate MOSFETs, there
Fig. 1. The physical parameters used for MEDICI simulations are strict constraints on the sizing of transistors to be able to
are listed in Table I [8]. The minimum channel length and the maintain the data stability and functionality of a 6T SRAM
fin height are 32nm. VDD is 0.8V. cell in a FinFET technology. Despite the similarity of the
TABLE I design constraints, however, the transistor sizes from a
DEVICE TECHNOLOGY PARAMETERS conventional single-gate-FET CMOS technology can not be
Parameter Value directly transferred to a FinFET technology due to the
Channel length (Lgate) 32nm
quantization of the FinFET width. A tied-gate FinFET SRAM
Effective channel length (Leff) 25.6nm
Fin thickness (Tfin) 8nm cell with parameterized sizing (N) for the pull-down
Fin height (Hfin) 32nm transistors is illustrated in Fig. 3.
Oxide thickness (Tox) 1.6nm
Channel doping 1015cm-3
Source / Drain doping 2 x 1020cm-3
Gates work function (NMOS) 4.5eV
Gates work function (PMOS) 4.9eV

The width of a FinFET is quantized due to the vertical gate


structure. Since the fin height (Hfin) is fixed (determined by
the technology), multiple parallel fins are utilized to increase
the width of a FinFET. The total physical transistor width of
an IG-FinFET with n parallel fins is
WIG-total = n × (2 × Hfin). (1)
Fig. 3. The tied-gate FinFET SRAM cell. The size of each transistor is given
An IG-FinFET provides two different active modes of as (number of fins × Hfin) / Lgate. Hfin: fin height. Lgate: channel length.
operation. In the Dual Gate Mode (DGM), the two gates are
biased with the same signal to control the formation of a Three tied-gate FinFET SRAM cells with different sizes are
considered in this paper. All of the six transistors in the first
conducting channel. Alternatively, in the Single Gate Mode
FinFET SRAM cell (SRAM-DG-1) are sized minimum (one
(SGM), one gate is biased with the input signal to induce fin, N = 1). The widths of the pull-down transistors in the
channel inversion while the other gate is disabled. The cross-coupled inverters of the second SRAM cell (SRAM-
variation of the drain current of an n-type IG-FinFET for two DG-2) are double sized (two fins, N = 2) to enhance the data
different operating modes is shown in Fig. 2. The threshold stability as compared to SRAM-DG-1. The widths of the pull-
voltage (Vt) is lowered at the DGM as compared to the SGM. down transistors in the cross-coupled inverters of the third

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SRAM cell configuration (SRAM-DG-3) are triple sized Due to the enhanced data stability, all six transistors of the
(three fins, N = 3) for further enhancing the data stability. This IG-FinFET SRAM cell are sized minimum. The cell area is
standard approach of achieving higher data stability through reduced as compared to the tied-gate FinFET SRAM cells
transistor sizing, however, comes at a significant cost of which need to be sized significantly larger for similar data
increased active and standby mode power and larger cell area.
stability. The memory integration density of the SRAM-IG
B. New IG-FinFET SRAM Cell circuit is, therefore, significantly enhanced. Furthermore, the
A six transistor SRAM cell based on an IG-FinFET leakage power consumption of the SRAM-IG is suppressed
technology [9], [10], [14] is presented in this section for since the total effective transistor width that produces the
simultaneously reducing the active and standby mode power leakage current is reduced as compared to the tied-gate
consumption while enhancing the data stability and the FinFET SRAM cells.
integration density. The IG-FinFET SRAM cell is shown in
Fig. 4. All the transistors have single fin (minimum width). IV. SIMULATION RESULTS
The transistors in the cross-coupled inverters are tied-gate The read stability, active mode power, speed, and leakage
FinFETs. Alternatively, the access transistors are independent- power of the three tied-gate FinFET SRAM cells and the IG-
gate FinFETs. An IG-FinFET has a higher threshold voltage FinFET SRAM cell (SRAM-IG) are compared in this section.
(high-Vt) in the SGM as compared to the DGM as described The three tested tied-gate FinFET SRAM cells are: SRAM-
in Section II. The unique Vt modulation aspect of IG-FinFETs DG-1, SRAM-DG-2, and SRAM-DG-3 as described in
through selective gate bias is exploited with the new technique Section III-A. The transistor sizing of the SRAM cells are
by dynamically tuning the read and write strength of the shown in Figs. 3 and 4. Active mode data are measured at
access transistors in SRAM circuits. One gate of each access 70°C. Leakage power consumption is measured at both 70°C
transistor is controlled by a read/write signal (RW). The other and 27°C in order to evaluate the effectiveness of the
gate of each access transistor is controlled by a separate write presented technique for suppressing leakage over the entire
signal (W), as shown in Fig. 4. range of a typical memory temperature spectrum. The leakage
The operation of the IG-FinFET SRAM cell is as follows. reduction and the data stability enhancement provided by the
Both RW and W signals are maintained low in an un-accessed SRAM-IG are verified with the statistical data produced under
SRAM cell. The two access transistors are cut-off. The data is process parameter variations in a 32nm FinFET technology.
maintained by the cross-coupled inverters whenever a cell is A. Read Stability
not accessed. To start a read operation, RW signal transitions Static noise margin (SNM) is the metric used in this paper
high while W is maintained low. Provided that Node1 stores to characterize the read stability of the SRAM cells. The SNM
“0”, BL is discharged through N3 and N1. Alternatively, is the minimum DC noise voltage that can flip the state of an
provided that Node2 stores “0”, BLB is discharged through SRAM cell [7]. When Node1 of the SRAM cells is maintained
N4 and N2. As compared to the tied-gate FinFET SRAM- at VDD, Node2 rises to a voltage higher than Vgnd due to the
cells, the access transistors N3 and N4 act as high-Vt devices voltage division between the access transistors and the pull-
with weaker current conducting capability during a read down devices of the cross-coupled inverters. The Node2
operation with the independent-gate-bias technique. The voltage and SNM of the different SRAM circuits during a read
intrinsic data disturbance that occurs due to the direct-data- operation are listed in Table II.
read-access mechanism of the 6T SRAM cell topology is The transistors in SRAM-DG-1 and SRAM-IG cells are
thereby significantly suppressed and the read stability is sized identical (W = Wmin for all the transistors). As listed in
enhanced with this technique. Table II, the disturbance induced at Node2 during a read
Alternatively, to start a write operation, both RW and W operation is significantly suppressed by dynamically
transition high. The two access transistors N3 and N4 act as increasing the Vt of the access transistors with the SRAM-IG
strong low threshold voltage (low-Vt) devices. Write ability is as compared to the SRAM-DG-1. The Node2 of SRAM-DG-1
thereby achieved with minimum sized access transistors and SRAM-IG rises to 80mV and 30mV, respectively, during
operating in the DGM. The write speed of an IG-FinFET a read operation. The read SNM of the SRAM-IG is enhanced
SRAM circuit is similar to SRAM-DG-1 with identical by 2× as compared to the SRAM-DG-1 despite the identical
transistor sizing. transistor sizing with the two techniques, as listed in Table II.
TABLE II
READ SNMS AND NODE2 VOLTAGES
SRAM Cell Read SNM (mV) Node2 Voltages (mV)
SRAM-DG-1 120 80
SRAM-DG-2 210 30
SRAM-DG-3 220 20
SRAM-IG 240 30

The pull-down devices of SRAM-DG-2 and SRAM-DG-3


are sized 2× and 3× larger, respectively, as compared to the
Fig. 4. The IG-FinFET SRAM cell. The size of each transistor is given as access transistors for enhanced read stability. SRAM-DG-2
(number of fins × Hfin) / Lgate.
and SRAM-DG-3 therefore experience a smaller voltage

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disturbance at Node2 as compared to SRAM-DG-1 during a unintentional read access to the inactive blocks does not
read operation. SRAM-IG has a similar Node2 voltage produce a data stability problem with the SRAM-DG-2 and
disturbance as compared to SRAM-DG-2 and SRAM-DG-3 the SRAM-DG-3 which are sized for read stability.
(difference less than 10mV), as listed in Table II. SRAM-IG Alternatively, for an interleaved cache architecture with the
however has relatively stronger pull-up strength in the cross- SRAM-DG-1 or the SRAM-IG cells, the unintentionally
coupled inverters as compared to both SRAM-DG-2 and accessed cells in the inactive blocks could lose data during a
SRAM-DG-3, thereby having a stronger immunity against the write operation since the access transistors are fully activated
data disturbance caused by a read access. The read SNM of and the cross-coupled inverters are sized minimum. The
SRAM-IG is 14.3% and 9.1% higher as compared to the read SRAM-IG and the SRAM-DG-1 are, therefore, not suitable
SNMs of SRAM-DG-2 and SRAM-DG-3, respectively. for an interleaved cache architecture.
B. Leakage Power Consumption
The IG-FinFET SRAM cell also lowers the total leakage
power. When an SRAM cell is in the idle mode, the access
transistors are cut-off and the bitlines are charged to VDD. The
WL of the tied-gate FinFET SRAM cells is maintained at
Vgnd. Similarly, both the RW and W signals are maintained at
Vgnd in the idle/unaccessed SRAM-IG cells.
The leakage power consumption of the SRAM cells at 70°C
and 27°C are compared in Fig. 5. The leakage power of an
SRAM cell is determined by the total effective transistor
width that produces the leakage current. In SRAM-DG-1 and
SRAM-IG, the transistors that produce the leakage current
have minimum width. SRAM-DG-1 and SRAM-IG therefore
consume the lowest leakage power. Since SRAM-DG-3 has
the largest total transistor width, SRAM-DG-3 consumes the
highest leakage power in the idle mode. The leakage power
consumed by SRAM-IG is 51.7% and 53.5% lower at 70°C
and 27°C, respectively, as compared to SRAM-DG-3.

Fig. 6. Thin-cell layouts of the FinFET SRAM cells. (a) SRAM-DG-1. Area =
Fig. 5. The normalized leakage power consumptions of the FinFET SRAM 0.23µm2. (b) SRAM-DG-3. Area = 0.28µm2. (c) SRAM-IG. Area = 0.23µm2.
cells at 70°C and 27°C. For each SRAM cell, the leakage power is normalized The area of each SRAM cell is determined by a dotted rectangle. The contacts
with respect to SRAM-DG-1 at the same temperature. that would be shared by the adjacent cells in a memory array are intersected by
the dotted lines for an accurate per-cell area calculation.
C. Area and Application Discussion
The layouts of SRAM-DG-1, SRAM-DG-3, and SRAM-IG D. Active Mode Power and Speed
(with the thin-cell memory layout style [11]-[12]) are shown The parasitic capacitance of the access transistors attached
in Fig. 6. The fin pitch is assumed to be 6 times the fin to the bitlines is extracted for each FinFET SRAM cell based
thickness [2] in the layouts. on the “thin-cell” layouts. The length of the bitlines is
SRAM-DG-3 has the largest area since the pull-down estimated based on the cell layout height. A Π-type RC
transistors in the cross-coupled inverters have three fins. network that represents the bitline parasitics of a 256-bit
SRAM-DG-1 and SRAM-IG have the smallest area. The area SRAM column is attached to the FinFET SRAM circuits. The
of SRAM-IG is 17.5% smaller than SRAM-DG-3. read delay is the time period from the 50% point of the WL
In the interleaved caches, the SRAM cells in each row are (RW in case of the SRAM-IG) low-to-high transition until a
grouped into different blocks (banks). When a row of cells in 200mV voltage difference is developed between BL and BLB.
an active block is selected, the cells in the corresponding row The normalized active mode power and delay of the four
of the inactive blocks are also simultaneously accessed. This FinFET SRAM circuits are shown in Fig. 7. The power and

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delay of each SRAM circuit are normalized to the power and gate length (Lgate), the silicon body thickness (tsi), the fin
delay of SRAM-DG-1. height (Hfin), and the gate oxide thickness (tox) are evaluated.
Lgate, tsi, Hfin, and tox are assumed to have independent normal
Gaussian statistical distributions. Each parameter is assumed
to have a three sigma (3σ) variation of 10% [13]. Monte Carlo
simulations are run to evaluate the read stability and the
leakage power statistical distributions. The distributions of the
read SNM of the FinFET SRAM cells at 70°C are shown in
Fig. 8. The statistical data for the read SNM of the FinFET
SRAM cells are listed in Table III.

Fig. 7. The active mode power and delay of the SRAM circuits. For each
SRAM circuit, the power and delay are normalized with respect to SRAM-
DG-1.

All of the FinFET SRAM cells have a similar bitline length.


SRAM-IG and SRAM-DG-1, therefore, have similar write
power and write delay. Since SRAM-DG-3 has the highest
capacitance at the data storage nodes, the write power and the
write delay of SRAM-DG-3 are 12.8% and 51.2% higher,
respectively, as compared to SRAM-IG. Fig. 8. The statistical distributions of the read SNMs of SRAM-DG-1, SRAM-
DG-3, and SRAM-IG under process parameter variations. T = 70°C.
The pull-down devices of the cross-coupled inverters of
SRAM-DG-2 and SRAM-DG-3 are sized 2× and 3× larger, TABLE III
respectively, as compared to SRAM-DG-1. The read delays of AVERAGE AND STANDARD DEVIATION (SD) OF SNM OF THE
FINFET SRAM CELLS AT 70°C
SRAM-DG-2 and SRAM-DG-3 are therefore 57.1% and
71.4% lower, respectively, as compared to SRAM-DG-1. The Read SNM (mV)
read delay of the SRAM-IG is increased by 57.1% as Average Standard Deviation
compared to the SRAM-DG-1 due to the dynamically SRAM-DG-1 122 9
increased threshold voltage of the access transistors during a SRAM-DG-3 207 3
read operation. SRAM-IG 222 3
The SRAM-IG has the lowest voltage disturbance at the
node which stores “0” during a read operation. The cross- SRAM-IG has the highest average read SNM among all of
coupled inverters of the SRAM-IG, therefore, produce the the FinFET SRAM cells. The average read SNM of the
lowest static DC current during a read access. The read power SRAM-IG is 82% and 7.2% higher as compared to the
consumption of the SRAM-IG is 8.6% lower as compared to SRAM-DG-1 and the SRAM-DG-3, respectively. The read
the SRAM-DG-1. SNM distribution curves of the SRAM-DG-3 and the SRAM-
IG cross at 214mV, as shown in Fig. 8. Read SNMs of 99.7%
E. Process Variations of the samples with the SRAM-IG are higher than 214mV.
Random and systematic fluctuations in the channel length, Alternatively, 98.7% of the statistical samples with the
the silicon body thickness, the fin height, and the gate oxide conventional SRAM-DG-3 have read SNMs lower than
thickness cause variations in the FinFET characteristics. The 214mV.
read stability of a 6T SRAM cell is primarily determined by The distributions of the leakage power consumption of the
the ratio of the current produced by the access transistors and FinFET SRAM cells at 70°C and 27°C are shown in Figs. 9
the NMOS transistors in the cross-coupled inverters. The and 10, respectively. The statistical data for the leakage power
relative strength of the NMOS transistors in the inverters can consumption of the FinFET SRAM cells are listed in Table
vary as compared to the access transistors due to process IV. The leakage power distribution curves of SRAM-DG-3
parameter fluctuations. The read stability, therefore, fluctuates and SRAM-IG cross at 18nW at 70°C, as shown in Fig. 9.
with the process parameters. Furthermore, the subthreshold Leakage power consumption of 99.5% of the samples with the
and gate oxide leakage currents vary with the fluctuations of SRAM-IG technique is lower than 18nW. Alternatively,
the threshold voltage and the gate oxide thickness, thereby 99.5% of the samples with the conventional SRAM-DG-3
inducing variations in the leakage power consumption of the consume leakage power higher than 18nW. The average
SRAM cells. leakage power consumptions of SRAM-DG-3 and SRAM-IG
In this section, read stability and leakage power variations are 25.6nW and 12.5nW, respectively, at 70°C as listed in
of the FinFET SRAM cells due to process fluctuations in the Table IV. A 51.2% and 53.3% average leakage power

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reduction is provided with the SRAM-IG as compared to the Due to the enhanced stability of the stored data, all of the
SRAM-DG-3 based on the statistical data produced under transistors in an IG-FinFET SRAM cell are sized minimum.
process parameter variations at 70°C and 27°C, respectively. The area of the IG-FinFET SRAM cell is, therefore, 17.5%
smaller than a tied-gate FinFET SRAM cell with comparable
data stability.
The leakage power reduction and the read stability
enhancement provided by the IG-FinFET SRAM technique
are evaluated with the statistical data produced under process
parameter variations in a 32nm FinFET technology. The
average leakage power consumption of the IG-FinFET SRAM
circuits is reduced by 51.2% and 53.3% at 70°C and 27°C,
respectively, as compared to the tied-gate FinFET SRAM
circuit with comparable data stability. Furthermore, the
average read SNM of the IG-FinFET SRAM cell is enhanced
by up to 82% as compared to the standard tied-gate FinFET
SRAM cells under process parameter variations.
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