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Ultra-Low Power 90nm 6T SRAM Cell for Wireless Sensor

Network Applications
D. Ho1, K. Iniewski2, S. Kasnavi2, A. Ivanov1, S. Natarajan3
1 2 3
Dept. of Elec. and Comp. Engineering Dept. of Elec. and Comp. Engineering Emerging Memory Technologies Inc.
University of British Columbia University of Alberta, Ottawa, Canada
Vancouver, Canada Edmonton, Canada

Abstract—This paper presents a comparative study of technology to find an optimal design for ultra-low power
leakage reduction techniques applied to a 90nm 6T SRAM to wireless sensor applications primarily from a power
find an optimal design for ultra-low power wireless sensor perspective. The techniques include the use of multi-VT
applications. A 4-Kb SRAM implemented with the proposed transistors, scaling supply voltage, sizing above minimum
techniques has a leakage as low as 26.5nA in the idle mode, a
gate length, and implementing sleep transistors. The leakage
189X improvement over a memory without applying such
techniques. reduction ability and the corresponding sacrifice in SNM of
each technique are compared. Section II examines major
sources of leakage present in the 6T cell. Section III
I. INTRODUCTION describes the impact of the supply voltage and the transistor
The emerging Wireless Sensor Network technologies are threshold values on leakage. Section IV analyzes the effect
facilitating novel applications in health monitoring, of transistor sizing on leakage. Section V investigates the
industrial monitoring and security surveillance. The small effectiveness of sleep transistors in leakage reduction,
physical dimensions of wireless sensor nodes often restrict followed by a comparison and conclusion in Section VI.
the energy source to a small battery. The limited energy
II. 6T SRAM LEAKAGE ANALYSIS
consumption requirement demands for ultra-low power
sensing, processing and communication. Ultra-low power The standard 6T SRAM cell is shown inside the box in
approaches at the device, circuit, system and network level Figure 1, with M2 and M4 normally connected to ground
have been proposed for reliable implementations of sensor rather than to Msleep (Msleep included only in Section V
networks [1-3]. simulations). M5 and M6 are the access transistors for read
SRAM, being a key component of the processing system and write operations. M1-4 form a cross coupled inverter
of sensor nodes, has to satisfy the low-power requirement as with positive feedback to statically retain data.
well. As feature size shrinks, the key component of power
consumption will be leakage [4]. In the past 5 years, there
has been significant effort to find ways to reduce leakage,
amongst them are supply voltage scaling [5, 6], idle mode
implementation [7-9], and body biasing [5, 10]. While the
existing solutions provide good leakage reduction, they
mostly target microprocessor cache, with circuit
performance being a critical parameter to be optimized. This
limits the extent to which leakage reduction techniques can
be applied, rendering them ineffective for the ultra-low
power domain. In a sensor node, there are two modes of
operation, namely data processing and idle. Since the
memory spends almost its entire operating time in the idle
mode, it is critical to vastly reduce leakage while retaining Figure 1 The standard 6T SRAM cell with the addition of a
data. With the primary function of retaining data and speed
sleep transistor.
being only a secondary requirement, good cell stability,
reflected by a high Static Noise Margin (SNM), becomes a
To clarify the leakage sources in the cell, assume V1 and
critical design objective for a SRAM used in a wireless
V2 are biased to a logic zero and a logic one respectively.
sensor application. Thus M1 and M4 are turned off. M1 and M4 give rise to the
This paper compares leakage reduction techniques leakage currents IS1 and IS2 respectively. IS1 and IS2 form the
applied to the 6T SRAM cell implemented in a 90nm supply leakage as they drain charges from the supply grid.

This research was funded by Canadian Microelectronics Corporation


(CMC) and Natural Science and Engineering Research Council of
Canada (NSERC).
The access transistors are off when the wordline (WL) is not 10000

selected (idle mode). Since the bitlines are precharged to


VDD when the memory is idle, M5 and M1 both leak. 1000 Supply Lk. (LVT)
However, since V2 and BIT’ are high, resulting in a very

L eakag e (p A )
Bitline Lk. (LVT)
small voltage difference between the drain and source of 100 Supply Lk. (SVT)

M6, leakage through M6 is typically only in hundreds of Bitline Lk. (SVT)

femto-amperes. Hence it can be reasonably ignored. The 10


Supply Lk. (HVT)
Bitline Lk. (HVT)
leakage of M5 (IB1) forms the bitline leakage. Based on the
above definition of leakage components, applying leakage 1
reduction techniques to the PMOS transistors reduces 0.2 0.4 0.6 0.8 1 1.2 Vdd (V)
supply leakage and doing the same for the access transistors
(a)
reduces bitline leakage. Simulations confirm that applying
leakage reduction techniques to the inverter pull-down 500
network reduces both leakage components. 450

In this paper, we study the stability of the cell by 400


350
measuring the SNM. SNM is the minimum amount of noise

SNM (mV)
300
250
that can corrupt the data stored in the cell. For SNM 200
HVT
simulations, noise sources are added to the inputs of both 150
SVT
100
inverters with the worst case polarity as shown in Figure 2 50 LVT

[5]. Simulations are performed at 25 ºC and all transistors 0


0.2 0.4 0.6 0.8 1 1.2
have L = 100nm, which is the minimum feature size for the Vdd (V)

90nm technology used. The access transistors have W = (b)


140nm and the inverters have Wp/Wn = 180nm/200nm for
correct write and read operations [5]. Figure 3 Leakage reduction achieved by supply voltage
scaling and high threshold transistors: (a) Leakage reduction
by supply voltage scaling, (b) cell stability trade off in terms
of lowered SNM. Results are shown for high, standard, and
low threshold transistor implementations (HVT, SVT, and
LVT respectively).

Figure 2 Noise Model in the cell [5]. 50

45 Supply Lk. (scaling INV W&L)

40 Supply Lk. (scaling INV L)


III. LEAKAGE REDUCTION BY SUPPLY VOLTAGE SCALING Bitline Lk. (scaling ACC W&L)
AND HIGH THRESHOLD TRANSISTORS 35
Bitline Lk. (scaling ACC L)
Leakage (pA)

30
Supply voltage scaling is a well known method to
25
reduce the power consumption of a circuit. The leakage is
reduced due to smaller voltage differences between the 20

drain, source and body of a transistor. 15

As depicted in Figure 3a, the leakage current through the 10

supply and the bitlines of the SRAM cell is significantly 5


reduced for low supply voltages (e.g. 0.2V). It also shows 0
that a cell with higher threshold voltages has significantly 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2
S (S=1 im plies Lm in)
lower leakage even at a nominal supply voltage of 1.2V.
Figure 3b shows that cell stability is compromised as supply Figure 4 Leakage vs. transistor size scaling.
voltage is lowered.
case, only L is scaled. When W and L are scaled together by
S, we see two key leakage components at work:
IV. LEAKAGE REDUCTION BY SIZE SCALING subthreshold leakage (between source and drain) and
Transistor sizing is a simple yet effective way to reduce junction leakage (between drain and body) [9]. Both supply
leakage. Figure 4 depicts the tradeoff between area and and bitline leakage initially decrease rapidly due to
leakage reduction. Gate dimensions, W and L, are scaled by reduction of the subthreshold component. But as S becomes
a factor S. In our first case study, W and L are scaled at the larger, the subthreshold component becomes comparable to
same time to keep the same aspect ratio and in the other the junction component, which strongly depends on W.
Considering that the total area used by the access transistors
is relatively small, it is effective to scale them more 400
aggressively than inverters. A reasonable choice is S = 1.1 350

Supply Leakage (pA)


for the inverters and S = 1.2 for the access transistors. In this 300
1 Cell
250
case, supply and bitline leakage are 20.2pA (66% of total 200
2 Cells

cell leakage) and 10.2pA (34%) respectively, for a total of 150


4 Cells
16 Cells
30.4pA per cell. 100
50
V. LEAKAGE REDUCTION BY SLEEP TRANSISTOR 0
1 2 3 4 5 6 7 8 9 10
A sleep transistor can be implemented between ground Sleep Transistor Width (um )
and the node (GNDX) that connects to the sources of all
pull-down NMOS transistors within a column in the (a)
70
memory array, as shown in Figure 1. This circuit topology
60
introduces the stack effect, also present in the pull-down

Bitline Leakage (pA)


50 1 Cell
network of a NAND gate [9]. The upper portion of the stack 40 2 Cells
is the parallel combination of all pull-down NMOS 30 4 Cells
transistors while the lower portion is the sleep transistor. 20
16 Cells
Due to the leakage current through the stack, GNDX is 10
above ground level, causing the gate-to-source voltage of 0
the pull-down NMOS transistors to be negative when their 1 2 3 4 5 6 7 8 9 10

gates are at logic zero. The sleep transistor has leakage ISleep, Sleep Transistor Width (um)

which is the total leakage of a column. In the idle mode, the (b)
sleep transistor’s control input VC is low, disconnecting the Figure 5 Leakage for different numbers of cells per column
memory cells from ground. When the cell is active, VC is using one NMOS sleep transistor: (a) Supply leakage, (b)
high, providing a path that connects the cells to ground with Bitline leakage.
ideally low resistance. The choice of an NMOS instead of a
PMOS as the sleep transistor is due to the fact that both 200
supply and bitline leakage current flow through the pull- 180
160
down network. 140 1 Cell
Figures 5a and 5b show respectively the dependencies of
SNM (mV)

120 2 Cells
100
the supply and the bitline leakage on the size of a high 80
4 Cells

threshold voltage (HVT) sleep transistor. We propose the 60 16 Cells


40
use of HVT as other VT levels reduce leakage by such a 20
small amount that its benefit does not outweigh the 0
1 2 3 4 5 6 7 8 9 10
additional circuit complexity. With a 1.2V VDD, SNM is Sleep Transistor Width (um)
obtained for different numbers of 6T cells attached to the
column of the memory array as depicted in Figure 6. SNM Figure 6 SNM vs. sleep transistor size.
is significantly lowered by the sleep transistor. For
comparison, the implementation without the sleep transistor cells in a column is large. The supply voltage scaling
yields an SNM of 475mV as shown in Figure 3b. The loss technique does not exhibit this characteristic.
of SNM is compensated by a large leakage reduction. In an attempt to further reduce leakage, two NMOS
To achieve a particular SNM, the size of the sleep sleep transistors are stacked between GNDX and circuit
transistor must be scaled linearly with respect to the number ground as in Figure 1. Figure 7a and 7b shows supply and
of cells in a column. As can be observed in Figure 6, it takes bitline leakage respectively when stacking two sleep
a sleep transistor with 1µm of width to achieve a SNM of transistors. Examining solely the leakage reduction, by
100mV for the 1-cell case. It takes 2µm and 4µm for the 2- comparing Figure 5 and 7, the sleep transistor stack is a
cell and 4-cell case respectively to achieve the same 100mV superior implementation. However, the SNM of the
SNM. Contrary to SNM, the leakage does not scale linearly. transistor stack implementation is noticeably worse than the
The leakage per cell decreases as the number of cells in a case with only one NMOS sleep transistor due to the high
column increases as observed in Figure 5. For example, resistance path between GNDX and circuit ground. Using
using a 10µm sleep transistor, the bitline leakage for 1 cell SNM as a cross reference, that is using the two methods to
is 23pA while the bitline leakage for 16 cells is just 62pA. achieve a specified SNM, we find that the use of two
This result suggests that greater leakage reduction can be stacked NMOS sleep transistors yields less leakage
achieved with a large sleep transistor when the number of reduction; hence the single NMOS implementation is
preferred.
250 reduction while maintaining acceptable cell stability. This
work investigated the use of different VT transistors, scaling
200
Supply Leakage (pA)

1 Cell supply voltage, sizing above minimum gate length, and


150 2 Cells implementing single and stacked sleep transistors. The
100
4 Cells counterintuitive results suggest that, after scaling transistors
16 Cells beyond minimum gate length, sleep transistor
50 implementation yields greater leakage reduction than supply
0
voltage scaling. While the wealth of existing knowledge
1 2 3 4 5 6 7 8 9 10 mainly targets cache memory, the proposed combinations of
Sleep Transistor Width (um)
techniques are effective in the emerging ultra-low power
(a) wireless sensor network domain. Proper applications of
40 these techniques can reduce leakage by 189X for a 4Kb
35 SRAM assuming 64 cells per column, with further reduction
Bitline Leakage (pA)

30
1 Cell for a larger size memory. Future work may investigate the
25
2 Cells performance impact of leakage reduction techniques so that
20 4 Cells a power-performance tradeoff can be made.
15 16 Cells
10 ACKNOWLEDGMENT
5
0
The authors gratefully acknowledge Alicja Pierzynska
1 2 3 4 5 6 7 8 9 10 for providing insightful comments on the paper.
Sleep Transistor Width (um)

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