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X-Calibration: A Technique for Combating

Excessive Bitline Leakage Current
in Nanometer SRAM Designs
Ya-Chun Lai and Shi-Yu Huang, Member, IEEE

Abstract—In an SRAM circuit, the leakage currents on the bit in the nanometer technology. According to the report of [1],
lines are getting increasingly prominent with the dwindling of the worst-case bit-line leakage current can reach 117 A
transistors’ threshold voltages as the technology scales down to under high temperature and large column height. Because the
90 nm and beyond. Excessive bit-line leakage current results in
slower read operations or even functional failure. In this paper, non-evaluating bit-line is discharged by the bit-line leakage
we present a new technique, called X-calibration, to combat this current, the effective bit-line voltage swing developed by the
phenomenon. Unlike the previous method that attempts to com- cell current of the accessed memory cell during a read op-
pensate the leakage current directly, this scheme first transforms eration will decline. The degraded effective bit-line voltage
the bit-line leakage current into an equilibrium offset voltage swing either increases the delay of the sense amplifier or makes
across the bit-line pair, and then simple circuitry is utilized to
cancel this offset accurately at the input of the sense amplifier
the sense amplifier react incorrectly. Several methods have
so that the sensing is not affected by the bit-line leakage. SPICE been proposed to solve this problem. These methods can be
simulation of a 1 Kbit SRAM macro shows that this X-calibration classified into two categories: leakage suppression [2]–[4] and
scheme can handle 83% higher bit-line leakage current than the leakage compensation [5]–[7]. These studies try to solve the
previous bit-line leakage compensation scheme. Measurement problem by means of either adapting the manufacturing process
results of the test chip show that the SRAM macro adopting
or changing the circuitry.
X-calibration scheme can cope with up to 320 A bit-line leakage
current. The negative word-line scheme proposed in [2] forces an
inactive word-line to a voltage level lower than the ground to
Index Terms—Bitline leakage current, on-off ratio, sense ampli-
fier, SRAM, X-calibration scheme.
reduce the leakage through access transistors. Yet, this scheme
may still suffer from the so-called gate-induced drain leakage
current. The scheme proposed in [3] uses both dual threshold
I. INTRODUCTION voltage and aggressive biasing on the word-lines, the bit-lines,
and the power lines of the storage cells to curb the leakage
A S CMOS process technology scales down into the
nanometer scale, a number of unexpected side effects,
such as raised leakage current of transistors, larger process
currents. Hence, this scheme can cope with excessive bit-line
leakage current in a 100-nm dual- technology as demon-
variation, worse matching of symmetric devices, and deterio- strated [3]. However, as technology advances, the leakage
rated power and ground lines, start to emerge. These nanometer current could become even more severe and thus this leakage
effects not only bring enormous challenges to circuit designers suppression technique may still need some compensating
but also greatly reduce the manufacturing yield. Consequently, techniques that help to tolerate the leakage currents in addition
to design a robust circuit to deal with these effects has become to curbing them in the future. Also, as the process variation
much more important. increases, the biasing circuits may not be able to generate the
For logic circuits, the threshold voltage of transistors is often bias voltages as accurately. In [4], a dynamic leakage cut-off
reduced to retain high performance as the supply voltage de- scheme was also proposed. The drawback is that this scheme
clines. In turn, the reduced threshold voltage results in increased may degrade the operation speed due to the large additional
leakage current, which does not lead to catastrophic results for time required for generating a reverse substrate bias.
logic circuits. Yet, the raised leakage current could not only de- The bit-line compensation (BLC) scheme described in [5]
grade the performance for an SRAM circuit but also lead to er- modifies the pre-charge circuitry to detect the amount of the
roneous operations. bit-line leakage. After that, similar amount of current is injected
Bitline leakage current is the most significant component into the bit-line so as to compensate the loss due to leakage. Nev-
of leakage in memories and will become increasingly large ertheless, this scheme is sensitive to the process variation due to
the dynamic current mirror structure, which is extremely sus-
ceptive to the variation of the threshold voltage. The modified
Manuscript received April 13, 2007; revised April 25, 2008. Current version
BLC schemes described in [1] and [6] attempt to overcome some
published September 10, 2008. This work was supported by the National Sci- weaknesses in [5] such as the mismatch problem of the dynamic
ence Council of Taiwan under Grant NSC 96-2220-E-007-028. current mirror. The modified circuit proposed by [6] success-
The authors are with the Department of Electrical Engineering, Na-
tional Tsing Hua University, Hsinchu, Taiwan 30013, R.O.C. (e-mail:
fully uses the same transistor to detect the bit-line leakage cur-; rent and inject the compensation current. Notwithstanding, the
Digital Object Identifier 10.1109/JSSC.2008.2001937 gate voltage of the transistor that decides the injected amount
0018-9200/$25.00 © 2008 IEEE

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Fig. 1. Conventional SRAM column with bit-line leakage.

of the compensation current is still sensitive to the coupling

noise from the bit-line. The bit-line leakage equalization tech-
nique mentioned in [7] does not require additional control sig- Fig. 2. Waveforms of the bit-line pair for a conventional SRAM (a) without
bit-line leakage and (b) with bit-line leakage.
nals and time to detect the amount of leakage current on the
bit-line pairs. This technique, nonetheless, has about 40% area
overhead because the conventional 6-transistor cell is replaced
hinder the bit-line differential signal detection performed by the
with the new 8-transistor leakage-equalized cell. Also, dupli-
sense amplifier.
cating leakage current on one bit-line for the other may double
Fig. 2 shows the waveforms of the bit-line pairs with and
total leakage current and cause more power consumption. In this
without the bit-line leakage. As shown in the figure, we can see
paper, we propose a new scheme to solve the bit-line leakage
that the bit-line voltage difference reduces when the excessive
current problem. The basic idea is to transform the leakage cur-
rent into an equilibrium offset voltage across the bit-line pair. bit-line leakage current exists. The reduced bit-line difference
Then, offset cancellation techniques can be applied to resolve degrades the performance and increases the read access time
the problem. The circuitry we propose here can work under a because the sense amplifier needs more time to detect smaller
wide-range bit-line leakage current. Moreover, there are only input differential voltage. If the bit-line leakage becomes close
two additional control signals in this scheme. Consequently, the to or larger than the cell current, the read operation would fail
new bit-line sensing circuitry is power efficient. due to potentially incorrect detection of the sense amplifier.
The rest of this paper is organized as follows. Section II The so-called on–off ratio has been popularly used as a de-
describes the problem caused by bit-line leakage current. sign criterion for taking the bit-line leakage current into account,
Section III presents the proposed X-calibration scheme. and is defined as the ratio of the cell current being accessed
Section IV gives a transient analysis of the proposed scheme to the total leakage current drained by the non-accessed cells.
and chip implementation. Section V shows the experimental As a rule of thumb, this ratio is often larger than 10 to pro-
results. Finally, we conclude the paper in Section VI. vide a good leakage immunity when designing a robust SRAM
circuit. This criterion could therefore impose on the maximum
height of a cell column, or the number of bit cells connected
to a single column of the SRAM cell array. Unfortunately, as
First, we will point out the problem caused by bit-line leakage the process continues to scale down, the threshold voltage of
current in detail. Fig. 1 shows a single-column circuit for a con- transistor is often reduced accordingly in order to compensate
ventional SRAM. The accessed cell stores logic-1 while the for the speed loss due to lower supply voltage. In turn, the sub-
others store logic-0. This is the worst scenario when the bit-line threshold leakage current becomes even larger and this on–off
leakage impacts the circuit’s operation most. For each non-ac- ratio target becomes harder to achieve. Sometimes, the same
cessed cell, there is subthreshold leakage current flowing from on–off ratio is retained at the sacrifice of the reduced height.
the bit-line, passing through one access transistor, and finally However, this strategy is only a tradeoff and not a good solu-
into the storing node of logic-0 as shown in Fig. 1. Under this tion because it forms a limit on the capacity of an SRAM and
condition, these leakage currents jointly contribute to the overall reducing the area efficiency as well [3].
bit-line leakage current. When the accessed cell is read, this joint The bit-line leakage current is dependent on the data pattern
bit-line leakage current will become the noise against the cell stored in one column and on the operating temperature. As a re-
current (i.e., the current flowing into the accessed cell) and may sult, the amount of the bit-line leakage current will change after

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Fig. 3. Basic concept of the X-calibration scheme.

Fig. 4. Schematic of the calibration circuitry.

each write operation, which varies the data pattern. The amount
of bit-line leakage also increases as the operating temperature


In this section, we first explain the basic concept of the X-cal-
ibration scheme and then describe its detailed implementation.

A. Basic Concept
We regard the bit-line leakage current as an offset voltage
and then cancel the offset voltage by means of the calibration
circuitry attached to the sense amplifier. This basic idea can be
explained in two parts, as follows.
• Generation of the equilibrium offset voltage: The bit-line
leakage current is transformed into an offset voltage across
the bit-line pair. As shown in Fig. 3, we use the conven-
tional bit-line static load circuitry to provide pull-up cur-
rent against the bit-line leakage current. Finally, the voltage
level of each bit-line reaches an equilibrium level after
some time. The difference of the equilibrium levels across
the bit-line pair is referred to as the equilibrium offset
voltage or simply the offset voltage for the rest of this
Fig. 5. (a) Waveforms of the bit-line pair and input pair of the sense amplifier.
• Cancellation of the offset voltage: The offset voltage men- (b) Timing diagram of the control signals.
tioned above is first recorded and then cancelled by the
calibration circuitry attached to the inputs of the sense am-
plifier as shown in Fig. 3. The detailed operations of the
in Fig. 5(a). This scheme is called X-calibration because of the
calibration circuitry will be described later.
crossing structure formed by the switches controlled by .
The operation of an SRAM column with the calibration cir-
B. Circuit Architecture and Operation
cuitry can be divided into the following three phases, shown in
The schematic of the calibration circuitry shown in Fig. 4 is Fig. 5(a).
mainly composed of several switches and two coupling capac- 1) Pre-charge phase: In this phase, the bit-line pair is pre-
itors. There are two additional control signals, and , the charged to an initial level (namely in the design) and
timing diagrams of which are shown in Fig. 5(b). The transient the input pair of the sense amplifier is left floating. At this
waveforms of the bit-line pair and the input pair of the sense am- moment, all switches in the calibration circuitry are turned
plifier in the presence of the bit-line leakage current are shown off.

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Fig. 6. Illustration of each operation phase. (a) Pre-charge and equalization. (b) Detection. (c) Calibration and read.

2) Detection phase: The pre-charge circuit is turned off and by . At the end of this phase, the equilibrium offset voltage
the switches controlled by are turned on to detect the across the bit-line pair has been generated and stored in the cali-
offset voltage developed by the bit-line static load. Note bration circuitry. Finally, the column comes into the calibration
that this offset voltage has been flipped around by the and read phase shown in Fig. 6(c). The cell current discharges
crossing structure of the switches controlled by . This the complementary bit-line so that the voltage level of the com-
reversal of the offset voltage is designed intentionally to plementary bit-line falls down and balances at the voltage level
support easy offset cancellation later. of 1.45 V. This voltage drop can be transferred to the comple-
3) Calibration and read phase: The switches controlled by mentary input of the sense amplifier by means of the coupling
are turned off and then those controlled by are turned capacitor. Now, we can clearly see that the offset voltage is per-
on to couple the voltages at the bit-lines to the inputs of fectly cancelled at the input pair of the sense amplifier from
the sense amplifier. At the beginning of this phase, the re- Fig. 6(c).
versed offset voltage detected in phase 2 was stored across The sense amplifier we used is the latch-type sense amplifier
the bottom nodes of the two coupling capacitors and will mentioned in [8] and [9]. In order to use capacitive coupling to
be deducted from the differential voltage across the bit-line achieve the offset cancellation, the input impedance of a sense
pair to cancel out the offset voltage during this coupling amplifier must be infinite and the inputs of sense amplifier need
process. Therefore, the offset voltage disappears from the to be floating during the calibration phase. In addition, the ca-
input pair of the sense amplifier in this phase and the oper- pacitance of the coupling capacitor should be selected appropri-
ation performed by the sense amplifier will not be affected ately. If its capacitance is too small, the coupling effect will be
at all by the bit-line leakage. too weak and the offset voltage cancellation will be less accu-
Since the operation of the calibration is hidden within the rate. On the other hand, using too large capacitance will cause
read operation, there is no access time penalty in this scheme. excessive area overhead. Therefore, the selection of the capac-
Also, the calibration circuitry works well for the write operation. itance of the coupling capacitor is a tradeoff between coupling
The timings of the two control signals ( and ) should not efficiency and area. In our design, the capacitance of the cou-
overlap each other. pling capacitor is determined according to simulation result and
In order to clearly demonstrate the three operation phases of consideration of physical implementation.
an SRAM column with the calibration circuitry, we give an ex-
ample with bit-line leakage, as shown in Fig. 6. For simplicity,
each node’s voltage designated in Fig. 6 is just an approximate
value and thus slightly different from the real case. In Fig. 6(a),
A. Transient Analysis of X-Calibration Scheme
the column is in the pre-charge phase and the bit-line pair is
pre-charged and equalized to initial voltage level, 1.8 V. Then, in Fig. 7 shows transient waveforms of bit-lines under diverse
Fig. 6(b), the column gets into the detection phase. The bit-line bit-line leakage currents during a read operation, where BL is
voltage level drops down and eventually balances at the lower discharged by bit-line leakage current and /BL is discharged by
voltage level of 1.4 V due to the bit-line leakage current. This cell current when WL is turned on. The entire read cycle can
voltage level is carried to the bottom node of the coupling ca- be divided into three phases: 1) pre-charge; 2) detection; and
pacitor on the other side through the crossing switch controlled 3) calibration and read. Because the detection time borrows the

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Fig. 9. Micrograph of the test chip.

Fig. 7. Transient waveforms of bit-lines under diverse bit-line leakage currents.

Fig. 10. Micrograph of the SRAM macro using X-calibration.

Fig. 8. Relationship between equilibrium time and bit-line leakage current.

the same configuration but without the calibration circuitry. The
micrograph of the test chip is shown in Fig. 9. The upper part of
timing margin from the pre-charge time and the calibration op- the test chip is the SRAM macro using the X-calibration scheme
eration is performed together with the normal read operation at and the lower is the conventional SRAM macro. The memory
the same time, there is no access time penalty. However, the built-in self-test (BIST) circuitry in the middle of the test chip
cycle time could rise a little due to the insertion of the detec- is also included. The detailed micrograph of the SRAM macro
tion phase between the pre-charge and the read operation phase. using X-calibration is shown in Fig. 10. The switching transis-
In our X-calibration scheme, the circuit designer can adjust the tors in the calibration circuitry are PMOS pass transistors, and
detection time on the design stage according to the equilibrium coupling capacitors implemented in the test chip are metal–insu-
time, which is defined as the time interval between the end of lator–metal (MIM) capacitors. The area of the proposed SRAM
the pre-charge phase and the time instant that the non-evalu- macro increases by 7.55% as compared with the conventional
ating bit-line (i.e., BL in Fig. 7) reaches equilibrium level as SRAM macro due to the calibration circuitry.
mentioned in Section III-A. By means of simulation analysis, it
is known that the equilibrium time is dependent on the amount C. Methods for Mimicking Bit-Line Leakage
of bit-line leakage current and is less than 25% cycle time at an In the test chip, we use 0.18- m CMOS technology. There are
operating frequency of 200 MHz when the bit-line leakage cur- two possible methods to mimic the leakage phenomena we may
rent is under 285 A as shown in Fig. 8. In fact, the detection encounter at 90 nm process and beyond. One method is to adjust
time can be less than the equilibrium time at the cost of max- the voltage levels of those inactive word-lines from ground to
imum tolerable bit-line leakage current when the timing budget slightly higher voltage level. This method, however, is difficult
is tight. to realize for the whole SRAM macro and all SRAM columns
would have the same bit-line leakage. In practice, each column
B. Implementation of Fabricated Test Chip
may have different bit-line leakage current due to different data
In order to evaluate the effectiveness of the proposed scheme, pattern. The other method is to add one NMOS transistor pair to
we have fabricated a test chip of an SRAM macro of 1 Kb in a each bit-line pair. These transistors connect bit-lines to ground
0.18- m standard CMOS process technology. For comparison, and we can adjust the gate voltage of the transistor to generate
the test chip has also included a conventional SRAM macro with appropriate drain current as bit-line leakage current. We adopt

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Fig. 11. Bit-line leakage current generator.

the latter method because of its simplicity. The bit-line leakage

current generator is shown in Fig. 11.


A. Simulation Results
In order to compare the X-calibration scheme with the pre-
vious bit-line leakage compensation (BLC) scheme [5], we also
implemented an SRAM macro of 1 Kb using the circuit ar-
Fig. 12. Impact of bit-line leakage on access time for the three SRAM macros
chitecture of the BLC scheme. Table I lists the read current, in a 0.18-m CMOS technology with extra bit-line loading capacitance of
the write current, the access time, and the maximum tolerable (a) 200 fF and (b) 500 fF, respectively.
bit-line leakage of these three SRAM macros. These circuit per-
formance parameters are obtained by running SPICE simula-
tion. The following is the meaning of each column of Table I. small as compared with the SRAM macro with a large column
• Read current: The average supply current for performing a height, e.g., 256 or 512. As a result, we added extra loading ca-
read operation during one cycle. pacitance on each bit-line pair and run SPICE simulation for the
• Write current: The average supply current for performing three SRAM macros when deriving the data.
a write operation during one cycle. The experimental results show that the X-calibration scheme
• Access time: The delay from the rising edge of the clock can handle 61% and 83% higher bit-line leakage current than
to the transition edge of the data output during a read the BLC scheme under 200 fF and 500 fF extra bit-line loading
operation. capacitance, respectively. In addition, when the extra bit-line
• Maximum tolerable bit-line leakage: The maximum toler- loading capacitance increases, the upper bound of the bit-line
able bit-line leakage current under which the SRAM circuit leakage current that all SRAM macros can cope with will
can operate correctly. decline. However, the X-calibration scheme can still function
The impact of the bit-line leakage current on the access time correctly up to 300 A bit-line leakage current, as shown in
for each of the three SRAM macros is shown in Fig. 12. In prac- Fig. 12(b).
tice, there is cell current distribution due to process variation or The size of the critical transistors of both BLC and X-cali-
noise emerging on the bit-line pair. Therefore, the upper bound bration scheme may influence the experimental results, so we
of bit-line leakage for the conventional SRAM macro could be use similar dimensions for those transistors in both schemes
lower. Because the number of memory cells on each column for so as to guarantee fair comparison. The critical transistors for
these SRAM macros is 32, the bit-line loading capacitance is too BLC scheme refer to those for detecting bit-line leakage and for

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Fig. 13. Relationship between the sensing time and the column height under Fig. 14. Shmoo plots of supply voltage versus BIAS for (a) conventional
(a) the room temperature 25 C and (b) a higher temperature 125 C for a 22-nm SRAM macro and (b) X-calibration SRAM macro.
CMOS technology.

X-calibration can still function correctly and has better sensing

injecting compensation current. For X-calibration scheme, the time than the BLC scheme.
critical transistors refer to the bit-line static loads.
The experimental results of Fig. 13 show the relationship be- B. Measurement Results
tween the sensing time and the column height under different Measured shmoo plots of the test chip are shown in Fig. 14.
temperatures, e.g., 25 C and 125 C, in a 22-nm CMOS tech- The parameter, BIAS, in the horizontal axis is the gate voltage
nology. The definition of the sensing time is the delay time from of the NMOS transistor in the bit-line leakage current generator
the word-line activation to the time when the voltage difference to induce bit-line leakage current. Hence, if BIAS goes up,
at the input pair of the sense amplifier, i.e., , reaches the bit-line leakage will increase as well. The relationship
0.1 , namely 80 mV for 0.8-V in a 22-nm CMOS tech- between BIAS and bit-line leakage, , is shown in Table II.
nology. Moreover, the column height signifies the total number When BIAS is low, both SRAM macros function correctly.
of bit cells connected to each bit-line pair. The data are de- When BIAS rises over 0.68 V, the conventional SRAM macro
rived by performing SPICE simulation using a 22-nm Predictive will fail. However, the X-calibration SRAM macro still works
Technology Model (PTM) [10], [11]. When the column height correctly until the BIAS goes up to 1 V. According to the
becomes larger or the temperature increases, the worst-case bit- measured results in Table II, it can be seen that the upper bound
line leakage current increases. Therefore, the sensing time in- of tolerable bit-line leakage of the conventional SRAM macro
creases and eventually the read operation of the conventional is only 76.6 A. However, the X-calibration SRAM macro can
SRAM circuit could fail. However, the SRAM circuit using our work correctly under 320 A bit-line leakage. As a result, the

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SRAM macro using X-calibration scheme can break through REFERENCES

the boundary of maximum tolerable bit-line leakage of the [1] A. Natarajan, V. Shankar, A. Maheshwari, and W. Burleson, “Sensing
conventional SRAM macro and reach a new boundary of as design issues in deep submicron CMOS SRAMs,” in Proc. IEEE Com-
puter Society Annu. Symp. VLSI, May 2005, pp. 42–45.
much as 320 A bit-line leakage current. [2] H. Tanaka, M. Aoki, T. Sakata, S. Kimura, N. Sakashita, H. Hidaka,
The test chip characteristics are summarized in Table III. T. Tachibana, and K. Kimura, “A precise on-chip voltage generator
Compared with the conventional 1 Kb SRAM macro, the area for a Gigascale DRAM with a negative word-line scheme,” IEEE J.
Solid-State Circuits, vol. 34, no. 8, pp. 1084–1090, Aug. 1999.
overhead of the SRAM macro using the X-calibration scheme [3] Y. Ye, M. Khellah, D. Somasekhar, A. Farhang, and V. De, “A 6-GHz
is 7.55%. The measured extra power consumption due to this 16-kB L1 cache in a 100-nm dual-VT technology using a bit-line
leakage reduction (BLR) technique,” IEEE J. Solid-State Circuits, vol.
scheme is 9.7% at the operating frequency of 150 MHz. The 38, no. 5, pp. 839–842, May 2003.
measured access time includes off-chip delay, i.e., the delay [4] H. Kawaguchi, Y. Itaka, and T. Sakurai, “Dynamic leakage cut-off
of the pad, the package, and the load-board on the ATE. As a scheme for low-voltage SRAM’s,” in Proc. Symp. VLSI Circuits, Jun.
1998, pp. 140–141.
result, the measured access time for each SRAM macro in the [5] K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, “A bit-line leakage
test chip is much larger than the simulation results, which only compensation scheme for low-voltage SRAMs,” IEEE J. Solid-State
Circuits, vol. 36, no. 5, pp. 726–734, May 2001.
include on-chip delay. Additionally, since the data output pin [6] M. Khellah, Y. Ye, D. Somasekhar, D. Casper, B. Bloechel, T. Nguyen,
of the X-calibration SRAM macro in the test chip encounters G. Dermer, K. Zhang, G. Pandya, A. Farhang, and V. De, “Bitline
a longer routing wire of the load-board on the ATE than that leakage compensation (BLC) and leakage reduction (BLR) techniques
for 2–3 GHz on-chip cache arrays in microprocessors on 90 nm logic
of the conventional SRAM macro, the measured access time technology,” in Proc. Symp. VLSI Circuits, Jun. 2005, pp. 262–263.
of the X-calibration SRAM macro is greater than that of the [7] A. Alvandpour, D. Somasekhar, R. Krishnamurthy, V. De, S. Borkar,
conventional SRAM macro. and C. Svensson, “Bitline leakage equalization for sub-100 nm caches,”
in Proc. 29th European Solid-State Circuits Conf. (ESSCIRC’2003),
Sep. 2003, pp. 401–404.
[8] T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, “A current-
controlled latch sense amplifier and a static power-saving input buffer
VI. CONCLUSION for low-power architecture,” IEEE J. Solid-State Circuits, vol. 28, no.
4, pp. 523–527, Apr. 1993.
We have developed a new scheme called X-calibration to [9] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed op-
timization of a latch-type voltage sense amplifier,” IEEE J. Solid-State
solve the problem induced by bit-line leakage current. This Circuits, vol. 39, no. 7, pp. 1148–1158, Jul. 2004.
problem, if not coped with well, will become increasingly dev- [10] Predictive Technology Model (PTM). Nanoscale Integration and
astating in nanometer technologies due to the ever-increasing Modeling (NIMO) Group, Arizona State Univ., Phoenix, AZ [Online].
Available:, last updated Feb. 28, 2008.
leakage current. In the X-calibration scheme, the calibration [11] W. Zhao and Y. Cao, “New generation of predictive technology model
circuitry consisting only of capacitors and switches is simple for sub-45 nm design exploration,” in Proc. Int. Symp. Quality Elec-
to build to shield the sense amplifier from the disturbance of tronic Design, Mar. 2006, pp. 585–590.

bit-line leakage current. Compared with the conventional 1 Kb Ya-Chun Lai was born in Taiwan in 1981. He re-
SRAM macro, the area overhead of the SRAM macro using the ceived the B.S. degree in electrical engineering from
X-calibration scheme is only 7.55%. Moreover, if the column National Tsing Hua University, Hsinchu, Taiwan,
R.O.C., in 2004, where he is currently working
height increases or the area of the coupling capacitor decreases, toward the Ph.D. degree in electrical engineering.
the area overhead can be reduced further. The measured extra He was a summer intern with Taiwan Semicon-
ductor Manufacturing Company, Ltd., in 2005. His
power consumption due to this scheme is only 9.7% at the recent research interests include VLSI design and
operating frequency of 150 MHz. Measurement results of the high-yield SRAM design for nanometer technology.
fabricated test chip validate that the X-calibration scheme is
not only feasible but also capable of increasing the maximum
tolerable bit-line leakage current up to 320 A, which is 4.18
times as much as in the conventional SRAM macro. Shi-Yu Huang (S’93–M’97) received the B.S. and
M.S. degrees in electrical engineering from National
Taiwan University, Taipei, Taiwan, R.O.C., in 1988
and 1992, and the Ph.D. degree in electrical and com-
ACKNOWLEDGMENT puter engineering from the University of California at
Santa Barbara in 1997, respectively.
He joined the faculty of the Department of Elec-
The authors would like to thank National Chip Implemen- trical Engineering, National Tsing-Hua University,
tation Center (CIC) and L.-M. Denq for technical support, Taiwan, in 1999, where he is currently an Associate
Taiwan Semiconductor Manufacturing Company (TSMC) for Professor. His research interests are mainly in VLSI
design, automation, and testing, with an emphasis on
chip fabrication, and M.-F. Chang and C.-W. Wu for their power estimation, fault diagnosis, CMOS image sensor design, and nanometer
valuable discussions. SRAM design.

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