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on REMOTE CONTROLLED CAR USING RF
Submitted in partial fulfillment of the requirements of
Bachelor of Engineering Degree To Chandigarh College of Engineering & Technology Sector 26, Chandigarh
SUBMITTED TO: Ms. Sarika Sharma (HOD EECE ) SUBMITTED BY: Vidisha Gupta (C05519)
It gives me great pleasure to present this project report on “Remote controlled car using RF technology”. I express my gratitude to the faculty of Chandigarh College of Engineering and Technology for supporting me and guiding me . I would also like to express my sincere thanks to Mr. Daljit Singh and Mr. Harjeet Singh for their inspiration and affectionate guidance throughout the project. I also extend my regards to the entire RAD team for their support and encouragement that helped to make this learning experience memorable and enjoyable.
Vidisha Gupta (C05519)
RAD Innovations ( A Research & Development Company )
RAD Innovations is a well established company in Mohali and has gained recognition as training and development company of high repute offering international quality in the field of embedded systems. They are associated with a number of companies and Engineering & Polytechnic Colleges in the states of Punjab, Haryana & Himachal Pradesh for providing specific training programs to their students. This company is located in Mohali in the main commercial area.
Area of Work
Industrial Project development Research & Development in the field of embedded systems. Industrial Training
Industrial Project Development
They develop Embedded system based projects for Industry as well as Engineering students as per their demands .They have products like Displays ( Moving Display , Density Display , Timers , Digital Clocks etc.) , weighing Machines , Security Systems & Automation etc...
They provide training programs of 6 weeks to 6 months in the following fields: Embedded Systems for (8/16/32 bit microcontrollers ) Robotics ORCAD Designing VLSI
Real Time operating Systems Proteus Advanced Communication Integrated Electronics Languages C / C ++ Project Guidance & Technical Help
Labs are equipped with following: Embedded system Trainer Kits for 8-bit (Atmel, philips),16-bit(microchip),32bit(ARM), CROs ,Soldering/Desoldering Stations ,Analog & Digital Trainer Kits ,Experimental Boards , Digital Multimeters & Magnified lamps
They have a skilled base of Engineers and professionals with in-depth knowledge of a variety of applications and who have worked with leading industries in field of research & development on a wide range of platforms.
( A Research & Development Company .) SCO 546, Level III , Sector 70 Mohali. Tel: 0172-4667778 / 4668887 (M) – 92164-97778
Certificate Acknowledgement Company Profile i ii iii
Introduction Abstract List of components Hardware used AVR: Key features Pin configuration Pin description AVR CPU core AVR ATMEGA8 memories Photo resistor LCD Softwares used AVR Studio ISP Flash Programmer Block diagram Working Coding Transmitter Receiver RF Advantages RF Disadvantages Limitations Future Development References
3 4 5 6 6 9 10 11 16 19 20 23 23 23 25 26 28 28 29 30 30 31 31 32
Wireless communication, as the term implies, allows information to be exchanged between two devices without the use of wire or cable. A wireless keyboard sends information to the computer without the use of a keyboard cable; a cellular telephone sends information to another telephone without the use of a telephone cable. Changing television channels, opening and closing a garage door, and transferring a file from one computer to another can all be accomplished using wireless technology. In all such cases, information is being transmitted and received using electromagnetic energy, also referred to as electromagnetic radiation. One of the most familiar sources of electromagnetic radiation is the sun; other common sources include TV and radio signals, light bulbs and microwaves. The electromagnetic spectrum classifies electromagnetic energy according to frequency or wavelength (both described below). As shown in Figure, the electromagnetic spectrum ranges from energy waves having extremely low frequency (ELF) to energy waves having much higher frequency, such as x-rays.
The project is based on RF communication which principally works by creating electromagnetic waves at a source and being able to pick up those electromagnetic waves at a particular destination. These electromagnetic waves travel through the air at near the speed of light. The wavelength of an electromagnetic signal is inversely proportional to the frequency; the higher the frequency, the shorter the wavelength. To understand RF communication, Imagine an RF transmitter wiggling an electron in one location. This wiggling electron causes a ripple effect, somewhat akin to dropping a pebble in a pond. The effect is an electromagnetic (EM) wave that travels out from the initial location resulting in electrons wiggling in remote locations. An RF receiver can detect this remote electron wiggling. The RF communication system then utilizes this phenomenon by wiggling electrons in a specific pattern to represent information. The receiver can make this same information available at a remote location; communicating with no wires. In most wireless systems, a designer has two overriding constraints: it must operate over a certain distance (range) and transfer a certain amount of information within a time frame (data rate). We have used this technology to control the movement of a car through a remote. It has a working range of 10-15 metres. Also, instead of using mechanical switches for the input, a touch panel is designed exploiting the property of a photoresistor whose resistance changes according to the intensity of light falling on it. This change in resistance is used to switch on or off the transistor connected to it. Also, to explore the working of AVR, an LCD has been interfaced with the system. The LCD displays the direction in which the car is steered.
LIST OF COMPONENTS
AVR MEGA8L LCD JHD162A RF MODULE B27M(RECEIVER) , 231TX(TRANSMITTER) LDR CRYSTAL 4.1 MHz BATTERY 9V ROBOT CHASIS WITH MOTORS (2400 RPM) AND GEAR SYSTEM. ANTENNA TRANSISITOR BC547 RESISTORS CAPACITORS CONNECTORS LED GENERAL PURPOSE BOARD
AVR STUDIO 4 ISP FLASH PROGRAMMER
HARDWARE USED: AVR ( ADVANCED VIRTUAL RISC)
The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.
KEY Features • High-performance, Low-power AVR 8-bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – One-chip 2-cycle Multiplier • Nonvolatile Program and Data Memories – 8K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 1K Byte Internal SRAM Programming Lock for Software Security • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler , one Compare Mode 5
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode.
– Real Time Counter with Separate Oscillator – Three PWM Channels – 8-channel ADC in TQFP and MLF package Six Channels 10-bit Accuracy Two Channels 8-bit Accuracy – 6-channel ADC in PDIP package Four Channels 10-bit Accuracy Two Channels 8-bit Accuracy – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down and Stand by. • I/O and Packages – 23 Programmable I/O Lines – 28-lead PDIP, 32-lead TQFP, and 32-pad MLF • Operating Voltages – 2.7 - 5.5V (ATmega8L) – 4.5 - 5.5V (ATmega8)
• Speed Grades – 0 - 8 MHz (ATmega8L) – 0 - 16 MHz (ATmega8) • Power Consumption at 4 Mhz, 3V, 25èC – Active: 3.6 mA – Idle Mode: 1.0 mA – Power-down Mode: 0.5 µA
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega8 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and MLF packages) where four (six) channels have 10-bit accuracy and two channels have 8-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hard- ware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power
consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash Memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self- Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega8 AVR is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.
VCC GND Digital supply voltage. Ground.
Port B (PB7-PB0) XTAL1/ XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier .If the Internal Calibrated RC Oscillator is used as chip clock source, PB7.6 is used as TOSC2-1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
Port C (PC5-PC0) Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer
than the minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset.
Port D (PD7-PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
AVCC AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that Port C (5..4) use digital supply voltage, VCC.
AREF AREF is the analog reference pin for the A/D Converter.
AVR CPU Core
Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture– with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is InSystem Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X, Y, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.
Arithmetic Logic Unit (ALU) The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. . Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input. • Two 8-bit output operands and one 8-bit result input. • Two 8-bit output operands and one 16-bit result input. • One 16-bit output operand and one 16-bit result input.
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.
The X-register, Y-register and Z-register The registers R26-R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as described in Figure.
Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when address is popped from the Stack with return from subroutine RET or return from interrupt RETI.
AVR ATmega8 Memories
This section describes the different memories in the ATmega8. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.
In-System Reprogrammable Flash Program Memory The ATmega8 contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16- or 32-bits wide, the Flash is organized as 4K x 16 bits. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8 Program Counter (PC) is 12 bits wide, thus addressing the 4K Program memory locations.
SRAM Data Memory The lower 1120 Data Memory locations address the Register File, the I/O Memory, and he internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 1024 locations address the internal data SRAM. The five different addressing modes for the Data memory cover: Direct, Indirect with displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In he Register File, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base Address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post increment, the address registers X, Y and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega8 are all accessible through all these addressing modes.
EEPROM Data Memory The ATmega8 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described bellow, specifying the EEPROM Address Registers, the EPROM Data Register, and the EEPROM Control Register.
I/O Memory All ATmega8 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general
purpose working registers and the I/O space. I/O Registers within the address range 0x00 -0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers0x00 to 0x1F only.
A photoresistor or Light Dependent Resistor or CdS Cell is a resistor whose resistance decreases with increasing incident light intensity. It can also be referred to as a photoconductor. A photoresistor is made of a high resistance semiconductor. If light falling on the device is of high enough frequency, photons absorbed by the semiconductor give bound electrons enough energy to jump into the conduction band. The resulting free electron (and its hole partner) conduct electricity, thereby lowering resistance. A photoelectric device can be either intrinsic or extrinsic. An intrinsic semiconductor has its own charge carriers and is not an efficient semiconductor, e.g. silicon. In intrinsic devices the only available electrons are in the valence band, and hence the photon must have enough energy to excite the electron across the entire bandgap. Extrinsic devices have impurities, also called dopants, added whose ground state energy is closer to the conduction band; since the electrons don't have as far to jump, lower energy photons (i.e., longer wavelengths and lower frequencies) are sufficient to trigger the device. If a sample of silicon has some of its atoms replaced by phosphorus atoms (impurities), there will be extra electrons available for conduction. This is an example of an extrinsic semiconductor. 18
LIQUID CRYSTAL DISPLAY PIN NUMBER SYMBOL FUNCTION 1 Vss GND 2 Vdd +3 to +5 Volts 3 Vee Contrast Adjustment 4 RS H/L Register Select Signal 5 R/W’ H/L Read/Write Signal 6 E H →L Enable Signal 7 DB0 Data Bus Line 8 DB1 Data Bus Line 9 DB2 Data Bus Line 10 DB3 Data Bus Line 11 DB4 Data Bus Line 12 DB5 Data Bus Line 13 DB6 Data Bus Line 14 DB7 Data Bus Line 15 LED +ve LED Backlight +ve 16 LED –ve LED Backlight –ve This LCD contains HD 44780 microcontroller, which is specially designed for versatile lcd control. The HD44780U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver.
Registers The HD44780U has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator RAM (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written into DDRAM or CGRAM and temporarily stores data to be read from DDRAM or CGRAM. Data written into the DR from the MPU is automatically written into DDRAM or CGRAM by an internal operation. The DR is also used for data storage when reading data from DDRAM or CGRAM. When address information is written into the IR, data is
Busy Flag (BF) When the busy flag is 1, the HD44780U is in the internal operation mode, and the next instruction will not be accepted. When RS = 0 and R/W = 1 (Table 1), the busy flag is output to DB7. The next instruction must be written after ensuring that the busy flag is 0.
Address Counter (AC) The address counter (AC) assigns addresses to both DDRAM and CGRAM. When an address of an instruction is written into the IR, the address information is sent from the IR to the AC. Selection of either DDRAM or CGRAM is also determined concurrently by the instruction. After writing into (reading from) DDRAM or CGRAM, the AC is automatically incremented by 1 (decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/W = 1 .
RS 0 0 1 1
R/W' 0 1 0 1
IR write as an internal operation (display clear, etc.) Read busy flag (DB7) and address counter (DB0 to DB6) DR write as an internal operation (DR to DDRAM or CGRAM) DR read as an internal operation (DDRAM or CGRAM to DR)
For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the HD44780U and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data. LCD Initialization Procedure 1. Function Set 2. Display ON / OFF 3. Clear Display 4. Entry Mode Set 5. Return Home 6. Write Data
AVR STUDIO AVR Studio is an Integrated Development Environment (IDE) for writing and debugging AVR applications in Windows 9x/ME/NT/2000/XP/VISTA environments. AVR Studio provides a project management tool, source file editor, simulator, assembler and frontend for C/C++, programming, emulation and on-chip debugging. AVR Studio supports the complete range of ATMEL AVR tools and each release will always contain the latest updates for both the tools and support of new AVR devices. Currently as a code writing environment, it supports the included AVR Assembler and any external AVR GCC compiler in a complete IDE environment. Many object file formats are also supported from various compiler vendors. You can open and debug these files, but you are not able to edit the code from within AVR Studio. Using your own editor to edit code and AVR Studio to debug (use the reload button), you still have a powerful code/debug environment. Using AVR Studio as an IDE gives you 2 main advantages: 1. Edit and debug in the same application windows. Faster error tracking. 2. Breakpoints are saved and restored between sessions, even if codes are edited.
ISP – FLASH PROGRAMMER
This ISP programmer can be used either for in system programming or as a stand – alone spi programmer for ATMEL programmable devices. The ISP 30a.zip file contains the main program and the o/p port driver. Place all files in same folder.
The main screen view of the program is shown in figure
Following are the main features of this software: Read and write the intel hex file and read signature Lock and fuse bits Clear and file memory buffer Verify with memory buffer Reload current hex file Program selected lock bits Fuse auto detection of hardware. The software does not provide the erase command because this function is performed automatically during device programming. If you are required to erase the controller, first use the clear buffer command then program the controller, this will erase the controller and also set the AVR device fuses to default setting.
TOUCH PANEL REMOTE
MICROCONTROLL ER (AVR)
RF Tx MODULE
MICROCONTROLL ER (AVR)
RF Rx MODULE
The project consists of 2 sections viz. the transmitter and the receiver. The working of the two sections can be explained as follows:
TRANSMITTER: The remote control acts as the transmitter. It is a touch panel in which four LEDs have been connected such that they face in different directions i.e. up, down, left and right. Opposite each led, a light dependant resistor (LDR) has been placed. When the remote is in working mode, light from LED continuously falls on the LDR. In this condition, the LDR offers very less resistance and so, the transistor gets forward biased. Due to this, the transistor is turned on and it acts as a drain. The pin of the micro controller to which this has been connected remains low. Now, when we want to move the car in a particular direction, we block the path of light from the led to the LDR. This results in increase of LDR resistance and the voltage across the base drops. This in turn switches off the transistor and the corresponding microcontroller pin receives 5V. This is the same for all four directions. Each of these microcontroller pins is in turn connected to another arrangement of a resistor and a transistor acting as a NOT gate. So, whenever we block the light, the corresponding pin of the radio transmitter gets low and a signal is sent to the receiver.
_________________ INTERFACING OF AVR WITH TOUCHPANEL AND RF TRANSMITTER MODULE
RECEIVER: The radio receiver has been fitted on the chassis of the car. The receiver consists of an RF module in which H-Bridges are connected to the demodulator IC. When the receiver senses a signal to move in a particular direction, a pin on the IC gets high. This pin is also connected to a pin of the receiver’s microcontroller. When the H-Bridge gets the pulse, the DC motor starts working and the car moves in the required direction. There are two DC motors: one to control the front and rear movement of the car and the other to turn the car left or right. The rotational motion of the DC motor along with the gears steers the car in either direction. Along with this, the LCD on the back of the car shows the direction in which the car is moving.
.include"m8def.inc" .org 0x0000 main: ldi out ldi out r16,$30 spl,r16 r16,$04 sph,r16
rcall initializedata in r17,pinb andi r17,$01 cpi brne in andi cpi brne in andi cpi brne in andi cpi brne ldi out rjmp r17,$00 upmotor r17,pinb r17,$02 r17,$00 downmotor r17,pinb r17,$04 r17,$00 leftmotor r17,pinb r17,$08 r17,$00 rightmotor r18,$ff portd,r18 main
cbi portd,0 rcall delay ret Cbi portd,1 rcall delay ret cbi portd,2 rcall delay ret
cbi portd,0 rcall delay ret ldi out out ret ldi dec brne Ret r18,$ff portb,r18 portd,r18 r18,$ff r18 delay
.include"m8def.inc" .org 0x0000 main: ldi out ldi out ldi rcall ldi rcall ldi rcall ldi rcall ldi rcall r16,$04 sph,r16 r16,$30 spl,r16 r16,$38 command_reg r16,$0e command_reg r16,$01 command_reg r16,$06 command_reg r16,$80 command_reg
ldi r16,$30 rcall data_reg rjmp here
command_reg:NOP rcall delay1 out portd,r16 cbi portb,0 cbi portb,1 sbi portb,2 rcall delay cbi portb,2 ret data_reg: Rcall delay1 out portd,r16 sbi portb,0 cbi portb,1
sbi portb,2 rcall delay cbi portb,2 Ret ready: rjmp sbi cbi sbi cbi rcall sbi sbis rjmp nop ret ldi dec brne ret ldi ldi ldi dec brne dec brne dec brne ret delay1 portd,7 portb,0 portb,1 portb,2 delay portb,2 portd,7 back r17,$ff r17 delay r18, $20 r19, $ff r20, $ff r20 l1 r19 l2 r18 l3
delay1: l3: l2: l1:
RF ADVANTAGES: Not line of sight Not blocked by common materials Longer range Not sensitive to light/weather/environmental conditions
RF DISADVANTAGES: Interference: communication devices using similar frequencies - wireless phones, scanners, wrist radios and personal locators can interfere with transmission Lack of security: easier to "eavesdrop" on transmissions since signals are spread out in space rather than confined to a wire Higher cost than infrared Lower speed: data rate transmission is lower than wired and infrared transmission 29
The RF frequency used is low. So the range of the device is limited. This can be corrected by using an RF module of higher frequency range. The car has a limited degree of rotation and has to cover a large distance to turn around. This limitation can be overcome by making certain mechanical changes viz. using two different controls for the front wheels.
The project can be extended to develop an automatic car which works in accordance with the commands given through a computer interface. In this system codes would be sent to the computer which will be translated into directions by the receiver A car navigation system using artificial intelligence and fuzzy logic and implemented in Matlab can also be developed.
1. Nemzow, Martin. 1995. Implementing Wireless Networks. New York: McGraw-Hill. 2. Resnick, Robert and Halliday, David. 1988. Fundamentals of Physics: Third Edition Extended. Toronto: John Wiley & Sons. 3. FitzGerald, Jerry and Eason, Tom S. 1978. Fundamentals of Data Communications. New York: John Wiley & Sons. 4. AVR Datasheet ( www.atmel.com/literature/avr) 5. LCD Datasheet (www.datasheets.com/lcd)