You are on page 1of 4

Curriculum
Index
Knowledge Control
Dictionary
Contact
List O !eerence
m
e
n
u

Main page Last update "#\$#%\$#&"& #"'"#'#(

3 Counters
In t)is section we examine special types o addition and subtraction operations* w)ic) are used or t)e purpose o counting+ In
particular* we want to design circuits t)at can increment or decrement a count by "+ Counter circuits are used in digital systems or
many purposes+ T)ey may count t)e number o occurrences o certain events* generate timing intervals or control o various tasks in
a system* keep track o time elapsed between speciic events* and so on+
Counters can be implemented using t)e adder\$subtractor circuits and t)e registers+ ,owever* since we only need to c)ange
t)e contents o a counter by "* it is not necessary to use suc) elaborate circuits+ Instead* we can use muc) simpler circuits t)at )ave
a signiicantly lower cost+ -e will s)ow )ow t)e counter circuits can be designed using T and D lip.lops+
3.1 Asynchronous counters
T)e simplest counter circuits can be built using T lip.lops because t)e toggle eature is naturally suited or t)e implementation
o counting operation+
3.1.1 Up-Counter with !"ip-!"ops
/igure "a gives a t)ree.bit counter capable o counting rom & to %+ T)e clock inputs o t)e t)ree lip.lops are connected in
cascade+ T)e T input o eac) lip.lop is connected to a constant "* w)ic) means t)at t)e state o t)e lip.lop will be reversed
0toggled1 at eac) positive edge o its clock+ -e are assuming t)at t)e purpose o t)is circuit is to count t)e number o pulses t)at
occur on t)e primary input called Clock+ T)us t)e clock input o t)e irst lip.lop is connected to t)e Clock line+ T)e ot)er two lip.lops
)ave t)eir clock inputs driven by t)e Q output o t)e preceding lip.lop+

1 of 4 26/06/2014 23:32
/igure " A t)ree.bit up.counter+

T)ereore* t)ey toggle t)eir state w)enever t)e preceding lip.lop c)anges its state rom Q 2 " to Q 2 &* w)ic) results in a
positive edge o t)e Q signal+
/igure "b s)ows a timing diagram or t)e counter+ T)e value o Q& toggles once eac) clock cycle+ T)e c)ange takes place
s)ortly ater t)e positive edge o t)e Clock signal+ T)e delay is caused by t)e propagation delay t)roug) t)e lip.lop+ 3ince t)e second
lip.lop is clocked by Q&* t)e value o Q" c)anges s)ortly ater t)e negative edge o t)e Q& signal+ 3imilarly* t)e value o Q# c)anges
s)ortly ater t)e negative edge o t)e Q" signal+ I we look at t)e values Q#Q"Q& as t)e count* t)en t)e timing diagram indicates t)at
t)e counting se4uence is &* "* #* 5* (* 5* 6* %* &* "* and so on+ T)is circuit is a modulo.6 counter+ 7ecause it counts in t)e upward
direction* we call it an up-counter+
T)e counter in /igure "a )as t)ree stages* eac) comprising a single lip.lop+ Only t)e irst stage responds directly to t)e Clock
signal8 we say t)at t)is stage is synchronized to t)e clock+ T)e ot)er two stages respond ater an additional delay+ /or example* w)en
Count 2 5* t)e next clock pulse will cause t)e Count to go to (+ As indicated by t)e arrows in t)e timing diagram in /igure "b* t)is
c)ange re4uires t)e toggling o t)e states o all t)ree lip.lops+ T)e c)ange in Q& is observed only ater a propagation delay rom t)e
positive edge o Clock+ T)e Q" and Q# lip.lops )ave not yet c)anged8 )ence or a brie count is &&&+
/inally* t)e c)ange in Q# occurs ater a t)ird delay* at w)ic) point t)e stable state o t)e circuit is reac)ed and t)e count is
"&&+ T)is be)avior is similar to t)e rippling o carries in t)e ripple.carry adder circuit+ T)e circuit in /igure "a is an asynchronous
counter* or a ripple counter+
3.1.# \$own-Counter with !"ip-!"ops
A slig)t modiication o t)e circuit in /igure "a is presented in /igure #a+ T)e only dierence is t)at in /igure #a t)e clock inputs
o t)e second and t)ird lip.lops are driven by t)e Q outputs o t)e preceding stages* rat)er t)an by t)e Q outputs+ T)e timing
diagram* given in /igure #b* s)ows t)at t)is circuit counts in t)e se4uence &* %* 9* :* (* 5* #* "* &* %* and so on+ 7ecause it counts in
t)e downward direction* we say t)at it is a down-counter+
It is possible to combine t)e unctionality o t)e circuits in /igures "a and #a to orm a counter t)at can count eit)er up or
down+ 3uc) a counter is called an up/down-counter+ -e leave t)e derivation o t)is counter as an exercise or t)e reader+

2 of 4 26/06/2014 23:32
/igure # A t)ree.bit down.counter

3.# %ynchronous counters
T)e async)ronous counters in /igures "a and #a are simple* but not very ast+ I a counter wit) a larger number o bits is
constructed in t)is manner* t)en t)e delays caused by t)e cascaded clocking sc)eme may become too long to meet t)e desired
perormance re4uirements+ -e can build a aster counter by clocking all lip.lops at t)e same time* using t)e approac) described
below+
Table " s)ows t)e contents o a t)ree.bit up.counter or eig)t consecutive clock cycles* assuming t)at t)e count is initially &+
Observing t)e pattern o bits in eac) row o t)e table* it is apparent t)at bit Q& c)anges on eac) clock cycle+ 7it Q" c)anges only w)en
Q& 2 "+ 7it Q# c)anges only w)en bot) Q" and Q& are e4ual to "+ In general* or an n.bit up.counter* a given lip.lop c)anges its
state only w)en all t)e preceding lip.lops are in t)e state Q 2 "+ T)ereore* i we use T lip.lops to reali;e t)e counter* t)en t)e T
inputs are deined as
T& 2 "
T" 2 Q&
T# 2 Q& Q"
T5 2 Q& Q" Q#
+ + +
+ + +
+ + +
Tn 2 Q& Q" < Qn."
An example o a our.bit counter based on t)ese expressions is given in /igure 5a+ Instead o using AND gates o increased
si;e or eac) stage* w)ic) may lead to an.in problems* we use a actored arrangement* as s)own in t)e igure+ T)is arrangement
does not slow down t)e response o t)e counter* because all lip.lops c)ange t)eir states ater a propagation delay rom t)e positive
edge o t)e clock+

Table " Derivation o t)e sync)ronous up.counter