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CHAPTER-5

DSPIC2010 AND ITS DETAILS



Overview of DSPIC30F Device family
The dsPIC30F device family employs a powerful 16-bit architecture that seamlessly integrates the
control features of a microprocessor (MCU) with the computational capabilities of a digital signal
processor (DSP). The resulting functionality is ideal for applications that rely on high-speed,
repetitive computations as well as control. The DSP engine, dual 40-bit accumulators, hardware
support for division operations, barrel shifter, 17 17 multiplier, a large array of 16-bit working
registers and a wide variety of data addressing modes, together provide the dsPIC30F CPU with
extensive mathematical processing capability. Flexible and deterministic interrupt handling, coupled
with a powerful array of peripherals, renders the DSPIC30F devices suitable for control applications.
Reliable, field programmable flash program memory and data EEPROM ensure scalability of
applications that use dsPIC30F devices. At the time if writing all dsPIC30F devices use Flash
program memory technology. The flash program memory can be electrically erased or programmed.
5.1 The prominent features of DSPIC30F are:
High current sink/source I/O pins: 25Ma /25Ma.
Three 16-bit timers/counters: optionally pair up.
16-bit timers into 32-bit timer modules.
Four 16-bit capture input functions.
Two 16-bit compare/PWM output functions.
Dual compare mode available.
3-wire SPITM modules (supports 4 frame modes).
12CTM module supports Multi-Master/Slave mode and 7-bit/10-bit addressing.
Addressable UART modules with FIFO buffers.


5.1.1 High-performance Modified RISC CPU:
Modified Harvard architecture
C compiler optimized instruction set architecture
84 base instructions with flexible addressing modes
24-bit wide instructions, 16-bit wide data path
12 Kbytes on-chip Flash program space
512 bytes on-chip data RAM
1 Kbyte non-volatile data EEPROM
16 x 16-bit working register array
Up to 30 MIPs operation:
DC to 40 MHz external clock input
4MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x).
27 interrupt sources.
Three external interrupt sources.
8 user selectable priority levels for each interrupt.
4 processor exceptions and software traps.
5.1.2 DSP Engine Features:
Modulo and Bit-Reversed modes
Two, 40-bit wide accumulators with optional saturation logic.
17-bit x 17-bit single cycle hardware fractional/integer multiplier.
Single cycle Multiply-Accumulate (MAC) operation.
40-stage Barrel Shifter.
Dual data fetch.
5.1.3 Peripheral Features:
High current sink/source I/O pins: 25 mA/25 mA.
Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules.
Four 16-bit Capture input functions.
Two 16-bit Compare/PWM output functions.
Dual Compare mode available.
3-wire SPITM modules (supports 4 Frame modes).
I
2
C
TM
module supports Multi-Master/Slave mode and 7-bit/10-bit addressing.

5.1.4 Motor Control PWM Module Features:
6 PWM output channels
Complementary or Independent Output modes
Edge and Center Aligned modes
4 duty cycle generators
Dedicated time base with 4 modes.
Programmable output polarity.
Dead time control for Complementary mode.
Manual output control.
Trigger for synchronized A/D conversions.




5.1.5 Quadrature Encoder Interface Module Features:

Phase A, Phase B and Index Pulse input.
16-bit up/down position counter.
Count direction status.
Position Measurement (x2 and x4) mode.
Programmable digital noise filters on inputs..
Alternate 16-bit Timer/Counter mode.
Interrupt on position counter rollover/underflow.







5.1.6 Analog Features:

10-bit Analog-to-Digital Converter (A/D) with:
500 Kbps (for 10-bit A/D) conversion rate.
Six input channels.
Conversion available during Sleep and Idle.
Programmable Brown-out Detection and Reset generation.

5.1.7 Special Microcontroller Features:

Enhanced Flash program memory:
10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical).
Data EEPROM memory:
100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical).
Self-reprogrammable under software control.
Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST).
Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable
operation.
Fail-Safe clock monitor operation.
Detects clock failure and switches to on-chip low power RC oscillator.
Programmable code protection.
In-Circuit Serial Programming (ICSP).
Selectable Power Management modes Sleep, Idle and Alternate Clock modes.
5.1.8 CMOS Technology:

Low power, high speed Flash technology.
Wide operating voltage range (2.5V to 5.5V).
Industrial and Extended temperature ranges.
Low power consumption.




5.2 Block Diagram of DSPIC30F2010

The block diagram of DSPIC30F2010 is as shown in fig 5.1. The DSPIC30F2010 device contains
extensive Digital signal processor (DSP) functionality within high-performance 16-bit
microcontroller (MCU) architecture. The core has a 24-bit instruction word. The program counter
(PC) is 23 bits wide with the least significant (LS) bit always clear, and the Most significant (MS) bit
is ignored during normal program execution, except for certain specialized instructions. Thus, the PC
can address up to 4M instruction words of user program space. An instruction pre-fetch mechanism
is used to help maintain throughput. Program loop constructs, free from loop count management
overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at
any point.
The working register array consists of 16x16-bit registers, each of which can act as data, address or
offset registers. One working register (W15) operates as a software stack pointer for interrupts and
calls. The data space is 64 Kbytes (32K words) and is split into two blocks, referred to as X and Y
data memory.
Each block has its own independent Address Generation Unit (AGU). Most instructions operate
solely through the X memory AGU, which provides the appearance of a single unified data space.
The Multiply-Accumulate (MAC) classes of dual source DSP instructions operate through both the
X and Y AGUs, splitting the data address space into two parts. The X and Y data space boundary is
device specific and cannot be altered by the user. Each data word consists of 2 bytes, and most
instruction scan address data either as words or bytes.
There are two methods of accessing data stored in program memory:
The upper 32 Kbytes of data space memory can be mapped into the lower half (user space) of
program space at any 16K program word boundary, defined by the 8-bit Program Space
Visibility Page (PSVPAG) register. This lets any instruction access program space as if it
were data space, with a limitation that the access requires an additional cycle. Moreover, only
the lower 16 bits of each instruction word can be accessed using this method.
Linear indirect access of 32K word pages within program space is also possible using any
working register, via table read and writes instructions. Tables read and write instructions can
be used to access all 24 bits of an instruction word. Overhead-free circular buffers (modulo
addressing) are supported in both X and Y address spaces. This is primarily intended to
remove the loop overhead for DSP algorithms.

The X AGU also supports bit-reversed addressing on destination effective addresses, to greatly
simplify input or output data reordering for radix-2 FFT algorithms. The core supports Inherent (no
operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and
Literal Offset Addressing modes.

Instructions are associated with predefined Addressing modes, depending upon their functional
requirements. For most instructions, the core is capable of executing data (or program data) memory
read, a working register (data) read, a data memory write and a program (instruction) memory read
per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A+B operations
to be executed in a single cycle. A DSP engine has been included to significantly enhance the core
arithmetic capability and throughput. It features a high speed 17-bit by 17-bit multiplier, a 40-bit
ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter.

Data in the accumulator or any working register can be shifted up to 15 bits right or 16 bits left in a
single cycle. The DSP instructions operate seamlessly with all other instructions and have been
designed for optimal real-time performance. The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two W registers. To enable this concurrent
fetching of data operands, the data space has been split for these instructions and linear for all others.
This has been achieved in a transparent and flexible manner, by dedicating certain working registers
to each address space for the MAC class of instructions. The core does not support a multi-stage
instruction pipeline. However, a single stage instruction pre-fetch mechanism is used, which
accesses and partially decodes instructions a cycle ahead of execution, in order to maximize
available execution time. Most instructions execute in a single cycle, with certain exceptions.
The core features a vectored exception processing structure for traps and interrupts, with 62
independent vectors. The exceptions consist of up to 8 traps (of which 4 are reserved) and 54
interrupts. Each interrupt is prioritized based on a user assigned priority between 1 and 7 (1 being the
lowest priority and 7 being the highest) in conjunction with a predetermined natural order. Traps
have fixed priorities, ranging from 8 to 15.


Fig 5.1: Block diagram of DSPIC30F2010



5.3 Pin Diagram of DSPIC30F2010:
The DSPIC30F2010 is a 28-pin enhanced flash 16-bit Digital signal controller, its pin configuration
is as shown in fig 5.2. Each pin is used to perform different functions.

Fig 5.2: Pin configuration of DSPIC30F2010

Table 5.1 provides a brief description of device I/O pin outs and the functions that may be
multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs,
the peripheral modules functional requirements may force an override of the data direction of the
port pin.









Table 4.1 Pin description of DSPIC30F2010


Table 4.1 Pin description of DSPIC30F2010 (continued)






PRODUCT IDENTIFICATION SYSTEM


5.5 Comparison of DSPIC30F Motor Control and power conversion family
Table 5.2 provides the comparison of different digital signal controller i.e dspic30F series. In the
table 5.2 seven DSPIC controllers (DSPIC30F2010, DSPIC30F3010, DSPIC30F4012,
DSPIC30F3011, DSPIC30F4011, DSPIC30F5015 and DSPIC30F6010) are compared and they are
differentiated in terms of their pin numbers, memory, PWM channels, A/D converters etc. All these
devices supports Quadrature encoder interface.
The DSPIC30F2010, DSPIC30F3010, DSPIC30F4012 have 28 number of pins, while the pin
numbers of DSPIC30F3011 and DSPIC30F4011 vary from 40-44, dsPIC30F5015 has 64 and
dsPIC30F6010 has 80 number of pins respectively. The memories of these devices vary from 12K to
144K DSPIC30F5015 and DSPIC30F6010 have 8 motor control PWM channels while others have
6PWM channels. Depending on the requirement of the system output we will select the desired
digital signal controller. In this work we have used DSPIC30F2010 controller
Table 5.2 Comparison of Different Digital signal controllers.












CHAPTER-6
DESIGN AND DEVELOPMENT OF HARDWARE
The block diagram of the complete proposed three phase PWM rectifier is shown in the figure. It
consists of following blocks:
1. DC regulated power supply.
2. Microcontroller (DSPIC30F2010).
3. Gate drive circuit.
4. Three phase PWM rectifier.
5. Voltage sensor.
6. Boost converter.
6.1 DESIGN OF DC REGULATED POWER SUPPLY
DC power is required for various sections of the proposed system. The different DC voltages
required are:
1. +5v for DSPIC.
2. +12V for gate firing pulses to IGBT.
The following components are used in dc regulated power supply:
1. Five sets of four diodes (D1, D2, D3, and D4).
2. Capacitor C1 (100F), C2 (1000F).
3. Voltage regulators (LM7805 and LM78012)
4. Step down transformers 0-12V.




+5V SUPPLY UNIT:
The circuit diagram of +5v is shown in fig. The +5v supply is obtained from the +5v supply unit for
DSPIC30F2010 controller. Initially 230V AC supply is reduced to (0-9V) with the help of a step
down transformer having a capacity of 500ma. Since the input voltage to the regulator IC should be
more than its output voltage, transformer secondary voltage is 9V.
This low voltage is rectified with the help of bridge rectifier. Here IN4001 diodes are used. The
rectified output contains ripples, so to eliminate those ripples we have used filter capacitor to get a
smooth DC supply. The rating of the chosen filter capacitor is 100 F, 35v.The DC regulated voltage
is obtained by using a regulator IC7805.In this case of 7805, the unregulated DC voltage is applied
to pin1, and the output is taken at pin 3 and pin 2 is grounded.
PLEASE PROVIDE THE CIRCUIT DIAGRAM.
+12V SUPPLY UNIT.
The circuit diagram of +12V is as shown in the figure. 230V supply is step down with the help of a
transformer. An unregulated, input voltage V
in
is filtered by capacitor C, and connected to the pin 1
of IC7812.The pin 2 (OUT terminal) of the IC provides a regulated +12V which is filtered by
capacitor C2. The pin3 of the IC is connected to ground.
PLEASE PROVIDE THE CIRCUIT DIAGRAM
6.2 DESIGN OF CONTROL UNIT USING DSPIC30F2010
Components used:
1. Crystal oscillator: KDS 8.000MHZ.
2. Capacitor: 1F, 22pF
3. Resistors: 1k.
Fig shows the design of control circuit. The control circuit of the proposed scheme consists of a
Digital signal controller DSPIC30F2010 and gate drive circuit for the generation of pulses of
frequencies. The microcontroller is operated at 8MHZ crystal frequency. DSC controls power
switches in the inverter circuit. The internal timer is used as a clock to determine the timing and a
counter is used for counting the pulses from the proximity sensor.
According to the requirement, a software program is written and is feed to the controller, which
decides the frequencies of pulses to be applied to the gate of the IGBT. The controller also decides
the instant timing of the gate signal to be given to the IGBTs, in order to avoid the overlapping in
conduction of incoming and outgoing IGBTs.The control circuit design using DSPIC30F2010 is
shown in fig. As per the design, digital oscillator is connected between pin number 9 and 10 for
generating clock frequency. Pin numbers 21 to 26 are the six PWM output channels connected to the
gate drive circuit. DSPIC is supplied by +5v V
DD
supply through pin number 28 and pin number 27
is grounded.
PLEASE PROVIDE THE FIGURE.
6.3 DESIGN OF ISOLATION AND GATE DRIVE CIRCUIT
Fig shows the isolation and gate drive circuit. The driver has two main functions:
1. To provide required gate voltage and current to IGBT for switching.
2. To transmit the control signals to the bridge circuit faithfully.
The following components are used in isolation and gate driver circuit:
1. Optocoupler :( TLP-250).
2. Capacitors C1, C2, C3, C4 (0.1F each).
3. Resistor: (R1, R2, R3 and R4)
PLEASE PROVIDE THE FIGURE
In the proposed scheme there are six IGBTs in the full bridge inverter. Separate isolator and gate
drive circuit are used to drive each IGBT. The pulses available at the output of the logic circuit are
given to two individual gate drives.
The DC supply required for the driver circuit is derived from the DC regulated power supply section.
The isolation and gate drive circuit consists of Optocoupler and Darlington amplifier. The pulses
from the controller circuit are given to pin 2 of Optocoupler through 1K resistance (R1). The output
is taken from pin number 7 and 8 and this is given to gate of the IGBT.


6.4 DESIGN OF PWM CONVERTER
PLEASE PROVIDE THE FIGURE
The following components are used in PWM converter.
1. MOSFETS-IRFP460.
2. Diodes UF5408.
SELECTION OF POWER MOSFETS
The selection of MOSFET is done on the basis of voltage, current and power rating of the load also
the maximum reverse voltage available across its source and drain terminals are taken into
consideration.
The maximum reverse voltage which is same as the dc link voltage is given by the equation. The
switches are selected in such a way that the voltage and current rating of the switch should be 5 to7
times than the rated voltage and current of the motor.
The maximum reverse voltage is given by:
V
avg =
V
dc =
(2*V
max
)/
= (2*2*V
S
)/
= (2*2*230)/
= 207.07V.
Here we selected FPGA25N120ANTD-IGBTs to meet the requirement. It has the following voltage
and current rating:
Voltage rating: 1200V
Current rating: 25A
The IGBTs is selected on the basis of voltages, current, power ratings of the load and maximum
reverse voltage available across its source and drain terminals.
6.5 DESIGN OF VOLTAGE SENSOR.
The voltage sensor used here is ACS714. It is an 8-pin IC.The pin diagram of the IC is shown in
figure below. The first two pins (pin-1 and pin-2) are connected to the pwm converter circuit.Pin-3
and pin-4 are shorted and connected to the boost inductors. Pin-5 is grounded and pin-6 is connected
to 1F capacitor. The output of the sensor is taken from pin-7. The ACS714 sensor is powered from
a +5V supply connected to pin-8. The pin-8 is connected to ground through 0.1f capacitor. The pin
diagram of ACS714 is shown in fig below
The device consists of a precise, low-offset, linear Hall circuit with a copper conduction path located
near the surface of the die. Applied current flowing through this copper conduction path generates a
magnetic field which the Hall IC converts into a proportional voltage. Device accuracy is optimized
through the close proximity of the magnetic signal to the Hall transducer. A precise, proportional
voltage is provided by the low-offset, chopper-stabilized BiCMOS Hall IC, which is programmed
for accuracy after packaging. The output of the device has a positive slope (>VIOUT (Q)) when an
increasing current flows through the primary copper conduction path (from pins 1 and 2, to pins 3
and 4), which is the path used for current sampling. The internal resistance of this conductive path is
1.2 m typical, providing low power loss. The thickness of the copper conductor allows survival of
the device at up to 5 over current conditions. The terminals of the conductive path are electrically
isolated from the signal leads (pins 5 through 8). This allows the ACS714 to be used in applications
requiring electrical isolation without the use of opto-isolators or other costly isolation techniques.

Fig: Pin diagram of ACS714.
6.6 BOOST CONVERTER:
There are three boost inductors used in this project. Three phase supply is given to the boost
inductors

DOUBTS
1. What is the value of Boost inductors?
2. What are the ratings of three-phase voltage to be applied?
3. What is the expected rating of input current that is sensed by the input current sensor?
4. Please provide the modified diagram of PWM rectifier including the general purpose diodes
and MOSFETS?
5. Please provide me the circuit diagram of Gate drive circuit and power supply?
6. What is the rating of PWM pulses generated by controller?
7. For how much rating of car wiper motor should I purchase?
8. What is the rating of fuses used at the input?
9. Whether we should provide three-phase supply in star or delta connection?
10. What is the expected final output voltage to be measured in CRO?