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A dissertation submitted in partial fulfillment of the requirement for the degree of Master of Science (Research)

by G. Venkateshwar Reddy

Under the Supervision of Dr. M. Jagadesh Kumar

Indian Institute of Technology, Delhi Oct, 2004

CERTIFICATE

This is to certify that the thesis entitled MODELING AND SIMULATION OF NANOSCALE SOI MOS TRANSISTORS WITH REDUCED SHORT-CHANNEL EFFECTS being submitted by G. Venkateshwar Reddy to the Indian Institute of Technology, Delhi, for the award of the degree of Master of Science (Research) in Electrical Engineering Department is a bona fide work carried out by him under my supervision and guidance. The research reports and the results presented in this thesis have not been submitted in parts or in full to any other University or Institute for the award of any other degree or diploma.

Date: 05-10-2004 Place: IIT, Delhi

Dr. M. Jagadesh Kumar Associate Professor Department of Electrical Engineering Indian Institute of Technology New Delhi - 110016

iii

ACKNOWLEDGEMENTS

I wish to express my sincere gratitude to my supervisor Dr. M. Jagadesh Kumar for his invaluable guidance and advice during every stage of this endeavour. I am greatly indebted to him for his continuing encouragement and support without which, it would not have been possible for me to complete this undertaking successfully. His insightful comments and suggestions have continually helped me to improve my understanding. Special thanks are due to Prof. D. Nagchoudhuri for his valuable suggestions and questions during my semester plan presentation. I am grateful to Prof. G. S. Visweswaran for allowing me to use the laboratory facilities at all points of time. My special thanks to my friends Linga, Anurag, Vinod, Sukhendu and others, who always inspired me and particularly helped me in difficult times. My sincere thanks and acknowledgements are due to all my family members who have constantly encouraged me for completing this project.

G. Venkateshwar Reddy

v

ABSTRACT

Silicon-on-insulator (SOI) technology has been receiving a lot of attention owing to its advantages in reduced second-order effects for VLSI applications and has been the forerunner of the CMOS technology in the last decade offering superior CMOS devices with higher speed, higher density and excellent radiation hardness. Many novel device structures have been reported in literature to address the challenge of short-channel effects (SCE) and higher performance for deep submicron VLSI integration. However, most of the proposed structures do not offer simultaneous SCE suppression and improved circuit performance. To simultaneously suppress SCE and improve device performance, the Dual Material Gate (DMG) structure was proposed. By a careful control of the material workfunction and length of the laterally amalgamated gate materials optimum performance can be attained in a DMG structure. In this thesis, a physics based analytical model of surface potential along the channel in a PD DMG SOI MOSFET is developed by solving 2-D Poisson’s equation. The model is used to investigate the excellent immunity against SCE offered by the DMG structure. Further the model is used to formulate an analytical expression of the threshold voltage, Vth. The results clearly demonstrate the scaling potential of DMG SOI devices with a desirable threshold voltage “roll-up” observed with decreasing channel lengths. Double Gate (DG) MOSFETs using lightly doped ultra thin layers seem to be another very promising option for ultimate scaling of CMOS technology. Excellent shortchannel effect immunity, high transconductance and ideal subthreshold factor have been reported by many theoretical and experimental studies on this device. To incorporate the advantages of both DG and DMG structures, we have proposed a new structure, the DualMaterial Double-Gate (DMDG) SOI MOSFET that is similar to that of an asymmetrical DG SOI MOSFET with the exception that the front gate of the DMDG structure consists of two materials (p+ poly and n+ poly). An analytical model using Poisson’s equation also has been presented for the surface potential leading to the threshold voltage model for the DMDG SOI MOSFET. A complete drain current model considering impact ionization, velocity overshoot, channel length modulation and DIBL is also presented. The results

vii

clearly suggest the superiority of the proposed structure over the conventional DG SOI MOSFET. Another widely used approach to alleviate the short channel performance is through channel engineering. Asymmetric single halo MOSFET structures have been introduced for bulk as well as for SOI MOSFETs to adjust the threshold voltage and improve the device SCE. Simulation studies have been done on channel engineering concept when applied to a DG structure. Our results reveal that the channel engineering concept indeed provides an improved performance over the conventional DG structure.

viii

TABLE OF CONTENTS

CERTIFICATE ............................................................................................................................................. iii ACKNOWLEDGEMENTS.............................................................................................................................v ABSTRACT ................................................................................................................................................. vii TABLE OF CONTENTS ...............................................................................................................................ix LIST OF TABLES .........................................................................................................................................xi LIST OF ILLUSTRATIONS....................................................................................................................... xiii

CHAPTER I.................................................................................................................................................1 INTRODUCTION...........................................................................................................................................1 1.1. 1.2. 1.3. 1.4. 1.5. MOTIVATION FOR PRESENT RESEARCH ........................................................................................1 NATURE OF THE PROBLEM ............................................................................................................5 RECENT RESEARCH RELEVANT TO THE PROBLEM .........................................................................5 RESEARCH PROBLEM STATEMENT ................................................................................................7 THESIS ORGANIZATION..................................................................................................................7

CHAPTER II ...............................................................................................................................................9 ANALYTICAL MODELING OF SURFACE POTENTIAL AND THRESHOLD VOLTAGE IN A PARTIALLY DEPLETED (PD) DMG-SOI MOSFET ..................................................................................9 2.1. 2.2. 2.3. 2.3.1 2.3.2 2.4. 2.4.1 2.4.2 2.4.3 2.4.4 2.5. INTRODUCTION..............................................................................................................................9 DMG SOI STRUCTURE AND ITS PARAMETERS ............................................................................10 MODEL FORMULATION........................................................................................................11 Two-Dimensional Potential Analysis .........................................................................................11 Threshold Voltage Model ...........................................................................................................19 RESULTS AND DISCUSSION ..........................................................................................................20 Surface Potential and Electric Field ..........................................................................................20 Minimum Surface Potential and Threshold Voltage...................................................................22 Substrate Bias dependence .........................................................................................................24 Gate Material Engineering.........................................................................................................27 SUMMARY ...................................................................................................................................28

CHAPTER III............................................................................................................................................29 A NEW DUAL MATERIAL DOUBLE GATE NANOSCALE SOI MOSFET − TWO DIMENSIONAL ANALYTICAL MODELING AND SIMULATION....................................................................................29 3.1. 3.2. 3.3. 3.3.1 3.3.2 3.3.3 a) b) c) INTRODUCTION............................................................................................................................29 DMDG SOI STRUCTURE AND ITS PARAMETERS .........................................................................31 MODEL FORMULATION .............................................................................................................32 Surface Potential Model .............................................................................................................32 Threshold Voltage Model ...........................................................................................................38 IV Model.....................................................................................................................................41 The impact ionization and parasitic BJT effects.........................................................................42 The channel length modulation, velocity overshoot and DIBL effects .......................................45 Total drain current .....................................................................................................................46

ix

3.4. 3.4.1 3.4.2 3.4.3 3.5.

RESULTS AND DISCUSSION ..........................................................................................................47 Surface Potential and Electric Field ..........................................................................................48 Threshold Voltage and Drain Induced Barrier Lowering ..........................................................52 IV Characteristics.......................................................................................................................54 SUMMARY ...................................................................................................................................57

CHAPTER IV ............................................................................................................................................59 INVESTIGATION OF THE NOVEL ATTRIBUTES OF A SINGLE HALO DOUBLE GATE SOI MOSFET: 2D SIMULATION STUDY ........................................................................................................59 4.1. 4.2. 4.3. 4.3.1 4.3.2 4.3.3 4.3.4 4.4. INTRODUCTION............................................................................................................................59 DG-SH STRUCTURE AND ITS PARAMETERS .................................................................................61 RESULTS AND DISCUSSION ..........................................................................................................61 Surface Potential ........................................................................................................................62 Threshold Voltage and DIBL......................................................................................63 Subthreshold Slope and On/Off Currents...................................................................................66 IV Characteristics.......................................................................................................................68 SUMMARY ...................................................................................................................................71

CHAPTER V..............................................................................................................................................73 CONCLUSIONS ...........................................................................................................................................73 APPENDICES...............................................................................................................................................77 REFERENCES..............................................................................................................................................85 LIST OF PUBLICATIONS...................................................................................................................................89

x

LIST OF TABLES

Table Table 3.1 Table 4.1 Device parameters used in the model and the simulation of the DMDG and the DG SOI MOSFETs. Device parameters used for the simulation of the DG-SH and the DG SOI MOSFETs. Page 47 61

xi

LIST OF ILLUSTRATIONS

Figure 1.1 Cross-sectional view of the PD (left) and FD (right) SOI CMOS devices Cross-sectional view of an n-channel partially depleted DMG SOI MOSFET. Surface potential profiles of a partially depleted SOI MOSFET obtained from the analytical model and MEDICI simulation for different drain biases with a channel length L = 0.15µm(L1 = 0.05µm and L2 = 0.1µm). Electric field along the channel towards the drain end obtained from the analytical model and MEDICI simulation in DMG-SOI and SMGSOI MOSFET’s with a channel length L = 0.15µm and a drain bias VDS = 1.75V. Variation of the channel minimum potential with channel length L (=L1+L2) for partially depleted DMG-SOI MOSFET’s with L1 constant at 50µm. Threshold voltage variation with channel length for DMG SOI device compared between MEDICI simulations and model prediction with L1 constant at 50µm. Threshold voltage variation versus channel length at a fixed back gate bias of φB = 1V with L1 constant at 50µm. Threshold voltage variation versus back gate bias φB with a channel length L=0.2µm (L1=0.05µm, L2=0.15µm). Threshold voltage variation versus back gate bias φB with a channel length L=0.2µm (L1 = 0.05µm, L2 = 0.05µm). Threshold voltage variation with gate work function difference with φM2 fixed at 4.17eV for the DMG-SOI MOSFET with channel length L (=L1+L2) of 0.25µm. Page 2

2.1

11

2.2

21

2.3

22

2.4

23

2.5

24

2.6

25

2.7(a)

26

2.7(b)

26

2.8

27

xiii

3.1

Cross-sectional view of (a) DG-SOI MOSFET (b) DMDG-SOI MOSFET. Surface potential profiles of DMDG and DG-SOI MOSFETs for a channel length L = 0.1µm (L1 =L2 = 0.05µm). Surface potential profiles at front gate and back gate for DMDG and DG-SOI MOSFETs for a channel length L = 0.1 µm (L1 = L2 = 0.05 µm). Back gate surface potential profiles for different film thicknesses for DMDG SOI MOSFETs for a channel length L = 0.1 µm (L1 = L2 = 0.05 µm). Electric-field variation at the drain end along the channel at the SiSiO2 interface of DMDG and DG SOI MOSFETs for a channel length L = 0.1µm (L1 =L2 = 0.05µm). Threshold voltage of DMDG and DG SOI MOSFETs is plotted for different channel lengths (L1 fixed at 0.05µm). DIBL of DMDG and DG SOI MOSFETs is plotted for different channel lengths, L=L1 + L2 where L1 = L2. The parameters used are tox =2nm tb = 3nm, tsi = 20nm. ID - VDS characteristics of the DMDG and DG-SOI MOSFETs for a channel length L = 0.1µm Variation of gm with different channel lengths, (L1 = L2) for DMDG and DG SOI MOSFETs. Variation of gd with different channel lengths, (L1 = L2) for DMDG and DG SOI MOSFETs. Variation of voltage gain with different channel lengths, (L1 = L2) for DMDG and DG SOI MOSFETs. Cross-sectional view of (a) DG-SOI MOSFET (b) DG-SH SOI MOSFET Surface potential profiles of DG-SH and DG-SOI MOSFETs for channel lengths 0.1µm and 0.2µm

31

3.2

50

3.3

50

3.4

51

3.5

51

3.6

53

3.7

53

3.8

55

3.9

55

3.10

56

3.11

56

4.1

60

4.2

63

xiv

with a film thickness of 20nm. 4.3 Threshold voltage of DG-SH and DG SOI MOSFETs is plotted for different channel lengths for a film thickness of 20nm. Threshold voltage of DG-SH and DG SOI MOSFETs is plotted for different film thicknesses for a fixed channel length 0.1µm. DIBL of DG-SH and DG SOI MOSFETs is plotted for different channel lengths for a film thickness of 20nm. Subthreshold slope of DG-SH and DG SOI MOSFETs is plotted for different channel lengths for a film thickness of 20nm. Variation of Ioff and Ion with channel length for DG-SH and DG SOI MOSFET for a film thickness of 20nm. Ratio of Ion and Ioff with channel length for DG-SH and DG SOI MOSFET for a film thickness of 20nm at VDS= 0.75V. ID-VDS characteristics of the DG-SH and DG-SOI MOSFETs for a channel length L = 0.1µm with a film thickness of 20nm. Variation of gm, gd with different channel lengths for DG-SH and DG SOI MOSFETs. Variation of voltage gain with different channel lengths DG-SH and DG SOI MOSFETs. 64

4.4

65

4.5

65

4.6

66

4.7(a)

67

4.7(b)

67

4.8

69

4.9

70

4.10

70

xv

CHAPTER I

INTRODUCTION

1.1

Motivation For the Present Research In conventional bulk-Si microcircuits, the active elements are located in a thin

surface layer (less than 0.5 µm of thickness) and are isolated from the silicon body with a depletion layer of a P-N junction. The leakage current of this P-N junction exponentially increases with temperature, and is responsible for several serious reliability problems. Excessive leakage currents and high power dissipation limits operation of the microcircuits at high temperatures. Parasitic n-p-n and p-n-p transistors formed in neighboring insulating tubs can cause latch-up failures and significantly degrade circuit performance. Silicon-on-insulator (SOI) technology employs a thin layer of silicon (tens of nanometers) isolated from a silicon substrate by a relatively thick (hundreds of nanometers) layer of silicon oxide. The SOI technology dielectrically isolates components and in conjunction with the lateral isolation, reduces various parasitic circuit capacitances and thus, eliminates the possibility of latch-up failures. SOI technology offers superior CMOS devices with higher speed, high density, and reduced second order effects as compared to the bulk silicon technology for low-voltage and low-power VLSI circuit applications. Depending on the thickness of the silicon layer, MOSFETs will operate in fully depleted (FD) or partially depleted (PD) regimes. When the channel depletion region extends through the entire thickness of the silicon layer, the transistor operates in a FD mode. PD transistors are built on relatively thick silicon layers with the depletion depths

1

Gate oxide n+ n+ poly p

100 – 200 nm thick Si n+ p+ p+ poly n

Undepleted Si layer Gate oxide p+ n+ n+ poly p

~ 50 nm thick Si n+

100 – 400 nm buried oxide Silicon handle wafer

Depletion layer extending into handle wafer p+ poly p+ p+ n 100 – 400 nm buried oxide

Silicon handle wafer

Fig. 1.1: Cross-sectional view of the PD (left) and FD (right) SOI CMOS devices [1]. of the fully powered MOS channel shallower than the thickness of the silicon layer. Fig. 1.1 illustrates these two types of transistors. The FD devices have several advantages compared to the PD devices: free from kink effect, enhanced subthreshold swing, highest gains in circuit speed, reduced power requirements and highest level of soft-error immunity. Several drawbacks of the FD SOI design and process come along with their benefits: Although FD MOSFETS are naturally free from the kink effect, the interface coupling effect affects their operation [2-3]. The interface coupling is inherent to fully depleted SOI devices, where all parameters (threshold voltage, transconductance, interface-trap response etc.) of one channel are insidiously affected by the opposite gate voltage (at the buried oxide). The threshold voltage fluctuation due to SOI thickness variation is one of the most serious problems in FD SOI MOSFETs. In comparison, partially depleted SOI devices [4-5] are built on a thicker silicon layer and are simpler to manufacture. Most design features for developing PD devices can be imported from the bulk silicon devices and used in the SOI environment with only modest changes. This makes circuit redesign for the PD devices simpler than for the FD microcircuits. Generally, CMOS device design has been optimized for digital applications even

2

for aggressively scaled channel length devices. However the same rules may produce a poor analog performance due to short channel effects (SCE) [6]. Thus it becomes necessary to optimize the existing CMOS logic technologies, so that they are compatible with the conventional CMOS process, and at the same time lead to improved performance in mixed-mode systems. During the past decade, excellent high-speed and performance have been achieved through improved design, use of high quality material and shrinking device dimensions [7-8]. However, with the reduction of channel length, control of short-channel effects is one of the biggest challenges in further down-scaling of the technology. The predominating short-channel effects are a lack of pinch-off and a shift in threshold voltage with decreasing channel length as well as drain induced barrier lowering (DIBL) and hot-carrier effect at increasing drain voltage. In contrast to the bulk device, front gate of the SOI device has better control over its active device region in the thin-film and hence charge sharing effects from source/drain regions are reduced. However, the thin-film thickness has to reduce to the order of 10nm to significantly improve the device performance, which becomes prohibitively difficult to manufacture and causes large device external resistance due to shallow source/drain extension (SDE) depths. MOSFET device design has been engineered by different approaches for the alleviation of these disadvantages. Different approaches like source/drain engineering, channel engineering and gate work function engineering have been implemented for the alleviation of these disadvantages. Gate engineering and channel engineering are the two aspects which are going to be the topic of this dissertation. Long et al [9-10] recently demonstrated that the application of dual-material gate (DMG) in bulk MOSFET and HFET leads to a simultaneous transconductance

3

enhancement and suppression of short-channel effects due to the introduction of a step function in the channel potential. In a DMG-MOSFET, the work function of metal gate 1 (M1) is greater than metal gate 2 (M2) i.e., φM1 > φM2 for an n-channel MOSFET and vice-versa for a p-channel MOSFET. For an n-channel DMG-MOSFET, VT1 > VT2, which has the inherent advantage of improving the gate transport efficiency by modifying the electric field pattern and the surface potential profile along the channel. The step potential profile, due to different work functions of two metal gates, ensures reduction in the shortchannel effects and screening of the channel region under M1 from drain potential variations. Beyond saturation, M2 absorbs any additional drain-source (D/S) voltage and hence the M1 region is screened from the drain potential variations. This work is therefore used to study for the first time the potential benefits offered by the DMG gate in suppressing the short-channel effects in PD SOI MOSFETs using two-dimensional modeling and numerical simulation. The model provides an efficient tool for further design and characterization of the novel DMG-SOI MOSFET. Double Gate (DG) MOSFETs using lightly doped ultra thin layers seem to be a very promising option for ultimate scaling of CMOS technology [11]. Excellent shortchannel effect immunity, high transconductance and ideal subthreshold factor have been reported by many theoretical and experimental studies on this device. To incorporate the advantages of both DG and DMG structures, we proposed a new structure, Dual-Material Double-Gate (DMDG) SOI MOSFET that is similar to that of an asymmetrical DG SOI MOSFET with the exception that the front gate of the DMDG structure consists of two materials (p+ poly and n+ poly). Subsequently, we present using two-dimensional simulation and with the analytical model, the reduced short channel effects exhibited by

4

DMDG

structure

below

100nm,

while

simultaneously

achieving

a

higher

transconductance and reduced drain conductance compared to the DG SOI MOSFET. The proposed structure exhibits the desired features of both DMG and DG structures. Another widely used approach to alleviate the short channel performance is through channel engineering. Asymmetric single halo MOSFET structures have been introduced for bulk as well as for SOI MOSFETs to adjust the threshold voltage and improve the device SCE. Simulation studies have been done on channel engineering concept when applied to a DG structure. 1.2 Nature of the Problem The present work involves three distinct aspects, viz. (a) Two-dimensional modeling of surface potential and threshold voltage of a PD SOI MOSFET with DMG, (b) Investigation of the novel features of the proposed DMDG SOI MOSFET along with a complete analytical model and (c) Numerical simulation studies using MEDICI [12] to investigate the novel features offered by the DG single halo (DG-SH) doped SOI MOSFET. 1.3 Recent research relevant to the problem The concept of a Dual Material Gate is similar to that of a Split-Gate Field Effect Transistor (SG FET) proposed by Shur [13]. However, SG FET suffers from the fringing capacitance between the metal gates which increases as the separation between the metal gates reduce. In 1999, Long et. al. [9] proposed a new gate structure called the dual material gate (DMG)-MOSFET. Gate material engineering with different workfunctions introduces a field discontinuity along the channel, resulting in simultaneous transport enhancement and suppressed SCEs. Zhou [14] suggested a way in which the Hetero5

Material Gate (HMG) MOSFET can be fabricated by inserting one additional mask in the bulk CMOS processing technology and demonstrated the novel characteristics of this new type of MOSFET by simulation studies. However, with PD SOI rapidly emerging as the technology for next-generation VLSI, the effect of DMG in submicron MOS technology remains to be investigated. In this work, we have developed an analytical model for surface potential and threshold voltage to aid in understanding the potential benefits of DMG structure in suppressing short channel effects in a PD SOI MOSFET. The model results are verified by numerical simulations. Double gate (DG) MOSFETs can be symmetrical or asymmetrical. Symmetrical DG MOSFETs employ the same type of gate material for both the gates (either p+ poly or n+ poly) while asymmetrical DG MOSFETs employ both, p+ poly for the front gate and n+ poly for the back gate. It would seem asymmetrical gates would undermine the current drive because the resulting device has only one predominant channel. However, it has been shown in [15] that gate–gate coupling in the asymmetrical DG MOSFET is more beneficial than in the symmetrical counterpart, resulting in superior performance of the former device for more reasons than just the threshold-voltage control. For the first time, we investigated the features exhibited by an asymmetrical DG MOSFET when dual material gate concept is applied. This has been complemented by an analytical model, which includes surface potential modeling, threshold voltage modeling and the drain current modeling. As pointed out previously, short channel performance can also be improved with the help of channel engineering, extensive studies have been done on the local high doping concentration in the channel near source/drain junctions via lateral channel

6

engineering, e.g., halo [16] or pocket implants [17]. Single halo MOSFET structures have been introduced for bulk [18] as well as for SOI MOSFETs [19] to adjust the threshold voltage and improve the device SCE. Halo implantation devices show excellent output characteristics with low DIBL, no kink, higher drive currents, flatter saturation characteristics, and slightly higher breakdown voltages compared to the conventional MOSFET. However, no such attempt has been reported on DG MOSFET. For the first time we have investigated the performance of DG structure with halo implantation using 2-D numerical simulations. 1.4 Research Problem Statement The work accomplished in this dissertation has been carried out in terms of the following intermediate stages: i) Physics based 2-D analytical model for the surface potential distribution and threshold voltage of a partially depleted DMG SOI MOSFET is developed and verified against numerical simulation results. ii) A novel design, the Dual Material Double Gate (DMDG) MOSFET is proposed along with an analytical model for surface potential, threshold voltage and drain characteristics. The model is verified by numerical simulation results. iii) Two-dimensional numerical simulation studies are used to investigate and compare the benefits of the DG single halo (DG-SH) doped structure over a conventional asymmetrical DG SOI MOSFET. 1.5 Thesis Organization The dissertation is divided into five chapters and its outline is described as given

7

below: Chapter I: Introduction. Some fundamental concepts related to SOI devices, emerging ideas: advantages & disadvantages, objectives of the project and outline of the thesis. Chapter II: Analytical modeling of surface potential and threshold voltage in a partially depleted (PD) DMG-SOI MOSFET. A physics based 2-D model for the surface potential variation along the channel in the Dual Material Gate Partially Depleted (DMG-PD) SOI MOSFET is developed. In addition, threshold voltage model of the DMG-PD MOSFET is also developed and is used to illustrate the role of DMG structure in suppressing short-channel effects. Chapter III: A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET − Two-dimensional analytical modeling and simulation. A New Dual Material Double Gate (DMDG) MOSFET is proposed along with the 2D model for the surface potential. An analytical model for the threshold voltage and drain characteristics is also proposed. The performance of the DMDG structure is compared with the conventional DG structure. The improvement in short channel behavior is clearly seen because of the introduction of the DMG concept. Chapter IV: Two-dimensional simulation studies of the novel features offered by the single halo doped asymmetrical DG MOSFET. This chapter presents the novel features offered by the asymmetrical double gate single halo (DG-SH) doped structure to enhance the MOSFET performance through 2-D numerical simulation studies. Chapter V: Conclusions.

8

CHAPTER II

ANALYTICAL MODELING OF SURFACE POTENTIAL AND THRESHOLD VOLTAGE IN A PARTIALLY DEPLETED (PD) DMG-SOI MOSFET

2.1

Introduction At very short gate lengths, the CMOS device operation is asymmetrical even at a

very small drain bias due to the higher drain side electric field resulting in short-channel effects like DIBL. Unconventional asymmetrical structures have been employed to

reduce the drain side electric field and its consequent impact upon the channel. DualMaterial Gate structure employs “gate-material engineering” instead of “doping engineering” with different workfunctions to introduce a potential step in the channel [9]. This leads to a suppression of short-channel effects and an enhanced source side electric field resulting in increased carrier transport efficiency in the channel region. And with its unique structure, DMG offers flexibility in choosing thin-film thickness, channel doping, buried oxide thickness and permittivity in short channel SOI MOSFET design. Furthermore, the DMG structure may also be employed in symmetric structures, i.e., adding a layer of material with different workfunction to both sides of the gate (like a LDD spacer). Till now, two general approaches have been used to model the surface potential profile, the electric field pattern and their impact on the threshold voltage. One of these approaches is the two-dimensional (2-D) numerical simulation [20]. The other approach is to develop an analytical solution, using either the charge sharing approach [21–22] or solving the Poisson’s equation in the depletion region [23-25]. One-dimensional analysis, based on gradual-channel approximation fails to characterize adequately the devices with

9

short channels and is suitable only for a long channel transistor where the “edge” effects along the sides of the channel can be neglected. In such an analysis, it is assumed that electric field lines are perpendicular or have a component along the y-direction only. If the channel is short (i.e., L is not much larger than the sum of the source and drain depletion widths), a significant part of the electric field will have components along both the y and x directions, the latter being the direction along the channel’s length. Thus a two-dimensional analysis is needed. So far, no analytical model has been reported for explaining the impact of partially depleted Dual Material Gate (DMG) SOI MOSFET structure over parameters such as carrier transport efficiency, hot electron injection and drain induced barrier lowering (DIBL). A 2-D analytical model is presented in this chapter, which enables a fast-physics based analysis of the partially depleted Dual Material Gate (DMG) silicon-on-insulator MOSFET. The expressions for the surface potential and electric field under the two metal gates are derived. The model results are verified by comparing them to simulated results obtained from the 2-D device simulator MEDICI. The characteristics of the DMG-PD SOI MOSFETs are examined and compared with those of corresponding single material gate partially depleted (SMG-PD) SOI MOSFETs. The model is simple in its functional form and lends itself to efficient computation. 2.2 DMG-SOI structure and its parameters A schematic structure of a partially depleted (PD) DMG SOI MOSFET implemented using the 2-D device simulator MEDICI [12] is shown in Fig. 2.1 with gate metals M1 and M2 of lengths L1 and L2, respectively. The source/drain (S/D) regions are rectangular and uniformly doped at 5×1019cm-3. The channel doping concentration NA is

10

Gate Source L1 M1 L2 M2 wd tox Drain

n+

tsi Buried oxide

n+

tb

x y

p substrate

Substrate

Fig. 2.1: Cross-sectional view of an n-channel partially depleted DMG SOI MOSFET. uniform at 1×1018cm-3. Typical values of the front-gate oxide thickness, the buried-oxide thickness and the body-film thickness are 2nm, 450nm and 100nm respectively. In the simulated structure, the S/D junction depth is 100nm. 2.3 Model Formulation

**2.3.1 Two-Dimensional Potential Analysis
**

Assuming that the impurity density in the channel region is uniform and neglecting the influence of charge carriers on the electrostatics of the channel, the potential distribution in the silicon thin-film, before the onset of strong inversion can be written as

11

∂ 2φ ( x , y ) ∂ 2φ ( x , y ) qN A + = ε si ∂x 2 ∂y 2

for

0 ≤ x ≤ L, 0 ≤ y ≤ wd

(2.1)

where NA is the body doping concentration , εsi is the silicon dielectric constant, L is the device channel length, wd is the channel depletion width and is given by

wd =

2ε si (2φ F + φ B ) qN A

(2.2)

where φB is the body electrostatic potential and φF = VT ln(NA/ni) is the Fermi potential where VT is the thermal voltage and ni is the intrinsic carrier concentration. The potential profile in the vertical direction is assumed to be a third order polynomial [26] i.e.,

φ ( x, y ) = φ s ( x ) + a1 ( x ) y + a2 ( x ) y 2 + a3 ( x ) y 3

(2.3)

where φs(x) is the surface potential and a1, a2 and a3 are arbitrary constants which are functions of x only. In the DMG structure, we have two different materials with different work functions φM1 and φM2. Therefore the flat-band voltages of the two gates would be different and they are given as

VFB1 = φ MS 1 = φ M 1 − φ Si

and

VFB 2 = φ MS 2 = φ M 2 − φ Si

(2.4)

where φsi is the semiconductor work function which is given by

φ Si = χ Si +

Eg 2q

+ φF

(2.5)

where Eg is the silicon bandgap and χsi is the electron affinity. Since we have two regions in the DMG structure, the potential under the metal gates M1 and M2 can be written as

φ1 ( x, y ) = φs1 ( x) + a11 ( x) y + a12 ( x) y 2 + a13 ( x) y 3 for

0 ≤ x ≤ L1 , 0 ≤ y ≤ wd

(2.6) (2.7)

**φ 2 ( x, y ) = φ s 2 ( x ) + a21 ( x ) y + a22 ( x ) y 2 + a23 ( x ) y 3 for L1 ≤ x ≤ L1 + L2 , 0 ≤ y ≤ wd
**

12

The Poisson’s equation is solved separately under the two gate regions using the following boundary conditions: 1. Surface potential at the interface of the two dissimilar metals is continuous

φ1 ( L1 ,0) = φ 2 ( L1 ,0) =φL1

where φL1 is the surface potential at x=L1. 2. Potential at the depletion edge is given by

(2.8)

φ1 ( x, wd ) = φ2 ( x, wd ) = φ B

where φB is the body electrostatic potential. 3. Electric flux at the interface of the two dissimilar metals at y = 0 is continuous

(2.9)

∂φ1 ( x, y ) ∂x

x = L1

=

∂φ2 ( x, y ) ∂x

x = L1

(2.10)

4. Electric flux at the interface of the gate/oxide is continuous for both the metal gates

∂φ1 ( x, y ) ∂y

∂φ2 ( x, y ) ∂y

y =0

=

' ε ox φs1 ( x) − VGS 1 ε si tox

(2.11)

y =0

' ε ox φs 2 ( x) − VGS 2 = ε si tox

(2.12)

**where εox is the dielectric constant of the oxide, tox is the gate oxide thickness and
**

' VGS 1 = VGS − V FB1

and

' VGS 2 = VGS − VFB 2

(2.13)

where VGS is the gate-to-source bias voltage, VFB1 and VFB2 are the front-channel flat-band voltages of metal 1 and metal 2, respectively. 5. Electric field at the depletion edge is zero, i.e.,

∂φ1 ( x, y ) ∂φ2 ( x, y ) = =0 ∂y ∂y

at y = wd

(2.14)

13

6. Potential at the source end is

φ1 (0,0) = φ s1 (0) = Vbi

where Vbi is the built in potential given by

(2.15)

**N N Vbi = VT ln A 2 D n i
**

where ND is the source/drain doping concentration. 7. Potential at the drain end is

(2.16)

φ 2 ( L,0) = φ s 2 ( L ) = V bi + V DS

where L=L1+L2 and VDS is the applied drain-source bias.

(2.17)

The expression for the constants a11 ( x) , a12 ( x) , a13 ( x) , a21 ( x) , a22 ( x) and a23 ( x) can be found from the boundary conditions (2.8) − (2.17) as described below. From (2.6), (2.11) and (2.14) we can obtain the following relations for the region under metal 1:

2 3 φs1 ( x) + a11 ( x) wd + a12 ( x) wd + a13 ( x) wd = φ B

(2.18)

**' ε ox φs1 ( x) − VGS1 a11 ( x) = tox ε si
**

2 a11 ( x ) + 2a12 ( x ) wd + 3a13 ( x ) wd = 0

(2.19)

(2.20)

**Similarly for the region under metal 2, we obtain the following expressions using (2.7), (2.12), and (2.14):
**

2 3 φs 2 ( x) + a21 ( x) wd + a22 ( x) wd + a23 ( x) wd = φ B

(2.21)

14

**' ε ox φs 2 ( x) − VGS 2 a21 ( x) = ε si tox
**

2 a21 ( x ) + 2a22 ( x ) wd + 3a23 ( x ) wd = 0

(2.22)

(2.23)

**Region under metal 1 Solving (2.18) - (2.20) for a12 ( x) and a13 ( x) we get
**

' 2ε ox φ s1 ( x) − VGS 1 3 a12 ( x) = − − 2 (φ s1 ( x) − φ B ) ε si wd tox wd

(2.24)

a13 ( x) =

2 ε ' φ ( x) − VGS1 ) + ox 2 (φ s1 ( x) − VG' S1 ) 3 ( s1 wd ε si wd

(2.25)

Thus substituting the values of a11 ( x ) , a12 ( x ) and a13 ( x ) in (2.6) and using φ1 ( x, y ) in (2.1) we obtain the potential distribution as

∂ 2φs1 ( x) α + βφs1 ( x) = γ 1 ∂x 2

where

(2.26)

2ε ox y 2 ε ox y 3 3 y 2 2 y 3 ε ox y α =1− 2 + 3 + − + 2 ε si t ox ε si t ox wd ε si t ox wd wd wd

β=

6ε ox y 4ε ox 12 y 6 − 2+ − 3 2 wd wd ε si t ox wd ε si t ox wd

qN A 6ε ox y 12 y 4ε ox ' 6 − + 3 − 2 φ B + VGS 1 2 wd ε si t ox wd ε si t ox wd wd

γ1 =

ε si

The above equation is a simple second order non-homogenous differential equation with constant coefficients which has a solution of the form

φ s1 ( x ) = A1 exp(ηx ) + B1 exp( −ηx ) +

γ1 β

for

0 ≤ x ≤ L1

(2.27)

where A1, B1 are constants and η = − β / α . Now using the boundary condition (2.15),

15

**we obtain A1 + B1 + Region under metal 2 Solving (2.21) - (2.23) for a22 ( x) and a23 ( x) , we get a22 ( x) = −
**

' 2ε ox φs 2 ( x) − VGS 2 3 − 2 (φ s 2 ( x ) − φ B ) ε si wd tox wd

γ1 = Vbi β

(2.28)

(2.29)

a23 ( x) =

ε 2 ' φ ( x) − VGS 2 ) + ox 2 (φs 2 ( x) − VG' S 2 ) 3 ( s2 wd ε si wd

(2.30)

Thus substituting the values of a21 ( x ) , a22 ( x ) and a23 ( x ) in (2.7) and using φ2 ( x, y ) in (2.1), we obtain the expression of the form

∂ 2φs 2 ( x ) α + βφs 2 ( x ) = γ 2 ∂x 2

where α and β are same as previously defined and γ 2 is

(2.31)

γ2 =

qN A

ε si

12 y 6 6ε ox y 4ε ox + 3 − 2 φ B + − 2 wd wd ε si t ox wd ε si t ox wd

' VGS 2

The above equation is a simple second order non-homogenous differential equation with constant coefficients which has a solution of the form

φ s 2 ( x) = A2 exp(ηx) + B2 exp( −ηx ) +

γ2 β

for

L1 ≤ x ≤ L

(2.32)

where A2, B2 are constants and η = − β / α . Now using the boundary condition (2.16), we obtain A2 exp(η L) + B2 exp(−η L) +

γ2 = Vbi + VDS β

(2.33)

16

Using boundary conditions (2.8) and (2.10), we get the following expressions A1 exp(η L1 ) + B1 exp(−η L1 ) +

γ1 γ = A2 exp(η L1 ) + B2 exp(−η L1 ) + 2 = φ L1 β β

(2.34) (2.35)

A1η exp(η L1 ) − B1η exp(−η L1 ) = A2η exp(η L1 ) − B2η exp(−η L1 ) Solving (2.28), (2.33) and (2.34) for A1, B1, A2 and B2, we obtain

A1 =

− (Vbi − σ 1 ) + (φ L1 − σ 1 )exp(ηL1 ) exp( 2ηL1 ) − 1

B1 =

**(Vbi − σ 1 )exp(2ηL1 ) − (φL1 − σ 1 )exp(ηL1 )
**

exp(2ηL1 ) − 1

A2 =

**(Vbi + VDS − σ 2 )exp(ηL) − (φL1 − σ 2 )exp(ηL1 )
**

exp(2ηL) − exp(2ηL1 )

− (Vbi + VDS − σ 2 )exp[η ( L + 2 L1 ) + (φ L1 − σ 2 )exp[η ( 2 L + L1 )] exp( 2ηL ) − exp( 2ηL1 )

B2 =

where σ1=γ1/β and σ2=γ2/β . Since the electrostatic potential and the electric field are continuous at the interface of the region below the two gates as indicated by the boundary condition 1 in (2.8), the value of φL1 can be obtained using (2.35) as:

2(Vbi + VDS − σ 2 ) exp[η ( L + L1 )] + σ 2 exp(2ηL1 ) + σ 2 exp(2ηL) 2(Vbi − σ 1 ) exp(ηL1 ) + σ 1 exp(2ηL1 ) + σ 1 + exp(2ηL) − exp(2ηL1 ) exp(2ηL1 ) − 1 φ L1 = exp(2ηL1 ) + 1 exp(2ηL1 ) + exp(2ηL) + (2.36) exp(2ηL1 ) − 1 exp(2ηL) − exp(2ηL1 )

The concept of drain induced barrier lowering (DIBL) can be illustrated by the channel surface potential. Since the sub-threshold leakage current often occurs at the position of minimum surface potential, the influence of DIBL on the sub-threshold behavior of the device can be monitored by the minimum surface potential. DIBL can be demonstrated by plotting the surface potential minima as a function of the position along the channel for different drain bias conditions. Due to the co-existence of the two

17

dissimilar gate metals, M1 and M2, having a finite workfunction difference, the position of minimum surface potential, xmin, will be solely determined by the gate metal with higher work function. For the NMOSFET (present case), the work function of M1 is greater than that of M2 and for the PMOSFET, it is vice-versa. The minimum potential of the front-channel can be calculated from (2.27) by solving ∂φS 1 ( x ) ∂x x = x =0

min

The minima of the surface potential φs1,min occurs at

xmin =

1 B1 ln 2η A1

(2.37)

The minimum surface potential can be obtained by substituting for x = xmin in (2.27) which is given as

φs1, min = A1 exp(ηxmin ) + B1 exp(−ηxmin ) +

γ1 β

(2.38)

An expression for the electric field can be obtained by differentiating the surface potential expressions (2.27) and (2.33) and is given by

E1 ( x ) = E2 ( x ) =

∂φ1 ( x, y ) ∂x ∂φ2 ( x, y ) ∂x

y =0

= A1η exp(η x) − B1η exp(−η x ) = A2η exp(η x ) − B2η exp(−η x)

0 ≤ x ≤ L1 L1 ≤ x ≤ L

(2.39)

y =0

(2.40)

The above two equations are quite useful in determining how the drain side electric field is modified by the DMG structure.

18

2.3.2

Threshold Voltage Model The threshold voltage Vth is that value of the gate voltage VGS at which a

conducting channel is induced at the surface of the SOI MOSFET. Therefore, the threshold voltage is taken to be that value of gate source voltage for which φS ,min = 2φF , where φF is the difference between the extrinsic Fermi level in the bulk region and the intrinsic Fermi level. Hence we can determine the value of threshold voltage as the value of VGS by solving the expression for φs1,min as shown below. Rewriting (2.38) here for convenience, we have

**φs1, min = A1 exp(ηxmin ) + B1 exp(−ηxmin ) +
**

By reorganizing, A1 and B1 can be written as A1 = K1 + K 2γ 1 where and

γ1 β

B1 = K 3 + K 4γ 1

(2.41)

** −V + φ L1 exp(η L1 ) K1 = bi exp(2η L1 ) − 1 K2 = 1 1 − exp(η L1 ) β exp(2η L1 ) − 1
**

Vbi exp(2η L1 ) − φ L1 exp(η L1 ) exp(2η L1 ) − 1

K3 =

K4 =

− exp( 2ηL1 ) + exp(ηL1 ) β [exp( 2ηL1 ) − 1]

Substituting for A1 and B1 in (2.38) and equating it to 2φ F , we obtain

** 2φ − K exp(η x ) − K exp(−η x ) qN ε t w 1 min 3 min − A si ox d Vth = VFB1 − F ε si 4ε ox 1 + K exp(η x ) + K exp(−η x ) 2 min 4 min β
**

19

(2.42)

The dependence of the surface potential on the work functions and the length of the metal gates mean that we can tune the surface potential and the threshold voltage of the transistor. This mechanism has also been observed for the bulk MOSFETs [14] when the dual material gate concept is applied. The threshold voltage model derived does not take into account the presence of mobile carriers in the channel. Hence the model cannot clearly demarcate the transition between the weak and the strong inversion. However, such an analysis will lead to a complex solution requiring the use of fitting parameters. 2.4 Results and Discussion To verify the proposed analytical model, the 2-D device simulator MEDICI was used to simulate the different aspects, viz. surface potential, electric field, threshold voltage etc. and compare with the results predicted by the analytical model. 2.4.1 Surface Potential and Electric Field Fig. 2.2 shows the calculated and the simulated values of the surface potential for different drain voltages along the channel for a channel length L = 0.15µm. It is clearly seen that because of the step function profile of the surface potential, there is no significant increase of the potential under gate M1 as the drain voltage is increased, which means that gate M1 is effectively screened from the drain potential variations. In other words, the drain voltage has very little influence on the drain current after saturation, thus reducing the drain conductance. It follows from the figure that the minimum surface potential point is independent of the applied drain bias. Because of this feature, DIBL is reduced considerably in the DMG structure. The predicted values of the model agree well with the simulation results.

20

3.0 Surface Potential (in volts) 2.5 2.0 1.5 1.0 0.5

VGS = 0.15V NA = 1×1018cm-3 L1= 0.05µm L2 = 0.1µm φM1 = 4.63V φM2 = 4.17V tsi = 100nm tox= 2nm

MEDICI MODEL

V DS = 1.75V

V = 0.95V

DS

V DS = 0.25V

0.00

0.05 0.10 0.15 Position in channel (in µm)

0.20

Fig. 2.2: Surface potential profiles of a partially depleted SOI MOSFET obtained from the analytical model and MEDICI simulation for different drain biases with a channel length L = 0.15µm(L1 = 0.05µm and L2 = 0.1µm). Fig. 2.3 shows the calculated and simulated values of electric field along the channel length at the drain end for the DMG-PD SOI MOSFET and the simulated values for the SMG-PD SOI MOSFET for the same channel length. It is clearly seen that there is a considerable reduction in the peak electric field at the drain end in the case of the DMG structure when compared with the SMG. This reduction in the electric field reduces the hot carrier effect, which is another important short channel effect. The agreement between the model and the simulated results proves the accuracy of the model.

21

600 Electric Field (in kV/cm) 550 500 450 400 350 300 250

DMG-SOI φM1 = 4.63V φM2 = 4.17V L1 = 0.05µm L2 = 0.1µm

SMG-SOI φM = 4.63V L = 0.15µm

**200 0.120 0.125 0.130 0.135 0.140 0.145 0.150 Position in channel (in µm)
**

Fig. 2.3: Electric field along the channel towards the drain end obtained from the analytical model and MEDICI simulation in DMG-SOI and SMG-SOI MOSFETs with a channel length L = 0.15µm and a drain bias VDS = 1.75V. 2.4.2 Minimum Surface Potential and Threshold Voltage Minimum surface potential as a function of channel length L (=L1+L2) for the partially depleted DMG-SOI with film thickness tSi = 100 nm is shown Fig. 2.4. As previously stated, Fig. 2.4 points out that the minimum channel potential is almost constant for different channel lengths i.e., the shift in the minimum surface potential with channel length is almost zero. This is due to the existence of a work function difference in the case of the DMG-SOI MOSFETs. The close match between the analytical results and the 2-D simulation results verifies the validity of the model for the minimum surface potential under the gate for different combinations of L1 and L2.

DMG-(MEDICI) SMG-(MEDICI) DMG-(MODEL)

22

Minimum Surface Potential (in volts)

0.7 0.6 0.5 0.4 0.3 0.2 0.1

φM1 = 4.63V φM2 = 4.17V L1 = 0.05µm MEDICI MODEL

0.10 0.15 0.20 0.25 0.30 0.35 0.40 Channel length (in µm)

Fig. 2.4: Variation of the channel minimum potential with channel length L (=L1+L2) for partially depleted DMG-SOI MOSFETs with L1 constant at 0.05µm. In Fig. 2.5, the simulated values of the threshold voltage as a function of channel length are compared with those of the model values. It is seen that the threshold voltage rolls-up with decreasing channel lengths for a fixed L1. This happens due to the increased L1/L2 ratio at decreasing channel lengths since the portion of the larger work function gate is increased as the channel length reduces. This unique feature of the DMG structure is an added advantage when the device dimensions are continuously shrinking. From the results it is clearly seen that the calculated values of the analytical model tracks the simulated values very well.

23

**0.7 Threshold Voltage (in volts) 0.6 0.5 0.4 0.3 0.2 0.1
**

φM1 = 4.63V φM2 = 4.17V L1 = 0.05µm

MEDICI MODEL

0.10 0.15 0.20 0.25 0.30 0.35 0.40 Channel length (in µm)

Fig. 2.5: Threshold voltage variation with channel length for DMG SOI device compared between MEDICI simulations and model prediction with L1 fixed at 50nm. 2.4.3 Substrate Bias dependence

Fig. 2.6 shows the threshold voltage variation against different channel lengths at a fixed back gate bias φB. In the case of the DMG-SOI MOSFET, the threshold voltage variation is quite less when compared with the SMG-SOI MOSFET. This figure clearly depicts that the threshold voltage of the DMG SOI structure is much less dependent on the substrate bias than the SMG SOI structure as the threshold voltage roll-up mechanism with reducing channel lengths can be observed in the former.

24

**0.9 Threshold voltage (in volts) 0.8 0.7 0.6 0.5
**

φ B = -1V 0.4 L = 0.05µm 1 0.3 φM1 = 4.63V φM2 = 4.17V

DMG-PD(MEDICI) DMG-PD(MODEL) SMG

0.2

0.10 0.15 0.20 0.25 0.30 0.35 0.40 Channel length (in µm)

Fig. 2.6: Threshold voltage variation versus channel length at a fixed back gate bias of φB = 1V with L1 constant at 0.05µm. In Fig. 2.7(a) and Fig. 2.7(b), the threshold voltage for both the DMG and the SMG is shown for different substrate biases for two different channel lengths. In Fig. 2.7(a) when the channel length L = 0.2µm, the threshold voltage variation in the DMG is smaller than that of the SMG. However, in Fig. 2.7(b), when the channel length is reduced to L = 0.1µm, the variation of the threshold voltage between the two is same. The threshold voltage saturates as the negative substrate bias is increased for both the DMG and the SMG. This condition is achieved for the low back gate bias when the channel length is reduced. The threshold voltage saturates because of the hole accumulation at the bottom of the silicon film. For the SMG-SOI MOSFET, the shift in the position of the minimum surface potential towards the source increases with increasing values of φB and, therefore, the DIBL increases. However, for the DMG structure, the shift in the position

25

of the minimum surface potential is almost zero and hence DIBL increase is far less in the DMG structure.

0.9 0.8 0.7 0.6 0.5 L = 0.05µm 0.4 1 L = 0.15µm DMG-PD(MEDICI) 0.3 2 φM1 = 4.63V DMG-PD(MODEL) 0.2 φ = 4.17V SMG-PD M2 0.1 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 Substrate bias (in volts)

Fig. 2.7(a): Threshold voltage variation versus back gate bias φB with a channel length L=0.2µm (L1=0.05µm, L2=0.15µm).

Threshold Voltage (in volts)

Threshold voltage (in volts)

0.8 0.7 0.6 0.5 0.4 0.3 0.2

L1 = 0.05µm L2 = 0.05µm φM1 = 4.63V φM2 = 4.17V DMG-PD(MEDICI) DMG-PD(MODEL) SMG-PD(MEDICI)

0.1 0.0

-0.5

-1.0 -1.5 -2.0 -2.5 Substrate Bias (in volts)

-3.0

Fig. 2.7(b): Threshold voltage variation versus back gate bias φB with a channel length L=0.2µm (L1 = 0.05µm, L2 = 0.05µm).

26

2.4.4

Gate Material Engineering The dual-material gate (DMG) structure offers the benefit of SCE suppression in a

SOI device by virtue of gate material engineering, i.e., engineering the length and workfunction of the two gate metals. Fig. 2.8 shows the variation of the threshold voltage with workfunction difference at a fixed channel length of L = 0.25 µm for two L1/L2 ratios as predicted by the analytical expression and the 2-D numerical simulations. As shown in the figure, the threshold voltage increases with the increasing workfunction difference. For a fixed workfunction difference, the threshold voltage is higher for a higher L1/L2 ratio due to the increased proportion of the channel region controlled by a higher wokfunction gate.

Threshold Voltage (in volts)

1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.2 0.3

MEDICI MODEL L1/L2 = 0.5 VDS = 50mV L = 0.15µm L1/L2 = 1

0.4 0.5 0.6 0.7 φM1- φM2(in volts)

0.8

Fig. 2.8: Threshold voltage variation with gate work function difference with φM2 fixed at 4.17eV for the DMG-SOI MOSFET with channel length L (=L1+L2) of 0.25µm.

27

2.3

Summary The effectiveness of the Dual-Material-Gate concept to the partially depleted

structure has been examined for the first time by developing a 2-D analytical model. The results obtained have been compared with the MEDICI simulations. The model results agree well with the simulated results. It is also emphasized that the DMG structure in the partially depleted SOI MOSFETs leads to a reduced short channel effect as the surface potential profile shows a step at the interface of the two metals which the reduces drain conductance and the DIBL. Also, the peak electric field at the drain end is reduced minimizing the hot carrier effect. The threshold voltage shows a roll-up with the reducing channel lengths. Thus the short channel behavior of the PD SOI MOSFETs is further enhanced with the introduction of the DMG structure over their single gate counterparts. Moreover, the immunity against the SCE is possible by a new way of “gate material engineering” which lends a tremendous flexibility in deep submicron SOI design.

28

CHAPTER III

A NEW DUAL MATERIAL DOUBLE GATE NANOSCALE SOI MOSFET − TWO DIMENSIONAL ANALYTICAL MODELING AND SIMULATION

3.1

Introduction Double Gate (DG) MOS devices using lightly doped ultra thin silicon layers are

very promising for ultimate scaling of the CMOS technology because they exhibit the best performance in terms of the short channel effects, the subthreshold slope, the current drivability and the transconductance [27]. One of the problems affecting the DG MOSFETs is the control of the threshold voltage that is hardly dependent on the doping concentration and on the other hand, is strongly affected by the thickness of the silicon layer. In particular, the when technological characteristics compatible with a 50nm gate length are assumed, Vth is negative if two n+ poly gates are adopted, while it becomes too large (approximately 1V) in the case of the p+ poly gates. Acceptable values for Vth (0.2 – 0.4V for VDD = 1.0 – 1.5V) are obtained when asymmetrical gate structure with one n+ poly and one p+ poly is realized [15]. Furthermore, device simulations demonstrate that the asymmetric structure provides almost the same drain ON current as the symmetric one [15]. For these reasons, it might be concluded that the asymmetric DG structure is preferable because symmetric devices would require alternative gate materials with a workfunction tailored in order to provide an acceptable Vth leading to more expensive fabrication process. However, the DG MOSFETs also suffer from considerable short channel behavior in the sub 100nm regime. As demonstrated in the previous chapter, to enhance the immunity against the short channel effects, the dual material gate (DMG) structure was

29

proposed. As the name suggests, the gate is composed of two materials in this structure with different workfunctions. Such a configuration introduces a step in the surface potential profile, along with an increase in the transconductance while suppressing the short channel effects. However, the drive capability of this structure is not as good as that of the DG SOI MOSFET. To incorporate the advantages of both the DG and the DMG SOI MOSFETs we propose a new structure called the dual material double gate (DMDG) SOI MOSFET. The proposed structure is similar to that of an asymmetrical DG SOI MOSFET with the exception that the front gate of the DMDG structure consists of two materials (p+ poly and n+ poly). We present here, using two-dimensional simulation, the reduced short channel effects exhibited by the DMDG structure below 100nm, while simultaneously achieving a higher transconductance and reduced drain conductance compared to the DG SOI MOSFET. The proposed structure exhibits the desired features of both the DMG and the DG structures. With this structure, we demonstrate a considerable reduction in the peak electric field near the drain end, increased drain breakdown voltage and transconductance, reduced drain conductance and threshold voltage “roll-up” even for channel lengths far below 100 nm. An analytical model using Poisson’s equation also has been presented for the surface potential leading to the threshold voltage model for the DMDG SOI MOSFET. A complete drain current model [28] considering the impact ionization [29], the velocity overshoot, the channel length modulation and the DIBL [30] is also presented. The accuracy of the model is verified by comparing the model results with the simulation results using a 2-D device simulator, MEDICI.

30

3.2

DMDG SOI structure and its parameters

Schematic cross-sectional views of both the asymmetrical DG and the DMDG SOI MOSFET implemented using the 2-D device simulator MEDICI are shown in Fig. 3.1. The front gate consists of dual materials M1 (p+ poly) and M2 (n+ poly) of lengths L1 and L2 respectively, while the back gate is effectively an n+ poly gate. The doping in the p type body and the n+ source/drain regions is kept at 1 x 1015cm-3 and 5 x 1019cm-3 respectively. Typical values of the front-gate oxide thickness, the back-gate-oxide thickness and the thin-film thickness are 2nm, 2nm and 12 nm respectively.

G S D tf n+ tsi tb n+ (a) G L1 S p+ L p n+ (b) Polysilicon SiO2 Metal Si Fig. 3.1: Cross-sectional view of (a) DG-SOI MOSFET (b) DMDG-SOI MOSFET L2 n+ D tf n+ tsi tb

p+ L p

n+

n+

31

3.3 3.3.1

Model Formulation Surface Potential Model Assuming that the impurity density in the channel region is uniform and the

influence of the charge carriers on the electrostatics of the channel can be neglected, the potential distribution in the silicon thin-film, before the onset of strong inversion can be expressed as

∂ 2φ ( x , y ) ∂ 2φ ( x , y ) qN A + = ε si ∂x 2 ∂y 2

for

0 ≤ x ≤ L, 0 ≤ y ≤ t si

(3.1)

where NA is the uniform film doping concentration independent of the gate length, εsi is the dielectric constant of silicon, tsi is the film thickness and L is the device channel length. The potential profile in the vertical direction, i.e., the y-dependence of φ ( x, y ) can be approximated by a simple parabolic function as proposed by [26] for the fully depleted SOI MOSFETs as

φ ( x, y ) = φs ( x) + a1 ( x) y + a2 ( x) y 2

(3.2)

where φS ( x ) is the surface potential and the arbitrary coefficients a1 ( x ) and a2 ( x ) are functions of x only. In a DG-SOI MOSFET, the front gate consists of only one material i.e, p+ poly, but in the DMDG structure, we have two different materials (p+ poly and n+ poly) with work functions φM 1 and φM 2 , respectively. Therefore, the front channel flat-band voltages of the p+ poly and n+ poly at the front gate would be different and they are given as VFB , fp = φMS 1 = φM 1 − φSi and VFB , fn = φMS 2 = φM 2 − φSi (3.3)

where φsi is the silicon work function which is given by

32

φSi = χ Si +

Eg 2q

+ φF

(3.4)

where Eg is the silicon bandgap at 300K, χsi is the electron affinity of silicon,

**φF = VT ln ( N A ni ) is the Fermi potential, VT is the thermal voltage and ni is the intrinsic
**

carrier concentration. Since we have two regions in the front gate of the DMDG structure, based on (3.2) the surface potential under p+ poly and n+ poly can be written as:

φ1 ( x, y ) = φ s1 ( x) + a11 ( x) y + a12 ( x) y 2

for 0 ≤ x ≤ L1 , 0 ≤ y ≤ tsi

(3.5) (3.6)

φ 2 ( x, y ) = φ s 2 ( x ) + a21 ( x ) y + a22 ( x) y 2 for L1 ≤ x ≤ L1 + L2 , 0 ≤ y ≤ tsi

where φs1 and φs2 are the surface potentials under p+ poly (M1) and n+ poly (M2) respectively and a11, a12, a21 and a22 are arbitrary coefficients. The Poisson’s equation is solved separately under the two top front gate materials (p+ poly and n+ poly) using the following boundary conditions: 1. Electric flux at the front gate-oxide interface is continuous for the dual material gate. Therefore, we have ∂φ1 ( x, y ) ∂y ∂φ2 ( x, y ) ∂y

' ε ox φs1 ( x) − VGS , f 1 = tf ε si ' ε ox φs 2 ( x) − VGS , f 2 = tf ε si

y =0

under M1

(3.7)

y =0

under M2

(3.8)

**where εox is the dielectric constant of the oxide, tf is the gate oxide thickness and
**

' VGS , f 1 = VGS − VFB , fp

and

' VGS , f 2 = VGS − VFB , fn

(3.9)

where VGS is the gate-to-source bias voltage, VFB,fp and VFB,fn are the front-channel flat-band voltages of p+ polysilicon and n+ polysilicon, respectively, and are given by (3.3).

33

2. Electric flux at the back gate-oxide and the back channel interface is continuous for both the materials of the front gate (p+ poly and n+ poly). ∂φ1 ( x, y ) ∂y ∂φ2 ( x, y ) ∂y

' ε ox VGS ,b − φB ( x) = tb ε si ' ε ox VGS ,b − φB ( x) tb ε si

y =tsi

under M1

(3.10)

y =tsi

=

under M2

(3.11)

**where tb is the back gate oxide thickness, φB ( x) is the potential function along the
**

' back gate oxide-silicon interface, and VGS ,b = VGS − VFB ,bn , where VFB ,bn is the back

gate flat-band voltage and is same as that of VFB,fn. 3. Surface potential at the interface of the two dissimilar gate materials of the front gate is continuous

φ1 ( L1 ,0) = φ 2 ( L1 ,0)

(3.12)

4. Electric flux at the interface of the two materials of the front gate at y = 0 is continuous ∂φ1 ( x, y ) ∂x 5. The potential at the source end is

x = L1

=

∂φ2 ( x, y ) ∂x

x = L1

(3.13)

**φ1 (0, 0) = φs1 (0) = Vbi
**

where Vbi = VT ln

(3.14)

N AND is the built-in potential across the body-source junction ni2

and NA and ND are the body and source/drain dopings respectively. 6. The potential at the drain end is

φ2 ( L1 + L2 , 0) = φs 2 ( L1 + L2 ) = Vbi + VDS

(3.15)

34

where VDS is the applied drain-source bias. The constants a11 ( x ) , a12 ( x ) , a21 ( x ) and a22 ( x ) in equations (3.5) and (3.6) can be deduced from the boundary conditions (3.7) – (3.15) as described. From (3.5), (3.7) and (3.10), we can obtain the following relations for the region under p+ poly (L1):

2 φS 1 ( x ) + a11 ( x ) tSi + a12 ( x ) tSi = φ B ( x ) ' ε ox φ S1 ( x ) − VGS , f 1 a11 ( x ) = = Cf tf ε Si ' φ S1 ( x ) − VGS , f 1 ε where C f = ox ε Si tf

(3.16)

(3.17)

a11 ( x ) + 2a12 ( x ) tSi =

' V ' −φ ( x) ε ox ε ox VGS .b − φ B ( x ) = Cb GS ,b B where Cb = tb tb tb ε Si

(3.18)

**Similarly for the region under n+ poly (L2), we obtain the following expressions using (3.6), (3.8), and (3.11):
**

2 φS 2 ( x ) + a21 ( x ) tSi + a22 ( x ) tSi = φ B ( x ) ' ε ox φS 2 ( x ) − VGS , f 2 a21 ( x ) = = Cf tf ε Si ' φ S 2 ( x ) − VGS , f 2 ε where C f = ox ε Si tf

(3.19)

(3.20)

a21 ( x ) + 2a22 ( x ) tSi = Region under p+ poly (L1)

' V ' −φ ( x) ε ox VGS ,b − φ B ( x ) ε ox = Cb GS ,b B where Cb = tb tb tb ε Si

(3.21)

**Solving (3.16)-(3.18) for a12 ( x ) , we get C C C C ' ' VGS ,b + VGS , f 1 f + f − φS 1 ( x ) 1 + f + f Cb CSi Cb CSi a12 ( x ) = C 2 tSi 1 + 2 Si Cb where CSi = ε Si tSi .
**

35

Thus substituting the values of a11 ( x ) and a12 ( x ) in (3.5) and using φ1 ( x, y ) in (3.1) we obtain the potential distribution as ∂ 2φS 1 ( x ) − αφS 1 ( x ) = β1 ∂x 2 where (3.22)

α=

2 (1 + C f Cb + C f CSi )

2 tSi (1 + 2 CSi Cb )

and

β1 =

qN A

ε Si

C C + C f CSi 1 ' ' − 2VGS , f 1 2 f b t (1 + 2 C C ) − 2VGS ,b t 2 (1 + 2 C C ) Si b Si b Si Si

The above equation is a simple second-order non-homogenous differential equation with constant coefficients which has a solution of the form

φS 1 ( x ) = A1 exp (η x ) + B1 exp ( −η x ) −

β1 α

(3.23)

where A1, B1 are constants and η = α . Now using the boundary condition (3.14), we obtain A1 + B1 − Region under n+ poly (L2) Solving (3.19)-(3.21) for a22 ( x ) , we get C C C C ' ' VGS ,b + VGS , f 2 f + f − φ S 2 ( x ) 1 + f + f Cb CSi Cb CSi a22 ( x ) = C 2 tSi 1 + 2 Si Cb Thus substituting the values of a21 ( x ) and a22 ( x ) in (3.6) and using φ2 ( x, y ) in (3.1), we obtain the expression of the form

β1 = Vbi α

(3.24)

36

∂ 2φS 2 ( x ) − αφS 2 ( x ) = β 2 ∂x 2 where α is same as previously defined and β 2 is

(3.25)

β2 =

qN A

ε Si

C C + C f CSi 1 ' ' − 2VGS , f 2 2 f b − 2VGS ,b 2 t (1 + 2 C C ) t (1 + 2 C C ) Si b Si b Si Si

The above equation is a simple second-order non-homogenous differential equation with constant coefficients which has a solution of the form

φS 2 ( x ) = A2 exp (η ( x − L1 ) ) + B2 exp ( −η ( x − L1 ) ) −

β2 α

(3.26)

where A2, B2 are constants and η = α . Now using boundary condition (3.15), we obtain Vbi + VDS = A2 exp (η L2 ) + B2 exp ( −η L2 ) −

β2 α

(3.27)

Using boundary conditions (3.12) and (3.13), we get the following expressions A1 exp (η L1 ) + B1 exp ( −η L1 ) + (σ 1 − σ 2 ) = A2 + B2 A1η exp (η L1 ) − B1η exp ( −η L1 ) = A2η − B2η where (3.28) (3.29)

σ 1 = − β1 α =

and

qN A

ε Si

C f Cb + C f CSi ' − VGS , f 1 1+ C C + C C f b f Si

1 ' − VGS ,b 1+ C C + C C f b f Si

(3.30)

σ 2 = − β2 α =

qN A

ε Si

C f Cb + C f CSi ' − VGS , f 2 1+ C C + C C f b f Si

1 ' − VGS .b 1+ C C + C C f b f Si

(3.31)

Solving (3.28) and (3.29), we obtain the relationship among the coefficients A1, B1, A2 and B2 as

37

A2 = A1 exp (η L1 ) +

(σ 1 − σ 2 )

2

and

B2 = B2 exp ( −η L1 ) +

(σ 1 − σ 2 )

2

Now solving for A1, B1, A2 and B2 we obtain (Vbi − σ 2 + VDS ) − exp ( −η ( L1 + L2 ) ) (Vbi − σ 1 ) − (σ 1 − σ 2 ) cosh (η L2 ) A1 = exp ( −η ( L1 + L2 ) ) 1 − exp ( −2η ( L1 + L2 ) ) (Vbi − σ 1 ) − (Vbi − σ 2 + VDS ) exp ( −η ( L1 + L2 ) ) + (σ 1 − σ 2 ) cosh (η L2 ) exp ( −η ( L1 + L2 ) ) B1 = 1 − exp ( −2η ( L1 + L2 ) ) A2 = A1 exp (η L1 ) +

(σ 1 − σ 2 )

2

and

B2 = B1 exp ( −η L1 ) +

(σ 1 − σ 2 )

2

The electric field pattern along the channel determines the electron transport velocity through the channel. The electric field component in the x–direction, under p+ poly is given as E1 ( x ) = ∂φ1 ( x, y ) ∂x =

y =0

∂φS 1 ( x ) = A1η exp (η x ) − B1η exp ( −η x ) ∂x

(3.32)

**Similarly the electric field pattern, in x–direction, under n+ poly (front gate) is given as E2 ( x ) = ∂φ2 ( x, y ) ∂x =
**

y =0

∂φS 2 ( x ) = A2η exp ( λ1 ( x − L1 ) ) − B2η exp ( −η ( x − L1 ) ) ∂x

(3.33)

The above two equations are quite useful in determining how the drain side electric field is modified by the proposed DMDG structure. 3.3.2 Threshold Voltage Model In the proposed DMDG SOI MOSFET, we have tf and tb as the front gate and back gate oxide thicknesses, and the same gate voltage, VG, is applied to both the gates. The channel doping is uniform with an acceptor concentration of 1015 cm-3 as in [28]. The

38

threshold voltage, Vth for the DMDG SOI structure is derived from the graphical approach as has been done for the DG SOI MOSFETs [28]. When the potential distribution dependence on the gate voltage is studied, it is seen that first an inversion layer is formed on the inside surface of the back gate n+ polysilicon. Then the potential distribution changes linearly while the surface potential is fixed. After this, an inversion layer on the inside surface of the p+ polysilicon is formed and then the potential distribution in the channel is invariable and the applied voltage is sustained by both gate oxides. This analysis concludes that this structure has two different threshold voltages related to the front and the back gate respectively. From [28], the expression for the front and the back gate threshold voltage of the long channel device is given as

Vth1 = VFB , fp + 2φF +

Qsi 2

4Csi 1 + VT Qsi

1 4Csi 1 + + VT ln VT Qsi 4Csi C f

**γ t f + tsi ∆VFB − γ t f + γ tb + tsi
**

(3.34)

Vth 2 = VFB , fp + 2φF +

Qsi 4Csi 1 + VT Qsi 2

1 4Csi 1 + + VT ln VT Qsi 4Csi C f

(3.35)

where Vth1 is the threshold voltage for the back gate with n+ poly and Vth2 is the threshold voltage for the front gate with p+ poly and n+ poly. VFB,fp and VFB,fn are given by (3.3),

**γ = ε si ε ox , Qsi = qN Atsi is the channel acceptor charge and ∆VFB is the difference
**

between the flatband voltages associated with the front and the back gates and is given by ∆VFB = VFB , fp − VFB ,bn (3.36)

In the above models, both the induced and the depleted charges have been considered in the channel region. However, for short channel devices, we neglect both the

39

charges in the derivation of the threshold voltage model. Low doping concentration of double-gate SOI MOSFETs makes this a good approximation [31]. This approximation leads to a Poisson equation of potential, φ, given by

∂ 2φ ( x , y ) ∂ 2φ ( x , y ) qN A + = ≈0 ε si ∂x 2 ∂y 2

(3.37)

As shown in [31], the above equation can be solved using the parabolic potential profile (3.5) and (3.6) and with the help of the boundary conditions (3.7)-(3.15). The short channel threshold voltage shift ∆Vth of DMDG SOI MOSFET can be written as ∆Vth = 2 η Sη L1 e −ζ where

' η S = Vbi − VGS , f 1 +

(3.38)

∆VFB t 2 1 + si 2γ t f

(3.39)

L1 L2 ' Vbi + VDS − VGS , f 2 sinh λ + ηS sinh λ 1 ηL1 = L1 L2 L1 2 L cosh sinh + sinh cosh 2 λ λ λ λ

(

)

(3.40)

ζ = L1

2γ tsi t f

(3.41)

Therefore, the expression for the threshold voltage of the DMDG SOI MOSFET is given by Vth = VthL − ∆Vth (3.42)

where VthL can be either Vth1 or Vth2. Equation (3.42) does not predict any threshold voltage roll-up, whereas the simulation results of the DMDG structure exhibit a threshold voltage roll-up phenomenon. To take into account this phenomenon, we introduce an

40

empirical correction factor, θ. The empirical relation used for this parameter is given by

θ = 1−

L1 − L2 ρ L1

(3.43)

Here the value of ρ, when compared with the simulated results has been obtained as

**ρ = kL1 − 2.25 , where L1 is in µm and k=185/µm. Therefore, the final expression for the
**

threshold voltage of the DMDG SOI MOSFET is given by Vth = VthL − θ∆Vth (3.44)

It is to be noted that when L1 = L2, θ is equal to unity and when the channel length is reduced keeping L1 fixed then θ decreases leading to a threshold voltage roll-up. It is assumed here that the length of M1 is always greater than that of M2, which is reasonable for sub 100 nm channel lengths. Using the threshold model given by (3.44), the DIBL of the DMDG structure can now be expressed as DIBL = Vth (VDS = 0) − Vth (VDS ) = Vth,lin − Vth, sat (3.45)

where Vth,lin and Vth,sat are the threshold voltages in the linear and the saturation regimes, respectively. 3.3.3 IV Model The proposed DMDG structure can be treated as two transistors connected in parallel, each having its own threshold voltage Vth1 and Vth2 relating to back gate and front gate respectively. The channel current is then given by [28] I ch = W µneff Cox 1 2 (VGS − Vthi )VDS − 2 VDS V i =1,2 L 1 + DS LEC

∑

in linear region

(3.46)

41

I ch =

i =1,2

∑

W µneff Cox V L 1 + DS , sati LEC

1 2 (VGS − Vthi )VDS , sati − 2 VDS , sati in saturation region

(3.47)

where Vthi corresponds to the back gate and the front gate threshold voltage for i=1, 2, respectively, EC is the critical electric field at which electron velocity ( υns ) saturates and VDS,sati is the saturation voltage and are given by EC =

µneff

2υns

;

VDS , sati =

VGS − Vthi V − Vthi 1 + GS LEC

(3.48)

where µneff is the effective mobility (Watt’s mobility model [32]) of the inversion layer electrons given by 1

µneff

=

1

µ ph

+

1

µ sr

(3.49)

where µph is the mobility associated with the phonon scattering and µsr is the mobility associated with the surface roughness scattering as discussed in [28] and are given by

µ ph

Eeff = µ ref 1 6 10 V / cm

α1

E µ sr = µ ref 2 6 eff 10 V / cm

α2

where µ ref 1 , µ ref 2 , Eeff , α1 and α 2 are the parameters for Watt’s mobility model and the values are as given in [28]. However, (3.46) and (3.47) do not include the short channel effects, the parasitic BJT effects and the impact ionization. To develop an accurate analytical drain current model, we need to consider the above effects as discussed below. a) The impact ionization and parasitic BJT effects Depending on the biasing condition, the impact ionization and the parasitic BJT

42

effects strongly affect the current conduction of the device. As the lateral electric field in the device is large in the saturation region, the impact ionization and the BJT effects are important. In the inversion layer at the oxide-silicon interface, there is a channel current (Ich), which is due to the drifting of the electrons. In the high electric field region near the drain, the drifting electrons collide with the lattice, resulting in electron and hole pairs. The generated electrons and holes move in the opposite direction as a result of the electric field − the generated electrons move towards the drain contact and the generated holes move in the source direction. Thus, the impact ionization results in the generated electron and hole current (Ih), equal in magnitude. For a very short-channel SOI MOS device, the parasitic BJT with its emitter at the source and its collector at the drain cannot be overlooked. A portion of the impact ionization current (KIh) is directed towards the source. As a result, the holes get accumulated in the thin film, which leads to the activation of the parasitic bipolar transistor. As the bipolar device is activated, these holes recombine with the electrons in the base region. In the parasitic bipolar device, a portion of the collector current (K’IC), which is mainly composed of electrons, is toward the high electric field as result of the vertical electric field. These electrons also collide with the lattice, and consequently also generate electron and hole pairs as described above. The drain current is composed of the channel current (Ich), the impact ionization current (Ih), and the collector current (IC) of the parasitic bipolar device [29]: ID = Ich+Ih+IC The collector current can be expressed in terms of the emitter current (IE): I C = α I E + I CBO (3.51) (3.50)

where ICBO, which is a function of the gate voltage, is the leakage current between the

43

collector and the base with the emitter open: I CBO = Wtsi I SO 1 + θ1 (VG − Vthi ) (3.52)

where ISO is the leakage current per unit cross section in the collector-base junction. The source current can be expressed as the sum of the channel current (Ich), a portion of the impact ionization current [(1-K)Ih], and the emitter current (IE) of the bipolar device: I S = I ch + (1 − K ) I h + I E (3.53)

The impact ionization current is a function of the current components, which include the channel current (Ich) and a portion of the collector current (K’IC) flowing through the high electric field region: I h = ( M − 1)( I ch + K ' I C ) where M is the multiplication factor given by β M − 1 = α (VDS − VDS , sat ) exp − V −V DS , sat DS (3.55) (3.54)

where α and β are process-dependent fitting parameters [33]. Note that at the onset of saturation, M-1=0. For current continuity, the source current should be equal to the drain current. Therefore, from eqns (3.50) - (3.54), one obtains the emitter current and the impact ionization current as: IE = K ( M − 1) 1 + KK '( M − 1) I ch + I CBO 1 − [1 + KK '( M − 1)]α o 1 − [1 + KK '( M − 1)]α o (3.56)

K' 1 − αo I h = ( M − 1) I ch + I CBO 1 − [1 + KK '( M − 1)]α o 1 − [1 + KK '( M − 1)]α o From eqns (3.50), (3.51), (3.56) and (3.57), the drain current is given by ID,sat = GIch+HICBO

(3.57)

(3.58)

44

where

G = 1+

( M − 1) 1 − (1 − K ) α 0 ' 1 − 1 + KK ( M − 1) α 0

H=

1 − 1 + KK ' ( M − 1) α 0

1 + K ' ( M − 1)

The values of K, K’, α o , ISO, ICBO [29] are given in Table 1. The drain current is equal to the channel current before the onset of saturation. b) The channel length modulation, velocity overshoot and DIBL effects Non-local effects are becoming more and more prominent as the MOSFET dimensions shrink to the deep submicrometer regime. Velocity overshoot is one of the most important effects from the practical point of view as it is directly related with the increase of the current drive and the transconductance [34-37]. It has been shown that an electric field step causes the electron velocity to overshoot the value that corresponds to the higher field for a period shorter than the energy relaxation time. Therefore, as the longitudinal electric field increases, the electron gas starts to be in non-equilibrium with the lattice with the result that electrons can be accelerated to velocities higher than the saturation velocity. This result has been shown for channel lengths under 0.15µm. Using (3.46), (3.47) and considering the channel length modulation [38], the velocity overshoot effects [39] and the DIBL [30], the final expression for the channel current of the DMDG structure is given by

W µ neff Cox I ch = ∑ l V i =1,2 L 1 − d + DS L LEC 1 2 − VDS 2 (3.59)

1 2 W ' ' VGS − Vthi VDS 2 VGS − Vthi VDS − 2 VDS + λa ( L − ld )

(

)

(

)

45

I ch , sat

W µneff Cox = ∑ l VDS , sati i =1,2 L 1 − d + LEC L

1 2 W ' ' VGS − Vthi 2 VGS − Vthi VDS , sati − 2 VDS , sati + λa L − ld ) (

(

)

(

)

1 2 VDS , sati − VDS , sati 2

(3.60)

where (3.59) corresponds to the current in the linear region and (3.60) corresponds to the current in the saturation region, λa is a parameter that takes into account velocity overshoot effects which is taken to be as 25×10-5 cm3/Vs as suggested in [39],

' Vthi = Vthi − DIBL and ld is the channel length modulation factor as given in [38].

c) Total drain current Using (3.58) and (3.60), the total drain current of the DMDG SOI MOSFET is given by the expression

W µneff Cox 1 2 1 2 W ' ' V − Vthi VDS ,sati − VDS ,sati + HICBO = G∑ 2 GS V − Vthi VDS ,sati − 2 VDS ,sati + λa l VDS , sati GS 2 i =1,2 ( L − ld ) d L 1 − + L LEC

I D,sat

(

)

(

)

(3.61) Equation (3.61) corresponds to the drain current in the saturation region. Drain current in the linear region is equal to the channel current given by (3.59).

46

Table 3.1: Device parameters used in the model and the simulation of the DMDG and the DG SOI MOSFETs. Parameter Front gate oxide, tf Back gate oxide, tb Film thickness, tsi Body doping, NA Source/drain doping, ND Length of source/drain regions Distance between source/drain contact and gate Work function p+ poly Work function n+ poly K K’ ISO Value 2 nm 2 nm 12 nm 1015 cm-3 5×1019 cm-3 100 nm 50 nm 5.25 eV 4.17 eV 0.85 0.85 80 A°/cm2 0.997 6

αo θ1

3.4

Results and Discussion To verify the proposed analytical model, the 2-D device simulator MEDICI was

used to simulate the different aspects, viz. the surface potential, the electric field, the threshold voltage etc. and compare with the results predicted by the analytical model.

47

3.4.1

Surface Potential and Electric Field Typical dimensions used for both the DMDG and the DG structures are

summarized in Table 3.1. Surface potential distribution within the silicon thin-film was simulated with MEDICI. Fig. 3.2 shows the calculated and simulated surface potential profile for a channel length of 100nm at the silicon-oxide interface of the DMDG structure along with the simulated potential profile of the DG structure. It is clearly seen that the DMDG structure exhibits a step function in the surface potential along the channel. Because of this unique feature, the area under p+ poly front gate of the DMDG structure is essentially screened from the drain potential variations. This means that the drain potential has very little effect on the drain current after saturation [14] reducing the drain conductance and the drain induced barrier lowering (DIBL) as discussed below. The predicted values of the model (3.23) and (3.26) agree well with the simulation results. Fig. 3.3 shows the surface potentials at the front and back gates of the DMDG and DG SOI MOSFETs along the channel using MEDICI. It can be observed that DMDG structure exhibits a step in the surface potential profile at the front gate as well as at the back gate. The step, which is quite substantial in the front gate surface potential, occurs because of the difference between the workfunctions of n+ poly and p+ poly. Though the back gate in DMDG structure consists of a single material, n+ poly, a small step can be seen in the back gate surface potential when the silicon film thickness is thin enough. This step occurs because of the coupling between the front channel and the back channel of the DMDG structure. This step in the back gate surface potential profile enables the DMDG structure to exhibit the reverse short channel effect (RSCE) i.e., the threshold

48

voltage rolls-up with decreasing channel lengths. Though the coupling between surface potential profiles of the front gate and the back gate is present in the DG SOI MOSFET also, reverse short channel effect cannot be observed. The back gate surface potential profile plays a dominant role in deciding the threshold voltage of an asymmetrical DG SOI structure, since the back gate consists of n+ poly which has a workfuction smaller than that of the p+ poly. Since the back gate surface potential of the DMDG structure has a step profile without having used two materials in the back gate, the coupling in the DMDG structure helps in improving the short channel behavior. Fig. 3.4 shows the back gate surface potential profiles of the DMDG structure along the channel for different film thicknesses. It can be clearly seen that as the film thickness increases, the step in the potential profile decreases and diminishes when the film thickness is thick enough. This is because when the film thickness is large, the coupling between the front and the back gate surface potentials is minimal. This result clearly demonstrates that to observe the RSCE or the threshold voltage roll-up with decreasing channel lengths, the film thickness should be as small as possible so that maximum coupling between the surface potential of the front gate and the back gate occurs. Fig. 3.5 shows the calculated and simulated values of the electric field along the channel length at the drain end for the DMDG SOI MOSFET and the simulated values for the DG SOI MOSFET for the same channel length. Because of the discontinuity in the surface potential of the DMDG structure, the peak electric field at the drain is reduced substantially, by approximately 40%, when compared with that of the DG structure that leads to a reduced hot carrier effect. The agreement between the model (3.33) and

49

simulated results proves the accuracy of the model.

2.0 Surface Potential (V) 1.5

VGS = 0.15V

DMDG (MEDICI) DMDG (MODEL) DG (MEDICI)

1.0 VDS = 0.75V 0.5 0.0

0

20 40 60 80 100 Position along the channel (nm)

Fig. 3.2: Surface potential profiles of DMDG and DG-SOI MOSFETs for a channel length L = 0.1µm (L1 =L2 = 0.05µm).

2.0 Surface Potential (V) 1.5 1.0 0.5

L1 = L2 = 50 nm tsi = 12 nm tf = tb = 2 nm VGS = 0.1 V VDS = 0.75 V Back gate

DMDG DG

Front gate

0.0 0.00

0.02 0.04 0.06 0.08 Position along the channel (µm)

0.10

Fig. 3.3: Surface potential profiles at front gate and back gate for DMDG and DG-SOI MOSFETs for a channel length L = 0.1 µm (L1 = L2 = 0.05 µm) using MEDICI.

50

Back Gate Surface Potential (V)

1.6 L1 = L2 = 50 nm

tf = tb = 2 nm

1.4 VGS = 0.1 V

VDS = 0.75 V

1.2 1.0 0.8 0.6 0.00

tsi = 12 nm tsi = 20 nm tsi = 25 nm

0.02 0.04 0.06 0.08 Position along the channel (µm)

0.10

Fig. 3.4: Back gate surface potential profiles for different film thicknesses for DMDG SOI MOSFETs for a channel length L = 0.1 µm (L1 = L2 = 0.05 µm) using MEDICI.

1.8 Electric Field (MV/cm) 1.5 1.2 0.9 0.6 0.3 0.0 70

**DMDG (MEDICI) DMDG (MODEL) DG (MEDICI)
**

VGS = 0.15V VDS = 1V

80 90 100 Position along the channel (nm)

Fig. 3.5: Electric-field variation at the drain end along the channel at the Si-SiO2 interface of DMDG and DG SOI MOSFETs for a channel length L = 0.1µm (L1 =L2 = 0.05µm).

51

3.4.2

Threshold Voltage and Drain Induced Barrier Lowering In Fig. 3.6, the threshold voltage of the DMDG structure as a function of channel

length is compared with that of the DG MOSFET and the proposed model (3.44). It can be observed clearly that the proposed DMDG structure exhibits a reverse short channel effect (RSCE), i.e., the threshold voltage “roll-up” with fixed L1, while the threshold voltage of the DG structure rolls-down with decreasing channel lengths. The threshold voltage roll-up occurs because as the channel length decreases, keeping L1 fixed, the proportion of the channel length influenced by p+ poly of the front gate at the back gate increases which leads to an increase in the threshold voltage. This unique feature of the DMDG structure is an added advantage when the device dimensions are continuously shrinking. With decreasing channel lengths, it is very difficult to fabricate precise channel lengths. A threshold voltage variation from device to device is least desirable. The DMDG structure exhibits a threshold voltage that is almost constant with decreasing channel lengths. From the results it is clearly seen that the calculated values of the analytical model tracks the simulated values very well. Fig. 3.7 shows the DIBL variation along the channel for both the DMDG and the DG SOI MOSFETs. The simulated DIBL results are calculated as the difference between the linear threshold voltage (Vth,lin) and the saturation threshold voltage (Vth,sat). The parameters, tf, tb and tsi used here are 2nm, 3nm and 20nm respectively. The linear threshold voltage, is based on the maximum transconductance method at VDS = 0.05V. The saturation threshold voltage is based on a modified constant-current method at VDS = 1V where the critical current is defined as the drain current when VGS = Vth,lin [40]. Again it can be observed clearly that the DIBL increase in the DMDG is far less when compared

52

**0.30 Threshold Voltage, Vth(V)
**

VDS = 50mV

0.25 0.20 0.15 0.10

L1 = 50nm

DMDG (MEDICI) DMDG (MODEL) DG (MEDICI)

60

70 80 90 Channel length (nm)

100

Fig. 3.6: Threshold voltage of DMDG and DG SOI MOSFETs is plotted for different channel lengths (L1 fixed at 0.05µm).

50 DIBL, Vth,lin -V th,sat (mV) 40 30 20 10 60

**DMDG (MEDICI) DMDG (MODEL) DG (MEDICI)
**

VDS = 1V

70 80 90 Channel length (nm)

100

Fig. 3.7: DIBL of DMDG and DG SOI MOSFETs is plotted for different channel lengths, L=L1 + L2 where L1 = L2. The parameters used are tox =2nm, tb = 3nm, tsi = 20nm.

53

with the DG MOSFET with decreasing channel lengths. The step profile ensures that the drain potential is screened and the surface potential minima at the source end remains effectively unchanged which accounts for the reduction in DIBL. 3.4.3 IV Characteristics Drain current characteristics of both the DMDG and the DG MOSFETs are shown in Fig. 3.8. In the case of the DMDG structure, the results obtained from the model are also shown. Fig. 3.8 demonstrates that the DMDG structure exhibits an improved transconductance, a reduced drain conductance and an increase in the drain breakdown voltage. This enhancement in the performance is because of the step function of the surface potential profile along the channel, which reduces the DIBL and the peak electric field at the drain end. In the drain current analytical model various short channel effects such as the channel length modulation, the DIBL, the velocity overshoot have been considered along with the breakdown mechanisms involved: the parasitic BJT effects and the impact ionization. Fig. 3.9 and Fig. 3.10 show the transconductance (gm) and the drain conductance (gd) for both the structures for different channel lengths. The gm is extracted from the slope of ID-VGS between VGS = 1V and 1.5V at VDS = 0.75V while gd is extracted from the slope of ID-VDS between VDS = 0.5V and 0.75V at VGS = 1.5V for both simulation and the model predicted values. Fig. 3.11 shows the voltage gain of the DMDG and the DG SOI MOSFETs. Because of the increase in the transconductance and decrease in the drain conductance, the voltage gain (gm/gd) predicted for the DMDG structure is much higher when compared with the DG structure.

54

Drain Current, ID (mA)

4 3 2 1

**DMDG (MEDICI) DMDG (MODEL) DG (MEDICI)
**

L1 = L2 = 50nm VGS = 1.5V VGS = 1V

VGS = 0.5V

0 0.0

0.5 1.0 1.5 Drain Voltage, VDS (V)

2.0

Fig. 3.8: ID - VDS characteristics of the DMDG and DG-SOI MOSFETs for a channel length L = 0.1µm

1.5 1.4 gm (mS/µ m) 1.3 1.2 1.1

VDS = 0.75V

DMDG (MEDICI) DMDG (MODEL) DG (MEDICI)

1.0

60

70 80 90 Channel length (nm)

100

Fig. 3.9: Variation of gm with different channel lengths, (L1 = L2) for DMDG and DG SOI MOSFETs.

55

0.25 0.20 gd (mS/µ m) 0.15 0.10 0.05

VGS = 1.5V

0.00

DMDG (MEDICI) DMDG (MODEL) DG (MEDICI)

60

70 80 90 Channel length (nm)

100

Fig. 3.10: Variation of gd with different channel lengths, (L1 = L2) for DMDG and DG SOI MOSFETs.

**20 Voltage gain, gm/gd 16 12 8 4 0 60
**

DMDG (MEDICI) DMDG (MODEL) DG (MEDICI)

70 80 90 Channel length (nm)

100

Fig. 3.11: Variation of voltage gain with different channel lengths, (L1 = L2) for DMDG and DG SOI MOSFETs.

56

3.5

Summary The concept of the Dual-Material-Gate has been applied to the Double Gate

structure and the features exhibited by the resulting new structure, Dual Material Double Gate, have been examined for the first time by developing an analytical model. The results obtained from the model agree well with the MEDICI simulation results. The results show that the DMDG structure leads to reduced short channel effects as the surface potential profile shows a step at the interface of the two materials of the front gate, which reduces the drain conductance and the DIBL. Moreover, the peak electric field at the drain end is reduced, minimizing the hot carrier effect. The threshold voltage shows a roll-up with reducing channel lengths. In addition, it has been demonstrated that the DMDG MOSFET offers higher transconductance and drain breakdown voltage. All these features should make the proposed DMDG SOI MOSFET a prime candidate for the future CMOS ULSI chips. Because of the asymmetric nature of the DMDG structure, it may pose few challenges while integrating with the present CMOS technology. But Zhou [14] suggested two fabrication procedures requiring only one additional mask step with which a dual material gate can be obtained. As the CMOS processing technology is maturing and already into the sub-100 nm [41] regime, fabricating a 50 nm feature gate length should not hinder the possibility of achieving the potential benefits and excellent immunity against the SCE’s that the DMDG SOI MOSFET promises.

57

CHAPTER IV

INVESTIGATION OF THE NOVEL ATTRIBUTES OF A SINGLE HALO DOUBLE GATE SOI MOSFET: 2D SIMULATION STUDY

4.1

Introduction The scaling of CMOS technology in deep submicron regime has enabled the

system-on-chip (SoC) applications that integrate the RF/analog and the digital logic functions. Most of the analog applications rely on pure digital CMOS technology [42]. However deeply scaled analog CMOS device design for SoC applications is particularly challenging, since the analog and digital circuit requirements are often conflicting. High performance logic devices like the double pocket structures, with good current drive-tooff state leakage tradeoff and good control of short channel effects, often have poor analog performance in terms of low output resistance, device gain, transconductance-todrive current ratio, and matching properties [43]. Recently, single pocket (SP) or asymmetric channel structures are suggested for mixed mode applications [44-45]. They have shown good digital performance compared to the double pocket or the super halo devices as well as the super steep retrograde devices [46], due to their laterally asymmetric channel doping profile that suppresses SCE and exploiting velocity overshoot to improve current drive [18]. The single halo MOSFET structures have been introduced for the bulk [18] as well as the SOI MOSFETs [19] to adjust the threshold voltage and improve the SCE. The halo implantation devices show excellent output characteristics with low DIBL, no kink, higher drive currents, flatter saturation characteristics, and slightly higher breakdown voltages compared to the conventional MOSFET. However, no such attempt has been

59

reported on the DG MOSFET. In this paper, for the first time we have investigated the performance of the DG structure with halo implantation using 2-D numerical simulations. The unique features of the double gate single halo (DG-SH) device are explored and compared with those of a conventional DG structure in terms of the threshold voltage (Vth) variation with the channel length and the film thickness, the drain-induced barrier lowering (DIBL), the on-current (Ion), the off-current (Ioff), and the ratio of transconductance to the drain conductance (gm/gd) with an intention to explore the potential benefits of the DG-SH structure over its counterpart.

G S n+ p

+

D n+ (a) tf tsi tb

L p

+

n G

S n+ p+ LP

p

+

D p n+ (b) tf tsi tb

L n

+

Fig.4.1 : Cross-sectional view of (a) DG-SOI MOSFET (b) DG-SH SOI MOSFET

60

4.2

DG-SH structure and its parameters Schematic cross-sectional views of the DG and the DG-SH n-channel MOSFET

implemented in the 2-D device simulator MEDICI are shown in Fig. 4.1. The doping in the p-type body and the n+ source/drain regions is kept at 1x1015cm-3 and 5x1019cm-3 respectively. Pocket implantation, NAP, on the source side of the DG-SH MOSFET is kept at 8x1017cm-3 while the length of the pocket, Lp, is fixed at 4nm. Typical value of the front-gate oxide thickness (tf) and the back-gate oxide thickness (tb) is taken as 2.5nm while the thin-film thickness (tsi) is kept at 20nm respectively. The values of different parameters are summarized in Table 4.1. Table 4.1: Device parameters used for the simulation of the DG-SH and the DG SOI MOSFETs Parameter Front gate oxide, tf Back gate oxide, tb Film thickness, tsi Body doping, NA Source/drain doping, ND Halo doping, NAP Length of halo implantation, LP Value 2.5 nm 2.5 nm 20 nm 1015 cm-3 5×1019 cm-3 8×1017 cm-3 4 nm

61

4.3

Results and Discussion Simulation studies are performed to explore the characteristics of the DG-SH SOI

MOSFET with the conventional DG structure. Comparisons between the two structures are drawn out on the basis of the threshold voltage variation with the channel length, the DIBL, the saturation current (Ion), the off-state leakage current (Ioff), the transconductance and the drain conductance. The DIBL is measured as the difference of the linear threshold (Vth,lin) voltage and the saturation threshold voltage (Vth,sat). The linear threshold voltage is based on the maximum transconductance (gm) method (linear extrapolation of ID – VGS to zero) at VDS = 50mV. The saturation threshold voltage is based on a modified constant-current method at VDS = 0.75V [40]. The saturation current is the drain current at VDS = 0.75V. The leakage current is the drain current at VGS = 0V and VDS = 0.75V (or VDS = 0.05V, as stated). The transconductance, gm, is extracted from the slope of ID - VGS at VGS = VDS = 0.75 V. The drain conductance (gd) is extracted from the slope of ID - VDS between VDS = 0.5V and 0.75V at VGS = 1.0V. 4.3.1 Surface Potential To gain an insight into the physical mechanism responsible for the improved performance of the DG-SH structure, the surface potential profile is plotted at the interface of the front-gate oxide and the thin film. Fig. 4.2 shows the surface potential plots for both the DG and the DG-SH MOSFETs for channel lengths 0.1µm and 0.2µm. As can be observed from the figure, a small step on the source side occurs in the surface potential profile in the case of DG-SH structure. This step function in the case of DG-SH structure is due to the higher doping near the source end. Because of this step in the surface potential profile, there is almost a zero shift in the minimum surface potential

62

2.0 Surface Potential (V) 1.6 1.2 0.8 0.4

DG DG-SH VGS = 0.25V VDS = 0.75V

0.0

0.00

0.04 0.08 0.12 0.16 0.20 Position along the channel (µm)

Fig. 4.2: Surface potential profiles of DG-SH and DG-SOI MOSFETs for channel lengths 0.1µm and 0.2µm with a film thickness of 20nm. which leads to a reduced DIBL and an extended threshold voltage roll-off is observed. 4.3.2 Threshold Voltage and DIBL Fig. 4.3 shows the threshold voltage variation with channel length for the DG and the DG-SH down to 80nm for a fixed film thickness, tsi = 20nm. The so-called reverse short channel effect [47-50] is clearly seen here as the threshold voltage slightly increases with decrease in channel length for the DG-SH MOSFET. This is because of the screening of the drain voltage as the channel length decreases due to the step function in the surface potential profile and the surface potential minima is essentially least affected. On the other hand, the threshold voltage rolls-off rapidly for the DG MOSFET. In the case of the DG structure, as the channel length decreases, the drain bias shifts the surface potential minimum which leads to the roll-off in the threshold voltage. It can also be

63

noted that the threshold voltage of the DG-SH structure is slightly higher than that of the DG structure due to the increase in the doping at the source end in the former. Fig. 4.4 shows the threshold voltage variation with film thickness, tsi, for a fixed channel length, L = 100nm. Due to the presence of the reverse short channel effect, it can be observed that the threshold voltage dependence on film thickness in the DG-SH MOSFET is much less compared to the DG structure. Another important short channel effect is the DIBL. Fig. 4.5 shows the DIBL parameter for both the DG and the DG-SH MOSFETs for channel lengths down to 80nm. This figure demonstrates that the DIBL is far less in the DG-SH structure when the channel length is reduced below 120nm than in the case of the DG structure.

**0.25 Threshold Voltage, Vth (V) 0.20 0.15 0.10 0.05 0.00
**

VDS = 50mV tsi = 20nm DG DG-SH

0.09

0.12 0.15 0.18 Channel length (µ m)

0.21

Fig. 4.3: Threshold voltage of DG-SH and DG SOI MOSFETs is plotted for different channel lengths for a film thickness of 20nm.

64

Threshold voltage, Vth (V)

0.30 0.25 0.20 0.15 0.10 0.05 0.00

L = 0.1µm VDS = 50mV DG DG-SH

10

15 20 Film thickness, t si (nm)

25

Fig. 4.4: Threshold voltage of DG-SH and DG SOI MOSFETs is plotted for different film thicknesses for a fixed channel length 0.1µm.

**30 DIBL, Vth,lin-V th,sat (mV) 25 20 15 10 5 0 0.09 0.12 0.15 0.18 Channel length (µm) 0.21
**

DG DG-SH

Fig. 4.5: DIBL of DG-SH and DG SOI MOSFETs is plotted for different channel lengths for a film thickness of 20nm.

65

4.3.3

Subthreshold Slope and On/Off Currents Fig. 4.6 shows the subthreshold slope of the DG and the DG-SH MOSFETs. It is

clear from the figure that the subthreshold behavior of both the structures is almost identical and the subthreshold slope is around 60mV/dec. The subthreshold slope of the DG-SH is expected to degrade because of the increase in the doping near the source end, but as can be seen, the increase is very small. The increase in subthreshold slope in DGSH MOSFET gives rise to a notion that the off-state leakage current of this structure will be greater than that of the DG MOSFET. But due to the screening of the drain bias by the step function in the surface potential profile, the increase in the leakage current is suppressed and the off-state leakage current is in fact less than that of the DG MOSFET. This can be observed in Fig. 4.7.

Subthreshold slope, S(mV/dec)

64 63 62 61 60

DG DG-SH

VDS = 50mV

0.08

0.12 0.16 Channel length (µm)

0.20

Fig. 4.6: Subthreshold slope of DG-SH and DG SOI MOSFETs is plotted for different channel lengths for a film thickness of 20nm.

66

Off state Leakage current, Ioff (A/µm)

**8×10-8 6×10-8 4×10-8 2×10-8 0
**

VDS = 0.75V

DG DG-SH

1.2 0.9 0.6 0.3 0.0

VDS = 50mV

0.08

0.12 0.16 0.20 Channel length (µ m)

Fig. 4.7(a): Variation of Ioff and Ion with channel length for DG-SH and DG SOI MOSFET for a film thickness of 20nm.

**3.0 ×105 2.4 ×105 Ion / Ioff 1.8 ×105 1.2 ×105 6×104 0 0.08 0.12 0.16 Channel length (µm) 0.20
**

DG DG-SH VDS= 50mV

Fig. 4.7(b): Ratio of Ion and Ioff with channel length for DG-SH and DG SOI MOSFET for a film thickness of 20nm at VDS= 0.75V.

67

Saturation current, Ion(mA/µ m)

10-7

1.5

Fig. 4.7(a) shows the saturation current (Ion) and the off-state leakage current (Ioff) for both the configurations. It can be seen that the saturation current of the DG-SH MOSFET is slightly lower than that of the DG MOSFET due to the increased threshold voltage of the former structure. It can also be observed that the off-state leakage current in the DG-SH structure is much less and there is nearly an order of magnitude difference in this current for a drain voltage, VDS= 0.75V, when the channel length is in the sub 100nm regime for the two structures. In other words, the on-off current ratio, (Ion/Ioff), of the DG-SH MOSFET is large compared to that of a DG MOSFET. This can be clearly observed from Fig. 4.7(b), where the Ion/Ioff ratio of both the DG and the DG-SH is shown. 4.4 IV Characteristics Output characteristics of the DG and the DG-SH SOI devices are compared for the same channel length, L = 0.1µm in Fig. 4.8. It is evident that the drive capability of the DG-SH is slightly less when compared with conventional the DG structure. This is because of the increase in the threshold voltage of the DG-SH when compared to the DG structure. It can be easily interpreted that while the transconductance is almost same for both the structures, the drain conductance is much less in the case of the DG-SH MOSFET, which leads to an increased voltage gain. The other advantages of the DG-SH MOSFET are the absence of kink in the drain characteristics and a slight increase in the breakdown voltage when compared to the DG MOSFET. Fig. 4.9 shows the transconductance (gm) and the drain conductance (gd) of the DG and the DG-SH MOSFETs. This figure clearly demonstrates that while the transconductance of both the structures is identical, the drain conductance is much less in

68

the case of the DG-SH MOSFET. This is primarily due to the reverse short channel effect and the reduced DIBL in the case of the DG-SH MOSFET. Fig. 4.10 shows the voltage gain of both the structures. Because of the drastic improvement in the drain conductance, a considerable increase in the voltage gain (gm/gd) can be observed for the DG-SH MOSFET when compared with the DG-MOSFET.

Drain Current, ID (mA/µm)

3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0

VGS=1.5V

VGS=1.0V

VGS=0.5V

DG DG-SH

0.5 1.0 1.5 Drain Voltage, VDS (V)

2.0

Fig. 4.8: ID-VDS characteristics of the DG-SH and DG-SOI MOSFETs for a channel length L = 0.1µm with a film thickness of 20nm.

69

3.0 2.5 gm , gd (mS/µm) 2.0 1.5 1.0 0.5 0.0 0.08

gd gm

DG DG-SH

0.12 0.16 Channel length (µm)

0.20

Fig. 4.9: Variation of gm, gd with different channel lengths for DG-SH and DG SOI MOSFETs.

**10 Voltage gain, gm /gd 8 6 4 2 0 0.08 0.12 0.16 Channel length (µ m)
**

DG DG-SH

0.20

**Fig. 4.10: Variation of voltage gain with different channel lengths DG-SH and DG SOI MOSFETs.
**

70

4.4

Summary The concept of channel engineering has been applied to an asymmetrical double

gate (DG) SOI MOSFET. The features of the resulting structure, the double gate single halo (DG-SH) SOI MOSFET have been studied in the context of its potential integration in the current CMOS technology and a comparison has been drawn out with the conventional asymmetric DG SOI structure. The unique features of the DG-SH MOSFET that are not easily available in the conventional asymmetric DG SOI devices include: threshold voltage roll-up, reduced DIBL, kink free output characteristics and an increase in the drain breakdown voltage.

71

CHAPTER V

CONCLUSIONS The work presented in this thesis can be divided into three categories, namely, (1) Analytical Model for a partially depleted (PD) dual-material gate (DMG) SOI MOSFET, (2) Analytical model for a dua1-material double gate (DMDG), and (3) 2-D numerical simulation studies of a double gate single halo (DG-SH) doped SOI MOSFET. a) DMG-PD SOI MOSFET Analytical model of the surface potential along the channel and of threshold voltage in a DMG-PD SOI MOS device is developed by solving the 2-D Poisson’s equation using a parabolic approximation. The conclusions are: 1. The 2-D surface potential model predicts a step in the channel potential profile due to the presence of the two different gate materials with the finite workfunction difference and the controllable gate lengths. 2. The shift in the surface channel potential minima position is negligible with the increasing drain biases. This leads to an excellent immunity against the shortchannel effects (SCE) like the drain-induced barrier lowering (DIBL) and the channel length modulation (CLM). 3. The peak electric field at the drain end is lowered leading to a reduced hot-carrier effect. 4. The threshold voltage, Vth, rolls-up with decreasing channel length in a DMG SOI MOSFET down to 0.1µm if the length and workfunction of the gate materials are chosen appropriately.

73

b) DMDG SOI MOSFET Analytical model of the surface potential, the threshold voltage and the drain characteristics is developed and the short channel performance of the proposed DMDG structure is compared with the asymmetrical DG SOI MOSFET. The conclusions are: 1. The surface potential model predicts the creation of a step in the channel potential profile when the DMG concept is applied to the DG SOI MOSFET. 2. The DMDG structure predicts an improved short channel performance when compared with the DG SOI MOSFET. The short channel behavior was analyzed with respect to the threshold voltage and the DIBL variation with channel length. The proposed structure exhibits a threshold voltage roll-up and a reduced DIBL when compared with the DG structure. Also the peak electric field at the drain end is lowered in the DMDG MOSFET leading to the reduced hot-carrier effect. 3. The proposed IV model and the simulated characteristics for the DMDG structure show a remarkable improvement when compared with the DG SOI MOSFET in terms of increased transconductance, reduced drain conductance and a consequent increase in the voltage gain. The IV characteristics of the proposed structure also predict an increase in the drain breakdown voltage. c) DG-SH SOI MOSFET 2-D MEDICI simulations were used to explore and compare the novel attributes offered by the double gate single halo (DG-SH) doped structure with a conventional asymmetrical DG SOI in terms of Vth variation with the decreasing channel length,

74

the drain-induced barrier-lowering (DIBL), the leakage current, the drive current, the transconductance, the drain conductance and the voltage gain. The conclusions are: 1. The surface potential profile exhibits a small step because of the increased doping at the source end. 2. The unique features of the DG-SH are: Vth roll-up with decreasing channel length, reduced DIBL, improvement in SCE suppression and reduced drain conductance. SCOPE FOR FUTURE WORK Several possible extensions could be attempted as ongoing research work. Some specific recommendations based on the present work are as follows: 1. The proposed structures can be applied at the circuit level (e.g. inverter) and the performance of the resulting circuit can be compared with a circuit that is composed of the compatible conventional structures. 2. A lot of scope lies in studying the effect of the proposed structures on devices employing wide bandgap materials like SiC. 3. Experimental results can provide further confirmation of the efficiency of the proposed structures.

75

76

APPENDIX A

COMMENT Partially depleted DMG-SOI with channel length L = 0.1 µm

COMMENT SPECIFY A RECTANGULAR MESH MESH SMOOTH=1 COMMENT X.MESH X.MESH X.MESH X.MESH X-mesh: gate length of 0.1 µm X.MAX=0.250 H1=0.05 X.MIN=0.250 H1=0.005 X.MAX=0.3 X.MIN=0.3 H1=0.0025 X.MAX=0.35 X.MIN=0.35 H1=0.05 WIDTH=0.25

COMMENT Y-mesh: gate oxide of 2 nm, thin-film thickness of 100 nm Y.MESH N=1 L=-0.0060 Y.MESH N=4 L=0 Y.MESH DEPTH=0.1 H1=0.01 Y.MESH DEPTH=0.45 H1=0.0250 Y.MESH DEPTH=.5 H1=0.250 COMMENT Eliminate some unnecessary substrate nodes ELIMIN COLUMNS Y.MIN=0.1 X.MIN=0.0 X.MAX=0.6 COMMENT Specify oxide and silicon regions REGION SILICON REGION OXIDE IY.MAX=4 REGION OXIDE Y.MIN=.1 Y.MAX=0.55 COMMENT Electrode definition ELECTR NAME=Gate1 X.MIN=.25 X.MAX=0.3 IY.MIN=1 IY.MAX=3 ELECTR NAME=Gate2 X.MIN=.301 X.MAX=0.35 IY.MIN=1 IY.MAX=3 ELECTR NAME=Substrate BOTTOM ELECTR NAME=Source X.MAX=.2 IY.MAX=4 ELECTR NAME=Drain X.MIN=0.4 IY.MAX=4 COMMENT Specify impurity profile and fixed charges PROFILE P-TYPE N.PEAK=1E18 UNIFORM OUT.FILE=DMPDSOI1DS_10 PROFILE N-TYPE N.PEAK=5E19 UNIFORM Y.MAX=.1 X.MIN=0 X.MAX=.25 PROFILE N-TYPE N.PEAK=5E19 Y.MAX=.1 X.MIN=.35 UNIFORM PLOT.2D GRID TITLE="INITIAL GRID" FILL SCALE

COMMENT Gate workfunction specification CONTACT NAME=Gate1 WORKFUNC=4.63 CONTACT NAME=Gate2 WORKFUNC=4.17 PLOT.2D GRID TITLE="SOI - DOPED GRID" FILL SCALE COMMENT Specify physical models to use

77

MODELS

CONMOB SRFMOB CONSRH FLDMOB AUGER BGN

COMMENT Symbolic factorization, solve, regrid on potential SYMB CARRIERS=0 METHOD ICCG DAMPED SOLVE REGRID POTEN IGNORE=OXIDE RATIO=1.0 MAX=1 SMOOTH=1 + IN.FILE=DMPDSOI1DS_10 + OUT.FILE=DMPDSOI1MS_10 PLOT.2D GRID TITLE="SOI-NMOSFET - POTENTIAL REGRID" FILL SCALE COMMENT Solve using refined grid save solution for later use SYMB CARRIERS=0 SOLVE OUT.FILE=DMPDSOI1S_10 PLOT.2D BOUND TITLE="SOI-NMOSFET - IMPURITY CONTOURS" FILL SCALE DEPLETIO CONTOUR DOPING LOG MIN=16 MAX=20 DEL=.5 COLOR=2 CONTOUR DOPING LOG MIN=-16 MAX=-15 DEL=.5 COLOR=1 LINE=2 PLOT.2D BOUND TITLE=DMG-SOI" FILL SCALE DEPLETIO CONTOUR ELECTRON COLOR=2 CONTOUR HOLES COLOR=4 COMMENT Plot the potential at top Si/SiO2 interface at zero bias PLOT.1D POTENTIA CURVE COLOR=5 X.START=0.25 X.END=0.35 Y.START=0 + Y.END=0 TITLE="SURFACE POTENTIAL DISTRIBUTION” COMMENT Plot the surface potential at a specific bias SOLVE V(Source)=0 V(Substrate)=0 LOG OUT.FILE=DMPD1SP1 SOLVE V(Gate1)=0.15 V(Gate2)=0.15 V(Drain)=0.05 PLOT.1D POTENTIA CURVE COLOR=1 X.START=0.25 X.END=0.35 Y.START=0.00 + Y.END=0.00 TITLE="POTENTIAL DISTRIBUTION"

78

COMMENT Gate Characteristics for a 0.1 µm DMG SOI MOSFET. COMMENT Read in simulation mesh MESH IN.FILE=DMPDSOI1MS_100 COMMENT Read in saved solution LOAD IN.FILE=DMPDSOI1S_100 COMMENT Use Newton's method for the solution SYMB NEWTON CARRIERS=1 ELECTRONS COMMENT Setup log file for IV data LOG OUT.FILE=DMPDSOI1GI COMMENT Solve for Vds =0.05 and then ramp gate SOLVE V(DRAIN)=0.05 SOLVE V(GATE1)=0 V(GATE2)=0 ELEC=(Gate1,Gate2) VSTEP=.05 NSTEP=25 COMMENT Plot Ids vs Vds PLOT.1D Y.AXIS=I(DRAIN) X.AXIS=V(Gate1) CURVE COLOR=2 + TITLE="SOI GATE CHARACTERISTICS" OUTFILE=gate.DAT COMMENT Extract MOS parameters like the linear threshold voltage, channel length, etc EXTRACT MOS.PARA IN.FILE=DMPDSOI1GI GATE=Gate1

79

APPENDIX B

COMMENT DMDG SOI MOSFET with channel length L = 0.1 µm

COMMENT Specify a rectangular mesh MESH SMOOTH=1 X.MESH X.MAX=0.05 H1=0.01 X.MESH X.MIN=0.050 H1=0.005 X.MAX=0.1 X.MESH X.MIN=0.1 H1=0.0025 X.MAX=0.15 X.MESH X.MIN=0.15 H1=0.01 WIDTH=0.05 Y.MESH Y.MESH Y.MESH Y.MESH Y.MESH N=1 L=-0.02 N=11 L=0 DEPTH=0.012 H1=0.0025 DEPTH=.002 H1=0.001 DEPTH=.02 H1=0.002

COMMENT Specify oxide and silicon regions REGION SILICON REGION OXIDE IY.MAX=11 REGION OXIDE Y.MIN=0.012 COMMENT Electrode definition ELECTR NAME=Gate1 X.MIN=.05 X.MAX=0.1 IY.MIN=1 IY.MAX=10 ELECTR NAME=Gate2 X.MIN=0.1025 X.MAX=0.15 IY.MIN=1 IY.MAX=10 ELECTR NAME=Gate3 X.MIN=.05 X.MAX=0.15 Y.MIN=.014 ELECTR NAME=Source X.MAX=.04 IY.MIN=1 IY.MAX=11 ELECTR NAME=Drain X.MIN=0.16 IY.MIN=1 IY.MAX=11 COMMENT Specify impurity profile and fixed charges PROFILE P-TYPE N.PEAK=1E15 Y.MIN=0 Y.MAX=0.012 UNIFORM OUT.FILE=DDMDSOI1DS_20 PROFILE N-TYPE N.PEAK=5E19 UNIFORM Y.MAX=.012 X.MIN=0 X.MAX=.05 PROFILE N-TYPE N.PEAK=5E19 Y.MAX=.012 X.MIN=.15 UNIFORM PLOT.2D GRID TITLE="INITIAL GRID" FILL SCALE

CONTACT NAME=Gate1 P.POLY CONTACT NAME=Gate2 WORKFUNC=4.17 CONTACT NAME=Gate3 N.POLY COMMENT Specify physical models to use MODELS CONMOB SRFMOB CONSRH FLDMOB AUGER BGN IMPACT.I COMMENT Symbolic factorization, solve, regrid on potential SYMB CARRIERS=0 METHOD ICCG DAMPED SOLVE REGRID POTEN IGNORE=OXIDE RATIO=1.0 MAX=1 SMOOTH=1

80

+ IN.FILE=DDMDSOI1DS_20 + OUT.FILE=DDMDSOI1MS_20 PLOT.2D GRID TITLE="SOI-NMOSFET - POTENTIAL REGRID" FILL SCALE COMMENT Solve using refined grid save solution for later use SYMB CARRIERS=0 SOLVE OUT.FILE=DDMDSOI1S_20 PLOT.2D BOUND TITLE="SOI-NMOSFET - IMPURITY CONTOURS" FILL SCALE DEPLETIO CONTOUR DOPING LOG MIN=16 MAX=20 DEL=.5 COLOR=2 CONTOUR DOPING LOG MIN=-16 MAX=-15 DEL=.5 COLOR=1 LINE=2 PLOT.2D BOUND TITLE=DMDG-SOI" FILL SCALE DEPLETIO CONTOUR ELECTRON COLOR=2 CONTOUR HOLES COLOR=4 COMMENT Plot surface potential at a specific bias SOLVE V(Source)=0 LOG OUT.FILE=DDMGFDSP1 SOLVE V(Gate1)=0.15 V(Gate2)=0.15 V(Gate3)=0.15 V(Drain)=0.25 PLOT.1D POTENTIA CURVE COLOR=1 X.START=0.05 X.END=0.15 Y.START=0.02 + Y.END=0.02 TITLE="POTENTIAL DISTRIBUTION" TOP=2.5 BOTTOM=-0.5 + OUT.FILE=SP1.DAT COMMENT Plot the electric field PLOT.1D E.FIELD CURVE + X.START=0.05 X.END=0.15 Y.START=0.0 Y.END=0.0 OUT.FILE=EF.DAT

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COMMENT Drain characteristics for DMDG SOI MOSFET COMMENT Read in simulation mesh MESH IN.FILE=DDMDSOI1MS_20 COMMENT Read in saved solution LOAD IN.FILE=DDMDSOI1S_20 COMMENT Do a Poisson Solve only to Bias the Gate SYMB CARRIERS=0 METHOD ICCG DAMPED CONT.STK=8 SOLVE V(Gate1)=0.5 V(Gate2)=0.5 V(Gate3)=0.5 OUT.FILE=DDMG2 SOLVE V(Gate1)=1 V(Gate2)=1 V(Gate3)=1 OUT.FILE=DDMG3 SOLVE V(Gate1)=1.5 V(Gate2)=1.5 V(Gate3)=1.5 OUT.FILE=DDMG4 COMMENT Use Newton's Method and solve SYMB NEWTON CARRIERS=2 COMMENT Ramp the drain voltage LOAD IN.FILE=DDMG2 LOG OUT.FILE=DDMGIV2 SOLVE V(DRAIN)=0 ELEC=(DRAIN) VSTEP=0.025 NSTEP=80 COMMENT Plot Ids vs Vds PLOT.1D IN.FILE=DDMGIV2 Y.AXIS=I(DRAIN) X.AXIS=V(DRAIN) CURVE COLOR=1 + TITLE="DMDG DRAIN CHARACTERISTICS"

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APPENDIX C

COMMENT DG-SH SOI MOSFET with a channel L=0.1µm

COMMENT Specify a rectangular mesh MESH SMOOTH=2 X.MESH X.MAX=0.05 H1=0.01 X.MESH X.MIN=0.050 H1=0.0025 X.MAX=0.15 X.MESH X.MIN=0.15 H1=0.01 width=0.05 Y.MESH Y.MESH Y.MESH Y.MESH Y.MESH N=1 L=-0.006 N=3 L=0 DEPTH=0.02 H1=0.002 DEPTH=.0025 H1=0.001 DEPTH=.02 H1=0.002

COMMENT Specify oxide and silicon regions REGION SILICON REGION OXIDE IY.MAX=3 REGION OXIDE Y.MIN=.COMMENT Electrode definition ELECTR ELECTR ELECTR ELECTR NAME=Gate1 X.MIN=.05 X.MAX=0.15 IY.MIN=1 IY.MAX=2 NAME=Gate2 X.MIN=.05 X.MAX=0.15 Y.MIN=.022 NAME=Source X.MAX=.04 IY.MIN=1 IY.MAX=3 NAME=Drain X.MIN=0.16 IY.MIN=1 IY.MAX=3

COMMENT Specify impurity profile and fixed charges PROFILE P-TYPE N.PEAK=1E15 Y.MIN=0 Y.MAX=0.02 UNIFORM OUT.FILE=DMDSOI1DS_20 PROFILE P-TYPE N.PEAK=8E17 UNIFORM Y.MAX=.02 X.MIN=0.05 X.MAX=0.09 PROFILE N-TYPE N.PEAK=5E19 UNIFORM Y.MAX=.02 X.MIN=0 X.MAX=.05 PROFILE N-TYPE N.PEAK=5E19 Y.MAX=.02 X.MIN=.15 UNIFORM PLOT.2D GRID TITLE="INITIAL GRID" fill scale

CONTACT NAME=Gate1 P.POLY CONTACT NAME=Gate2 N.POLY COMMENT Specify physical models to use MODELS CONMOB SRFMOB CONSRH FLDMOB AUGER BGN COMMENT Symbolic factorization, solve, regrid on potential SYMB CARRIERS=0 METHOD ICCG DAMPED SOLVE REGRID POTEN IGNORE=OXIDE RATIO=1.0 MAX=1 SMOOTH=1 + IN.FILE=DMDSOI1DS_20 + OUT.FILE=DMDSOI1MS_20

83

PLOT.2D GRID TITLE="SOI-NMOSFET - POTENTIAL REGRID" FILL SCALE COMMENT Solve using refined grid save solution for later use SYMB CARRIERS=0 SOLVE OUT.FILE=DMDSOI1S_20 PLOT.2D BOUND TITLE="SOI-NMOSFET - IMPURITY CONTOURS" FILL SCALE DEPLETIO CONTOUR DOPING LOG MIN=16 MAX=20 DEL=.5 COLOR=2 CONTOUR DOPING LOG MIN=-16 MAX=-15 DEL=.5 COLOR=1 LINE=2 PLOT.2D BOUND TITLE=DG-SH-SOI" FILL SCALE DEPLETIO CONTOUR ELECTRON COLOR=2 CONTOUR HOLES COLOR=4 COMMENT Plot surface potential SOLVE V(Source)=0 LOG OUT.FILE=DGSHSP2 SOLVE V(Gate1)=0.25 V(Gate3)=0.25 V(Drain)=1 PLOT.1D POTENTIA CURVE COLOR=1 X.START=0.05 X.END=0.25 Y.START=0.0 + Y.END=0.0 TITLE="FRONT GATE POTENTIAL DISTRIBUTION" + OUT.FILE=DGGAS_SP2.DAT COMMENT Plot electric field PLOT.1D E.FIELD CURVE + X.START=0.05 X.END=0.25 Y.START=0.0 Y.END=0.0

84

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LIST OF PUBLICATIONS 1. “Evidence for suppressed Short-channel effects in deep Submicron Dual-Material Gate (DMG) Partially Depleted SOI MOSFETs – A Two-dimensional Analytical Approach,” To appear in Microelectronic Engineering, 2004. “Analytical Model for the Threshold Voltage of Dual Material Gate (DMG) Partially Depleted SOI MOSFET and Evidence for Reduced Short-channel Effects,” The 7th International Conference on Solid-State and IntegratedCircuit Technology(ICSICT-04), October 18-21, 2004 Beijing, China. “A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET – Twodimensional Analytical Modeling and Simulation,” To appear in IEEE Trans. on Nanotechnology, 2004. “A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET for Nanoscale CMOS design,” International Semiconductor Device Research Symposium (ISDRS), pp.238-239, Washington DC, USA, December 10-12, 2003. “Diminished SCEs in Nanoscale Double-Gate SOI MOSFETs due to Induced Back-Gate Step Potential,” Under Review with IEEE Transactions on Electron Devices, 2004. “Investigation of the Novel Attributes of a Single-Halo Double Gate SOI MOSFET: 2D Simulation Study,” Microelectronics Journal, Vol.35, pp.761-765, September 2004.

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