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LUL2 Dual-band CMOS GPS Receiver

Jongmoon Kim, Sanghyun Cho, Jinho KO

PHYCHIPS Inc. Daejeon Republic of Korea
Tel. +82 42 864 2402
Fax. +82 42 864 2403

Abstract ......... ............................................._.
lbndNl&Eku ..__.

This paper presents the design and implementation of oscodr
LlIL2 dual-hand global positioning system. (GPS)
receiver. The receiver has been implemented in a 1P6M
0.18 um CMOS technology. It consists of a low-noise
pre-amplifier, I-Q mixers, VGA-merged complex BPFs,
2-bit analog-digital converters, and a whole phase-locked
loop synthesizer, excluding loop filter. The measured
-A,,-A. u=mm Ll-m54m&
results show 95-dB maximum gain, 8.5-dB noise figure Fig. 1. The GPS L1L2 band signal spectrum
and -31-dBm IIP3 while consuming 10.6mA from 1.8V
supply voltage.
While many integrated receivers for GPS LI band have
1. Introduction been reported in literature [1-5], no integrated solution
for LUL2 dual-band application has been introduced.
The fundamental Global Positioning System (GPS) This paper presents a new GPS integrated receiver that
technique intends to get accurate positions, velocity, and can receive L1 and L2 signal, sharing all hardware except
time data by using one-way ranging signal from the RF input buffer.
satellites and is being widely used in car navigation
systems, auto-vehicle location systems, intelligent 2. Ctiip Architecture
transport systems, and so on. In the GPS navigational
system, CPS receivers receive satellite positioning signal A block diagram of the LUL2 dual-band GPS receiver
from a set of up to 32 satellites deployed in 12-hour is shown in Fig. 2. The signal processing circuitry
orhits about earth and dispersed in six orbital planes at an consists of two down-conversion stages incorporating
altitude of 10,900 nautical miles. two stages of amplifications. The LliL2 signal is
The GPS ranging signal broadcasting from the received by an active antenna at signal levels down to -
satellites uses two frequencies: a primary signal at 130 dBm and filtered via an associated RF filter to
1575.42-MHz (LI hand) and a secondary signal at remove signals at the image frequency and other strong
1227.6-MHz (L2 band). The signal spectrum of the GPS out-of-hand interference. This signal is then amplified by
signal is shown in Fig. 1. about 21dB and mixed down to first IF of 173.91-MHz
These signals amve at the receiver at a very low- by the first local oscillator signal of 1401.51-MHz (freq,,
power level. By integrating over time a receiver can + freq,, 12) generated by the on-chip phase-locked loop.
exploit the inherent spread-spectrum processing gain of In the receiver of Fig. 2, the first LO frequency is set
the navigation signals to provide positive postcorrelation midway between the L1 and L2 bands, making the two
signal-to-noise ratio. bands images of each other. That is, the RF mixing uses
The L1 signal from each satellite is modulated by two low-side injection for L1 band and high-side injection for
pseudo random codes, the coarse acquisition (CIA) code L2 hand.
and the precision (P) code. The P-code is normally The first IF signal is then down-converted to the
encrypted, with the encrypted version of the P-code second IF signal of 1.279-MHz by the second local
referred to as the Y-code. The L2 signal is modulated by oscillator signal of 175.189-MHz. The first and second
the civil signal (CIS) code and the P-code. L1IL2 dual- local oscillator signals are derived from the frequency
band receivers have the ability to make ionospheric delay synthesizer, which includes a 1401.51-MHz VCO,
calculations from the fact that the propagation speed of dividers and a phase detector on chip. A 10.9493-MHz
L1 and L2 differ with varying ionospheric conditions. reference frequency is required for the PLL. An inverting
Such differences are conventionally used to correct amplifier is provided on chip to support crystal oscillator
ranging information, in order to produce more accurate reference frequency generation. In most applications, the
position fixes. user will need an external source such as temperature
compensated crystal oscillators, to provide greater
frequency stability.

87 0-7803-8480-6/04/$20.00 O Z W IEEE

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Fig. 2. Block diagram of the LIIL2 dual band GPS receiver

The VGA-merged complex Gm-C BPF executes the The RF mixer output couples through 2-pF on-chip
channel selection, the image rejection and variahle gain MiM capacitor to a pair of I and Q double-balanced
amplification process. The BPF comprises a 6'h-order mixers. Each mixer drains a total current of 0.5mA. The
Butterworth filter and provides 2-MHz bandwidth. The 90" phase shifted LO signal is driven by the divide-by-2
VGA provides 75 dB of gain range with a maximum circuit. Due to the high gain in the preceding circuits of
gain of 64 dB. Since the variation of GPS signal levels ahout 32 dB, the second mixer limits receiver linearity.
according to the position of the satellites is not serious, This mixer's 1IP3 is about -0.5 dBm.
the VGA intends to compensate for the effect due to the The RF section measured performances are 44 dB gain,
variation of power supply voltage, temperature, and 7 dB noise figure and -3 1 dBm IIP3.
process variations. The quantizer has a nominal input
T -r
range of 500 mVpp and provides a 2-bit output coded as
Sign (SIGN) and Magnitude (MAG) hits.

3. Chip Design L- O"T+J

The complete analog signal path is implemented,
including the low-noise preamplifier, I-Q mixers, VGA
merged complex BPF, 2-hit analog-digital converters,
and the full phase-locked loop synthesizer, excluding
loop filter. Below, the detailed design choices in the
various sections are described.

A. RF Section
The low-noise preamplifier depicted in Fig. 3 uses a
single-to-differential architecture to eliminate the need of Fig. 3. Simplified schematic of the low-noise pre-
an external balun transformer as well as to achieve good amplifier
supply rejection. A high voltage gain is necessary to
sufficiently reduce the noise conhihution of the B. IF Section
following mixers. In this application, the gain of the low-
noise preamplifier was specified as 21 dB, while the Fig. 4 illustrates a unit cell of the on-chip VGA
requirements for both the noise figure and IIP3 were merged complex Gm-C BPF.
quite moderate, 6 dB and -10 dBm, respectively. After downconversion, the signal is filtered and
The RF mixer itself is a Gilbert-cell double-balanced amplified using a VGA merged complex Gm-C BPF
mixer. The RF signal is fed to the lower devices and the with 75 dB of gain adjusts with a maximum gain of 64-
LO to the upper devices. The RF mixers can he directly dB. It executes the channel selection, the image rejection
driven by the on-chip frequency synthesizer. and variahle gain amplification process. The BPF


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compriscs a 6Ih-order Butterworth filter and provides 2-
MHz bandwidth.
The final stage in the receiver signal path is 2-hit
analog-digital converter. Using a 2-hit converter results
in slightly improved performance compared to that of a
one-bit converter. The quantizer has a nominal input
range of 500 mVpp and provides a &bit output coded as
Sign (SIGN) and Magnitude (MAG) hits. The AGC
feedback loop maintains using a charge-pump controlled
by internal MAG bit duty cycle and an external capacitor.

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Fig. 5. VCO output frequency vs. tuning voltage

4. Experimental Results

I !
- -pp The L l L 2 dual-band GPS receiver is implemented in
a 1P6M 0.18 um CMOS proccss, and a die micrograph is
shown in Fig. 6. The layout consumes 2.6 mm2 include
ESD protection pads. A standard 40-pin MLF package is
- - The entire signal path of the chips is differential
configuration exclude RF pre-amplifier, and careful
(a) Block diagram attention is paid to symmetry throughout the layout. The
RF input is matched with SI 1 better than -25 dB. The
measured voltage gain of the GPS receiver is 95-dB,
with the VGA output signal and the SSB noise figure is
8.5 dB, slightly higher than the simulated 7.4 dB, while
the input third intercept point is -31 dBm. Fig. 8 shows a
measured output spectrum at the BPF output port when -
80 dBm RF signal is applied at the RF input port. This
RF front-end operates over a supply range of 1.5V to
2.5V and temperature range of 4 0 to 90°C. It consumes
19mW from a 1.8V supply at room temperature. A
summary of the most important characteristics of this
LliL2 dual-band GPS receiver is shown in Table I.

(h) Circuit implementation
Fig. 4. Variable gain Gm-C complex filter unit cell

C. Synthesizer
The synthesizer provides two local oscillator
frequencies and master clock signals of the digital
correlator. The frequencies are generated by an on-chip
PLL including VCO, prescalar, phase-frequency detector
and charge-pump. The second-order passive loop filter is
external. All prescalar are composed entirely of divide-
by-2, a fully differential CML circuits. The total current Fig. 6. Die photograph of the LliLZ dual-band GPS
consumption of the synthesizer is 5.5 mA. Fig. 5 shows receiver
measured VCO output frequency vs. tuning voltage.


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100.0 [ I ] G. Montagna, et al. “A 35-mW 3.6-mm2 Fully
Integrated 0.18-um CMOS GPS Radio”, f€€€Jownu/of
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ri 2003
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-9 CMOS’, ISSCC2002 fnfernufiona/So/id-Sfafe
~ Circiiifs
Conjerence,February 2002, Digest of Technical Papers,
>” 40.0
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Receiver Front-End with 40mW Power Consumption”,
0.0 ISSCC2002 - Znfernu/iula/ So/id-Sfufe Circuifs
0.80 0.90 1.00 1.10 1.20 1.30 1.40 Conjerence,February 2002, Digest of Technical Papers,
[4] D. Shaeffer, et al. “A 1 ISmW, 0.5um CMOS GPS
Fig. 7. The receiver voltage gain vs. VGA-ctrl voltage receiver with wide dynamic-range active filter,” f€EE
Journal ojSolid-SfafeCircuit$, vol. 33,no. 12,pp. 2219-
2231, Dec. 1998
[5] F. Piazza et al. “A 1.57-GHz Front-End for Triple
Conversion GPS Receiver,” Z€€EJourna/ of So/id-Sfu/e
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[6] B. W. Parkinson et al. GPS : Theory and Applications
Volume I, A I M , 1996.

Fig. 8. RF signal downconverted by the GPS receiver to

Table I

5. Conclusions
This paper describes the implementation of a complete
L l L 2 dual-hand GPS receiver that includes all necessary
active blocks in the RF and analog signal path, plus a
PLL for LO synthesis.
The final GPS receiver consumes 19 mW from a 1.8 V
power supply and occupies 2.6 mm2 of die area in a 0.18-
um CMOS process. It is packaged in a standard 40-pin


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