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A Differential CMOS Automatic Gain Control

R. G. Bozomitu, VI. Cehan
Faculty of Electronics and Telecommunications, "Gh. Asachi" Technical University
Carol I No. 11 Av., 700506, Ia,i, Romania
Phone: +40-232-213737, bozomitu(, v1cehanAetctuiasiro
Abstract - In this paper, a differential CMOS automatic gain The envelopes of the two alternations of the input signal are
control amplifier is presented. The proposed architecture uses a added and inverted and the resulted low frequency voltage
differential variable gain amplifier, implemented with a Gilbert signal is used in the feedback loop to control the VGA. Thus a
cell and provides an automatic gain control amplifier for both
alternations of the input signal. It yields almost 20 dB dynamic ignalmwith aota magnitd is p ed The VGA
range of input 100 MHz sinusoidal signal and provides a constant
differential output of 200 mVpp with AGC loop bandwidth of
plemen wi differential Gilbet cell. th popsed
VGA provides two differential output currents with constant
lMHz. The power consumption is 50 mW from a single 3.3 V magnitude. For an optimal operating of the voltage mode peak
voltage supply. detectors, the two differential currents provided by the VGA
are converted in two differential voltages having a constant dc
I. INTRODUCTION level of 1.5V.
The method's principle of the proposed AGC architecture
The automatic gain control (AGC) amplifier and limiting has been confirmed by system level simulations.
amplifier are the two post-amplifier techniques for maintaining
constant output signal amplitude against the input signal II. CIRCUIT DESCRIPTION
The different types of AGC are presented in literature [1] - A. Variable Gain Amplifier
[4]. VGA is an amplifier stage whose gain can be adjusted using
We introduce in this paper a compact differential CMOS the information provided by the feedback loop. There are three
automatic gain control amplifier which can be found in basic types of VGA's that are applicable in AGC: linear,
numerous applications in communications systems and exponential, and polynomial [1]. The exponential type is
audio/video analog signal-processing circuits. widely used because of its wider dynamic range [1].
The block diagram of the proposed circuit is presented in In our design a VGA implemented by a differential Gilbert
Fig. 1. It is composed of a forward path and a feedback path. In cell is used.
the forward path, the variable gain amplifier (VGA) is In Fig. 2, the electric scheme of the proposed variable gain
controlled by a feedback low frequency path and the output amplifier is shown.
differential currents given by VGA are transformed into VDD
voltages using a differential current to voltage converter. The
AGC feedback path circuits shown in Fig. 1 include two peak lo .l
detectors (for both alternations of the input signal) and an - Current mirrors
inverter summing amplifier. 65 46


current to \,oltage V0 l
IM4<1:32> M5<1:32> r NMOS GND
7 V1- \ 2+ V2- P. conmerter _ 0
° 1
LI1 W=10u W=10u
+ Vdcl Vdc2 + Vcm A V1In L=400n L=400n L=400n L=400n
M1<1:32> 12 M2<1:32>
ui vet RV1+11 cv Pek deecto 0V2+ NMOS GND NMOS
|| F1 W= lou W= lou
X Vin2 L = 400n RO L = 400n

R3 R 2 VOfr, 0
V 2- 25

R3 R2 Vtrl6:k-~~2 -

Figureh1.eBlock dara
of the atern i iproposedA

1 -4244-0969-1/07/$25.OO ©C2007 IEEE.

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The operating of the proposed VGA is described in FVO-VCM+ +
following. n 0 0 (6)
First, the situation when resistor Ro is not present (1R = 0) Vo = VCM + VO
in the electric scheme shown in Fig. 2 is analyzed. In this case where
a single bias current, having the Ibias value, is used. VCM = 1.5V (7)
The currents through transistors Ml and M2 can be written: and
,1= 2+ bIas4u,
1 (~A4
in2 (V2
bias V+=i+
0 0
Rconvy V=U.i-R
0 0 conv (8)
2 4r (Lj2 lV2 08 (SW Ain2 Rconv

,bias __ AV 41 i2 V + Vc
24 L.) 2
'"Cox ) OPAMP diff -1.5V

The dynamic ranges of the two differential input signals .- -
pairs for which the relation between current and voltage can be
considered linear, can be written:
°V R v

ias bias
Figure 3. Differential current to voltage converter
JAVin I(<< 2 |AV 2 (2) By using equations (5), the two differential output voltages
IIOX L L 92 signals from (8) can be written:
The dynamic range of the proposed VGA will be studied in
section III.

1Vijn21lCOXR'" r L rL
L L~)
If the relations (2) are fulfilled, the equations (1) become: =- -= W2A J/'24uC0C n ) ()
,=bias +-V" I21
1 2 2 in is
C. Peak Detector Circuit
I_ bias
-2 2 in2 __AVi2 biasf OX L ) IIasCox areInshown.
Fig. 4, the electric schemes of both peak detectors circuits
2htoiferntaotptuens notedtwaUsing
the peaksinl
detectors from Fig. 4, the envelopes of the
The two differential output currents, noted i3s and i46 in Fig. difreta +/0 an 7aeotand hs w
2 can be expressed as:
2 can beexpressed
as: ~~~~two differential signals VO+ and Vo- are obtained. These two
* wV are noted Vpeakthese
|5[ + envelopes
W p and Vpeak n in Fig. 1. To obtain the
s bias
2 + AVin'AVi 1CO J control voltage of AGC, signals are low-pass filtered, by
2 4 L I n L 2 (4) using simple RC filters. In this way the V ,+, and V-l, low
,bias _w AVAV
w frequency signals are obtained. Finally, the differential low
'46 - in' in2PC ox A
L,), L frequency control voltage (Vct,) of the VGA circuit is obtained
2 4~~~~~~~~~~~~~~~
The two differential output currents of the VGA circuit can by summing and inverting of the V+, and V-, low frequency
be written: signals.
35 -146 =2
~~~AJjnjAiAJj2fCox . (~~~~~~w
)1L)2 L
(w v UI O MP +
Ii (w~~~~~(w~1 (5)

equations (5), (WIL), and (W/L)2 represent the aspect
In Vpeak Ypeak n
ratio of the transistors M3, M4, M5, M6 and MI, M2, CT Idischl C2 \ Idisch2
B. Differential Current to Voltage Converter
In Fig. 3, the electric scheme of the differential current to a) b)
voltage converter is presented.
The two differential output voltages provided by the circuit Figure 4. Peak detectors electric schemes:
shw in Fi.3cnbewitn a) for positive alternation; b) for negative alternation

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D. Inverter Summing Amplifier For better performances of the proposed AGC, the dynamic
The electric scheme of the inverter summing amplifier is range of VGA has to be as higher as possible. In order to
shown in Fig. 1. This circuit is built by using Uin, operational increase the dynamic range of the VGA, the differential pair
amplifier and R1, R2, R3 resistors from Fig. 1. formed by the transistors M1 and M2 is degenerated with the RO
The output control voltage provided by the inverter summing resistor shown in Fig. 2. In this case, the differential input
amplifier presented in Fig. 1 can be written: voltage signal V1M2 is copied over the series impedance of the
J?3 + R3 two nonlinear transconductances gn and the linear degeneration
VC,r VCM+ sVet - R tVr, R *tl

resistor Ro resulting in a differential signal current io given by

1 2 [6]:
where [6]:
Ri = R2 = R3 =lOkQ ( 1) ioV2/[Ro+2g] (19)
So th controlvoltageofthesecondinputofGilbertcellcan According to equation (19) results that the gain of the
be written: proposed VGA decreases when the series resistor
increased. Thus, for better performances, a trade off between
RO is
VMK2 =Vl -VCM =Vset -(VA, +VJri) (12) dynamic range and gain has to be considered in the VGA
For the ideal operation of the AGC loop, the magnitude of designing.
V0+ and V- differential signals are equal to Vs,t signal which is forIndifferent
Fig. 5.b) the dc characteristic of proposed VGA is plotted
referred to VCM
to dc level. Thus, the desired magnitude of the
dc level. Thus, the desired magnitude of the is V1M2=50mV. values of RO (25Q - 250Q), when control voltage
For low values of the RO resistor, the gain of the
differential signals provided by the AGC loop can be VGA is significantly increased. But, for a bigger gain of the
prescribed by Vset signal. VGA, the closed-loop AGC operation can become instable. On
So, for the ideal operation of the proposed AGC loop, one the other hand, for high values of the RO resistor, the dynamic
range of the VGA is increased. In our design the value of the
Vctrl = Vctrl = o (13) RO resistor (RO = 252 ) has been chosen taken into account the
By using equations (11) and (13), the relation (10) becomes: observations above.
Vctri VCM + Vset (14)
and (12) can be expressed as: DCVin2-lm D
j; Vin2=7Xm
; \in2:-<rn *; Vin2=R1rom
i.2 = Vctrl VCM Vset
= AV = v -v = V
2,0m y;~ ~ ~ ~Vin2 ~ ~v W00m
~ ~ ~VI ~i; Vin2 70rn -;Vin2_40rn
s. VinZ=10m

Thus, the proposed AGC loop provides two differential output v,,2=1OOmV'. <
voltages having the magnitude equal to Vset signal. 1.0,7
It is important to note that the equation (12) is precise as long
as the loop has a greater gain. t -
So, the proposed circuit provides an automatic gain control
amplifier for both alternations of the input signal. This is a very Vin2=10M___
important issue for many applications in communications.
The gain of the AGC loop forward path can be written:
AO =Gm Rov (16)
__2_ ._._._._._...
1-10lrn 1nm n
where a)
DC Response
G G- iV C./ w w 7 i ,,; ,< tR.025
2-IAijxCI |) (17) v; RO=250
R!2m R- 250
a; RO175
kR!0=175 RO=1
-:R-;~ 100
R.; S"
w 1 2 .i-_Ro=25f2T
represents the transconductance of the Gilbert cell, used as
VGA, if relations (2) are fulfilled and R,on, is the conversion _____________
resistor of the circuit shown in Fig. 3.
By using (17) in (16), the gain of the AGC loop forward path R0=250Q
A00 Gm Rconv
o IV2in2 R,1IpCJ2(18)
2 L LVinL
conv ox

_3 00n -1 ECrn 1 OOrn 3 Oorn
Figure 5. DC characteristic of the Gilbert cell used as VGA
First, the dynamic range of the VGA, implemented with the a) R0=25Q, Vin2=1OmV-1OOmV;
Gilbert cell shown in Fig. 2 is analyzed. b) V-2=5OmV, R0=25Q-250Q
In Fig. 5.a) the dc characteristic of proposed VGA is plotted
for different values of V1"2 (lOmV-lOOmV). It is obvious from In Fig. 6 the close-loop AGC operation is illustrated, when a
Fig. 5.a) that the transconductance of Gilbert cell depends on sinusoidal 100mVpp, 100MHz input signal modulated with m =
the value of the control voltage V1"2, as equation (17) shows. 0.5 by a low-frequency of 1MHz noise is applied.

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Transient Response signal with a frequency of 100MHz and magnitude variable in
2- 50 Vin a 15mV - 1 OOmV range. The transient regime shown detailed
2.45 jl in Fig. 7 is de test signal wich has a very smal rise/fal time
> 2,41b J (50ps) for each step. According to simulations results shown in
2 35 lPi Uh IUIWPRg Fig. 7, the differential output signal is kept constant at
20Lniv6 ±
- v~-) a)
z2m00Vpp. The frequency operation of the proposed AGC
depends by time constant of peak detector (controlled by the
200r+ :discharging current) and time constants of the low-pass filters.
1 0;m The main limitations of the proposed AGC are represented
0;a I I I J 1X by the dynamic ranges of peak detector and Gilbert cell. The
-11Xl value of AGC dynamic range is given by peak
detector used which cannot operate properly with magnitude
values less than 15mV. On the other hand, the maximum

150 v6tr 4- vctr magnitude value is limited by the nonlinear characteristic of
1 5kl Gilbert cell for value bigger than 100mV. According to these
> 1i50 observations and simulations results, the dynamic range of the
1 45 ~ proposed AGC input signal, for which the output signal varies
4A0 ., i.i
| ........
only with 3dB, is about l5mV - IOOmV, which means 17dB.
v; o Vpe3kln c) The simulations confirm that the distortions introduced by
1M o; 6tri- o; 6trlthe proposed circuit can be neglected, the differential output
_5_ signal having the total harmonic distortion, THD < 1%.
> 1 50 It is important to note that the proposed architecture operates
1A,5 U--X
L ge > _ t w w Jll Wdifferentially, providing an automatic gain control amplifier for
1.40 both alternations of the input signal. Thus, the control voltage
t1 .g2612
400n1T 9XX1g 40n
tilme ( 3 }
1 skj
of the VGA has information from both alternations of the input
signal and the differential output signal magnitude is kept
Figure 6. AGC waveforms for Vset=5OmV: a) input signal, Vi,1; b) differential
output signal (200mVpp); c) output signal positive alternation (1OOmVpp) and constant more efficiently than for other AGC architecture
positive alternation control voltage V,,, ; d) output signal negative alternation presented in literature.
(1 OOmVpp) and negative alternation control voltage VC,r IV. CONCLUSIONS
1.650 A :ctrl
In this paper a new differential CMOS automatic gain
1.575 control amplifier has been presented.
1.50t The proposed architecture uses a differential variable gain
1425 amplifier implemented with a Gilbert cell and provides an
automatic gain control amplifier for both alternations of the
1,X50 input signal. Thus, the control voltage of the VGA is given by
1.640v Vc;tri a) both alternations of the input signal and the output signal
J.LL/0 magnitude is kept constant more efficiently than for other AGC
1580 The proposed architecture yields a constant differential
1550 F + \ /L output magnitude of 200mVpp for an input signal having almost
20 dB dynamic range.
1520 The simulations made in a 0.13 pim CMOS technology
200m Vb-0
V+ Vo- confirm the theoretical results.
120mE [ L ; _ L REFERENCES
[1] Chorng-Kuang Wang and Po-Chiun Huang, "An Automatic Gain Control
-1 r Architecture for SONET OC-3 VLSI", IEEE Trans. Circuits Syst. II, vol.
E200n aIll 44, no. 9, pp. 779-783, Sept. 1997;
[2] Po-Chiun Huang, Chen-Yi Huang, and Chorng-Kuang Wang, "A 155-
-0,0 55u
2.56 F . 25u 1L
MHz BiCMOS Automatic Gain Control Amplifier", IEEE Trans.
time (s) c)
Figure 7. AGC waveforms for an input signal with variable magnitude in a Circuits Syst. II, vol. 46, no. 5, pp. 643-647, May 1999;
Vi, = 15mV - lOOmV range; a) variable input signal and control [3] Ali Motamed, Changku Hwang, and Mohammed Ismail, "A Low-Voltage
Low-Power Wide-Range CMOS Variable Gain Amplifier", IEEE Trans.
voltage; b) control voltage; c) differential output signal (~200mVpp) Circuits Syst. II, vol. 45, no. 7, pp. 800-811, July 1998;
The magnitude of the AGC differential output signals is still [4] Alfi1o Zanchi, Carlo Samori, Salvatore Levantino, and Andrea L. Lacaita,
2-V 2.5-GHz - 104-dBc/Hz at 100kHz Fully Integrated VCO with
constant (~.200mVpp), like the outputs shown in Fig. 6. In Fig. 7 ~ "A
Wide-Band Low-Noise Automatic Control Loop", IEEE J. Solid-State
the operation of the proposed AGC is illustrated for an input Circuits, vol. 36, no. 4, pp. 611-619, April 2001.

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