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Fast Automatic Gain Control Employing Two Compensation

Loop for High Throughput MIMO-OFDM Receivers
I1-Gu Lee, Jungbo Son, Eunyoung Choi and Sok-Kyu Lee
Next Generation Wireless LAN Research Team, ETRI
161 Gajeong-dong Yuseong-gu Daejeon, 305-700, KOREA
Tel: +82-42-860-1633, Fax: +82-42-860-6732

Abstract- The performance of a receiver front-end limits the of the AGC circuit. Moreover, it can be used to dynamically
quality and range of the given communication link. An control the gain of the received signal for MIMO-OFDM
appropriate design based on well-defined system parameters and systems with large variations in received signal power caused
architecture can make a huge difference in the performance, cost by multi-path fading with time and frequency offset.
and marketability of the entire system. In particular, there is a The remainder of this paper is organized as follows. In
need for improved digital Automatic Gain Control (AGC) for Section II, the frame model is given for next generation
use in Multi Input Multi Output Orthogonal Frequency Division
Multiplexing (MIMO-OFDM) systems with application to
Sess II, the overadl receiver nect is
wireless LANs, and the overall receiver architecture is
Wireless Local Area Networks (WLANs), targeted for the presented in Section III. A detailed description for each sub-
upcoming 802.11n standard [11, [2]. In this paper, we propose an block is then provided in their respective sections: Automatic
efficient algorithm and implementation of the digital AGC for Gain Control in Section IV; carrier sensing block in Section
next generation WLANs. The proposed AGC algorithm has two V; and digital amplifier in Section VI. In Section VII, the
feedback loops for gain control to improve convergence speed, performance of the proposed design is shown. Finally, we
and at the same time maintains the stability of the AGC circuit. conclude in Section VIII.
Also, a complete set of parameters for practical implementation
is obtained by various experiments with fixed point constraints
and accuracy requirements. II. FRAME MODEL
The next generation WLAN is a packet-based high-
I. INTRODUCTION throughput MIMO-OFDM system in the 5GHz band. Figs. 1
AGC circuits are employed in many systems where the and 2 show the packet structure of next generation WLAN as
level of an incoming signal can vary over a wide dynamic specified by [1] and [2]. Each packet contains a header for
range. In high data rate digital communication systems, and detection, channel estimation and synchronization. This
especially in burst packet switched systems such as WLANs, preamble is known at both sides of the communication link.
the start of each packet introduces a large signal variation. To The legacy OFDM packet preamble consists of 10 identical
demodulate a received signal with an improved signal-to- short OFDM training symbols t, i=1, 2, ... , 10, each of which
noise ratio, AGC can be used to hold the average power of the contains 16 samples; and two identical long OFDM symbols
baseband signal close to a desired level. AGC implementation Ti, i=1, 2, each of which contains 64 samples as in the IEEE
of high-throughput MIMO-OFDM applications to next 802.1 la. For MIMO-OFDM mode, two long OFDM symbols
generation WLANs is important to ensuring achievable Ti, i=3, 4, are transmitted after the signal field for providing
operating SNR at the receiver and, consequently, achievable channel measurement capability. The short training symbols
data rates. are intended for signal detection, automatic gain control,
There have been several research contributions that provide diversity, coarse acquisition, and frequency synchronization
automatic gain control algorithms and present implementation purposes. In order to ensure timely gain control for the
issues. In [3] and [4], the authors present the implementation received signal and provide reliable transmission with stable
of a simple digital automatic gain control architecture gain, a receiver designer can use the short preamble to adjust
targeting the IEEE 802.1 la standard. The authors of [3] the strength of the received signal to an optimum level within
propose a simple multi-stop AGC scheme. In [4], an AGC the dynamic range of various signal processing components in
interface with a synchronization scheme based on double the received signal path.
auto-correlation is proposed. In those papers, the theoretical OFOMp~~~~bI~
p~~~k~t OFMDTfiI
3.2=8us j=0.83.2=fied =4us,>
problem is analyzed and simulation results are provided 1 OxD8usM8 1.6 2x 0.83.2
without considering implementation constraints in detail. 11

In this paper, the proposed architecture includes a large t2 (4 (5 t6 (7 (9 jtGI2; TI T\ SIGNAL) OsFDM

gain update loop and a small gain update loop to improve
convergence speed and at the same time maintain the stability Fig. 1. The packet structure ofthe Legacy OFDM mode

0-7803-9390-2/06/$20.00 ©)2006 IEEE 5459 ISCAS 2006

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0.8 DMpacketpreamble~
OFDM packet preable
MIMO-OFDM- preable
in the bit-reversed order, which is fed into the MIMO detector
E. 2=8t
<____________________________________>i'2) j4
[2], which uses the zero-forcing (ZF) method.
10 x0.8=8us 1 62
6 x3.2=8us 08 +3.2 =4us +3.2)x 2=8us

t2l t3~ 4l t5 t6 l.t7 it8 tt9iYG2 Tl k T3

1,08 + 32.=4us

GI T4 symbol i symbol\
Fig. 2. The packet structure of the MIMO-OFDM mode
From Cr + - r s

Dgt > e st MIIQ AMP B*9'WUF FFT Wi_'

antenna 2 a -eg ,
2 Digit~I IC CEOmph~

Fig. 4. State digram of AGC block
Fig. 3. The front-end architecture of dual-band MIMO-OFDM receiver Teapiueo h eevdsga
sajse h ota
with 3 antennasT
dynamic range of the ADC can be fully utilized. The state
The long training symbols are designed to be used for transition diagram implemented physically for the AGC is
channel estimation and fine frequency offset correction. The shownin Fig. 4. The AGC block state is changed t the idle
signal field includes information for parity, length and rate, state from whatever state the AGC is in when the AGC block
etc. There is a short guard interval (GI) and a long guard enable (agc_en) is deactivated. The first state is a power
interval (GI2) that consist of 32 or 64 data samples for the measurement state (MSR), which determines whether the
long legacy-OFDM training symbol and the long MIMO- peak signal is within the dynamic range of ADC before
OFDM training symbol, respectively. In the OFDM data field, adjusting the amplifier gain. As shown in Fig. 5, the signal
four subcarriers are inserted as pilots into positions -21, -7, 7, power is measured by accumulating the absolute real (in-
and 21 for each band. The total number of subcarriers is 52 phase) and imaginary (quadrature-phase) components of each
and 104 in single and dual band mode, respectively. antenna. The power of the input signal is measured for
0.8usec (32 samples at 40MHz sampling). Out of the two
III. RECEIVER ARCHITECTURE estimated signal powers, the larger one is selected for gain
The overall receiver block diagram is shown in Fig. 3. The update. The chosen signal power is converted to a log-scale
three received signals from 3 antennas are fed into digital value. It is possible to reduce the range of values by taking
amplifiers to adjust the power of the incoming signals to the log scale for the signal power. If the measured power is out of
target value. The digital front end operations are applied to the dynamic range of ADC (ADC saturation) during this
only the two received signals out of the 3 available paths to power measurement period, the power measurement is
reduce implementation complexity. The power of the input stopped and AGC makes a coarse adjustment with the large
signal is measured and gain update is calculated in the AGC gain update state (Update L) to speed up gain adjustment
block. The digital amplifier output is monitored to detect if with the large gain control value. The amplifier gain is
the signal is large or not for the carrier sensing purpose. The reduced right away by the amount of the register programmed
DC offset and I/Q imbalance that come from RF components value (agc_gainl) in order to speed up convergence. The gain
and ADC are compensated in each signal path. The received step is fixed to 3dB. The gain update due to ADC saturation is
signals are directed to a channel mixer for +10 and -IOMHz conducted only when ADC saturation is observed during the
frequency shifting. The input OFDM symbol is buffered into signal power measurement period. If ADC is not saturated
the FFT input buffer, and the Carrier Frequency Offset (CFO) during the power measurement period, the measured power is
is corrected at the input of the FFT. The frequency and phase compared to a reference power to calculate an error signal,
errors are estimated and corrected by using the pilot tones in and the magnitude of the error signal is compared to a
the phase tracking block. The CFO estimation, frame reference value in a small gain update state (Update_S). By
synchronization and band detection are performed by an auto- comparing the measured log-scale power with the target
correlation result of short and long preambles. After the power that can be selected to maximize the signal to noise
synchronization process is done, the CFO compensated ratio and minimize saturation effects. If the measured power
packets are transformed to the frequency domain by a 128- (agc_pwr log) is smaller than the target power (agc_vref),
point radix-23 DIF FFT block. The output of FFT is the data which is a programmable register, then the gain is adjusted so
that the signal power is equal to the target power given by the


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k D
-13,.;-~ ~ MUX cth-sa
register value after the signal is settled down for the gain
change. If the measured signal power is larger than the target
power, then the gain is reduced even more given the
agc gains, which is register programmable. This additional
gain suppression will speed up the gain adjustment and
prevent saturation when the received signal is large. Once the
amplifier gain is updated, the AGC block waits for a register
programmed time period (agc_delay) in wait state. This
register value should be sufficiently large so that the signal is
well settled down to the gain change. The Wait cont and
Wait_last state are the wait states of the continued gain
control process and the last gain control, respectively. After
the waiting period, the signal power measurement and gain
update is repeated until the measured power is smaller than
the target power and gain is updated accordingly. The initial
gain is given by the programmable register (agc_ginit).

Fig. 5.

The digital amplifier is used to scale the incoming signal


Block diagram of AGc

power either by amplifying or attenuating and adjusts it to the
target power specified in a programmable register according
to the current gain state. The digital amplifier includes a gain
state unit that stores the selected gain state for processing of a
received packet. The gain state unit begins with the highest
gain state to ensure the lowest power signals can be detected
and processed. The same amount of gain adjustment is
applied to the two received signal paths. The implementation
- M UX
the reliability of detecting the ADC saturation, 16 consecutive
samples at 40MHz sampling are used. Consider one signal
component that is a real component from antenna 0. If the
number of ADC output sample whose absolute value is larger
than a certain threshold (cs th sat, 500) is larger than or equal
to a register programmable value (cs_th_cnt_sat, 4), then we
flag that the ADC is saturated. Any one of the 4 signal
components (real and imaginary components from the two
antennas) can flag the ADC saturation. A block diagram is
shown in Fig. 7.

S +
. S t+ -

thD 21og()

Fig. 7.
D gsat

6 btshiftist

_ v _ _ _ sat__ton

Block diagram of carrier sensing

We apply a 50ns RI\MS delay spread channel model. As
well, RF impairments, a RAPP power amplifier with 10dB
backoff and phase noise with a pole-zero model, are included.
There can be a residual frequency error caused by frequency
instabilities in the oscillators at the transmitter and receiver.
All simulation cases have time/frequency offset, introduced
by an analog-to-digital converter (ADC). Packet size is fixed
to 1K bytes. Simulation modes are fixed to 36Mbps and
54Mbps, employing the QPSK, 16-QAM and 64-QAM
modulation schemes, which all employ the dual band with
MIMO technique. Therefore, the actual data rate is 72Mbps,
144Mbps and 216Mbps, respectively.
+ --- QPSK,Oppm, FX

of the digital amplifier is simplified by utilizing this coarse > -O64-QAM, OppmFX
gain step as shown in Fig. 6. The amount of gain update is A 16-QAM, 20ppm,FX
divided into 6dB and 3dB steps. The 6dB step gain update is 5A[ QPSK,40ppm,FX
firstly applied to the incoming signal and then the 3dB step X
X QPSK,40ppPm
64-QAM, 40pp~m FX
gain adjustment is conducted. When the9 gain control value is 0.1 ...
the same as the AGC reference value, there is no gain L+
20 (=g_ii)Input X

dgain ¾ A

X +3 <15> ,17W1-|,^
3 19 21 23 25 27 29
mux output ~~~~~~~~~~~~~~~~~~~SNR (dB)

Fig. 8. Modulation schemes vs. PER

3 __11-0
m ux 2 The simulated PER using different modulation schemes is
plotted in Fig. 8. FL and FX refer to the simulated result of
Fig. 6. Block diagram of digital amplifier floating point version and fixed point version, respectively.
Although most modulation schemes of fixed point have
VI. CARRIER SENSE BY MONITORING ADC SATURATION similar performance with floating point, a performance gap
due to quantization error is apparent when a 16-QAM and 64-
The existence of the incoming signal is detected by QAM modulation scheme is utilized, resulting in 0.3 and
monitoring whether the ADC is saturated or not. To improve 0.7dB SNR loss at PER 10%o, respectively. We show that the


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proposed algorithms and their implementation are effective controlled input signal level at the same time, as shown in Fig.
for multi-path fading channel with a 50ns rms delay spread 10 and simulated at 27dB with 1000 packets, 64-QAM and
and 40 ppm time/frequency offset in Fig. 8. As well as the R=3/4. The large gain update loop quickly brings the received
known constraint, it requires about 10% PER at 28dB SNR. signal to the desired range. The small gain update loop
Considering the tradeoff between the implementation gradually smoothes the received signal to avoid saturation on
complexity and the performance, our proposed algorithms and the AD converter and speeds-up convergence of the input
their implementation stand as a good compromised solution signal level.
agc_gainl agc_gains # of Update L # of Update_S PER[%]
1 ~~~ ~~0
__- 1 20 209 18.4
____I - 0 1 728 16.1
I____ 1 4 648 -13.3
6 4 4 608 12.7
12 8 8 589 12.7
18 - 12 4 721 -24.6
\4 X X a:\ input signal level of s igital amp vs. time

0.01 2000 2500 3000 3500 4000 4500 5000 5500
17 19 21 23 25
SNR (dB) output signal level of digital amp vs. time

Fig. 9. AGC reference value (agc vref) adjustment
In Fig. 9, the target signal amplitude is adjusted through <
simulation under 16-QAM and R=3/4. The agc_vref is the _ _ _ _ _ _ _
target signal amplitude after AGC is done in terms of the 3dB 2000 2500 3000 3500 4000 4500 5000 5500
step. For example, agc_vref=13 corresponds to the target
signal amplitude of 2A(13/2). We found that the receiver Fig. 10. Input/output signal level of digital amplifier
performance is improved by using different settings for signal
band use and dual band use, as shown in Table I. As shown in VIII. CONCLUSIONS
Table II, the agc_gainl and agc_gains register values are set
considering the PER result, and the range of the input signal In this paper, the proposed AGC circuit is designed to
power and the number of updates since the AGC should be adjust the strength of the received signal to a near constant
finished well before the end of the short preamble. The optimum power level within the dynamic range of various
agc_init is the initial gain setting. If the signal needs to be signal processing components in the received signal path. It
amplified, the gain will be increased up to the maximum. If includes a large gain update loop and a small gain update loop
the signal is large and needs to be suppressed, the gain will be to improve convergence speed and at the same time maintain
reduced up to 0. When the agc_ginit is 20, the maximum the stability of the AGC circuit. Moreover, it can be used to
signal suppression will be 20x3=60dB for 3dB gain control dynamically control the gain of the received signal with large
and the maximum signal amplification is (32-20)x3=36dB. variations caused by multi-path fading with time and
The initial gain should be set high enough to suppress the frequency offset in order to ensure timely gain control for the
signal. In this example of agc_ginit=20, there is 60dB room to received signal and provide reliable transmission with stable
suppress the signal. Simulation parameters for the AGC gain.
register setting are shown in Table I.
AGC registers Values [1] Heejung Yu, et. al., "IEEE 802.11 Wireless LANs ETRI
agc delay 32 proposal specification for IEEE 802.11 TGn," IEEE 802.11
age_gainl 12 document, doc. No. 1 1-04-0923-00-OOOn, August, 2004.
agc_gains 8 [2] H.Yu, T.Jeon and S.Lee, "Design of Dual-Band MIMO-OFDM
agcginit 20 System for Next Generation Wireless LAN," IEEE
agc vref 13 (dual band use) / 10 (single band use) International Conference on Communications (ICC), May. 2005.
[3] Jimenez, V.P.G., Garcia, M.J.F.-G., Serrano, F.J.G. and Armada,
Faster convergence of a receiver's AGC circuit reduces the A.G, "Design and implementation of synchronization and AGC
time required to bring a received signal within the operating for OFDM-based WLAN receivers," Consumer Electronics,
range of ADC. The proposed digital AGC circuit includes a IEEE Trans. on Vol.50, Issue 4, pp. 1016-1025, Nov. 2004.
large gain update loop and a small gain update loop to [4] Fort, A., and Eberle, W., "Synchronization and AGC proposal
improve convergence speed and maintain stability of the for IEEE 802.1 la burst OFDM systems," GLOBECOM, Vol.3,
pp.1335-1338, Dec. 2003.


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