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You are on page 1of 4

Automatic Gain Control Circuit

**Hsuan-Yu Marcus Pan and Lawrence E. Larson
**

University of California, San Diego

9500 Gilman Drive

La Jolla, CA, 92093, USA

hspan@ucsd.edu

**Abstract—An improved exact dynamic model of a fast-settling
**

linear-in-dB Automatic Gain Control (AGC) circuit is proposed. II. AGC CIRCUIT OPERATION AND FIRST-ORDER STEADY-STATE

The explicit transient behavior is calculated for a first-order and LARGE SIGNAL MODELING

second-order AGC loop.

A. First-order Steady-state Large-signal Model

I. Introduction

The first-order basic AGC loop is shown in Fig.1. According

Automatic Gain Control (AGC) circuits are used in many to the linear-in-dB operation of the VGA, the output of the

systems, where the input amplitude varies over a wide dynamic VGA can be expressed as:

range and the output amplitude is designed to achieve a certain

specified level. An AGC circuit is usually composed of a peak Vout = Vin × α × eVctrl /VT (1)

detector (PD), a variable gain amplifier (VGA), and a loop filter,

as shown in Fig.1 [1]. The output of the VGA is detected by the where α is the VGA gain when the control voltage Vctrl is zero,

peak detector, and compared with a reference voltage Vref. Since and VT is the constant representing the linear-in-dB slope.

the gain of the VGA is adjusted according to the amplitude of the As an example, suppose an envelope-modulated signal is fed

input, the resulting output amplitude is constant. to the input of the VGA, Vin can be written as

AGC circuits can be categorized according to different gain Vin = A (1 + m cos ωe t ) cos ωc t (2)

characteristics of the VGA. One of the most popular types is the

“Linear-in-dB” VGA, whose gain control has an exponential where m is the modulation index of the envelope-modulated

characteristic [2]. As a result of this characteristic, an exact signal, ω e is the envelope angular frequency and ω c is the

analysis of the large-signal settling behavior of the Linear-in-dB

circuit is very difficult. Previous authors have used a Taylor carrier angular frequency [7, 8].

series expansion to approximate the exponential function in the Based on peak extraction operation, the output of the peak

overall loop analysis [1, 3-4], which is only valid for small input detector Vpd can be expressed as

level variations. One important use of this VGA is as a feedback

control element for a wideband polar transmitter [5-6]. These

circuits require a very wide dynamic range for their operation

and therefore an exact analysis of the settling behavior of the Vout

Vin

Linear-in-dB VGA is needed. VGA

**In light of this, we present an exact dynamic large-signal
**

model of a linear-in-dB AGC circuit. Our proposed model is Peak

Detector

capable of describing the entire loop large-signal behavior, and

exactly predicts the overall loop settling time dependence on

input amplitude variations. Vpd

Vctrl

Gm

The paper is organized as follows: Section II reviews the Vref

AGC loop operation and derives the first-order exact steady-state C

**large signal model. Section III generalizes the analysis to a
**

second-order response. Section IV derives the settling time of the

Fig.1. Basic AGC circuit block diagram. The gain of VGA is adjusted

overall loop. Section V compares the calculated settling time according to the amplitude of Vin to hold Vout at constant-amplitude.

results with behavioral simulation results. Conclusions are

provided in Section VI.

**1-4244-0921-7/07 $25.00 © 2007 IEEE.
**

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V pd = Peak (Vout ) (3) If ω e is relatively small when compared with ω gmVref / VT , the

where Peak( ) is the peak extraction function. The output of the envelope of Vout,ss1 can be approximated to Vref (steady-state

gm-C filter, which acts as a loop filter, can also be described as value), which means the overall AGC can settle within a very

short time. If ω e is large, (9) implies that the AGC cannot keep

t

1 (4) the output amplitude constant.

Vctrl = ∫ g m (Vref −Vpd )dt

C −∞

where Vctrl is integrated from the error term Vref-Vpd. II. AGC CIRCUIT SECOND-ORDER LARGE SIGNAL MODEL

Combining (1)-(4), we have A. Peak Detector Delay Model

dVctrl g m (5) The analysis in the previous section was concerned only with

= (Vref − A (1 + m cos ω et ) × α × eVctrl / VT ) the first-order (single-pole) approximation, where the pole is

dt C

only determined by the gm-C filter and there are no delays

Equation (5) describes the transient behavior of Vctrl of the anywhere else in the circuit. However, as the input frequency

first-order AGC circuit. It is a nonlinear first-order differential increases, other poles in the circuit become more important [10].

equation and is difficult to solve directly. However, (5) can be Therefore, a second-order large-signal model is proposed here,

simplified by substituting u = eVctrl / VT and then: which takes into account the other poles associated with the peak

detector.

1 du g m Vref 1 g A × α (1 + m cos ωet ) (6)

− =− m Consider the peak detector delay model in Fig. 2, where the

u 2 dt C VT u C VT

input signal is A cos(ω t ) and ω p is the angular frequency of the

Equation (6) is known as the Bernoulli Equation [9] and can

be solved as associated pole. In steady state, the output of the peak detector

delay block, Vdout(t), can be calculated by the Inverse Laplace

−1

Transform of Vdout(s) as follows:

ωgmVref

(7)

ω A × α m cos(ωet − φ ) Aα − t Aω p ω (10)

u = gm + + Pe VT Vdout (t ) = cos(ωt − ϕd ),φd = tan−1 ( )

VT ω V Vref

2

ω + ωp

2 2 ωp

ωe2 + gm ref

VT

g m and P is the integration constant. B. Second-order Steady-state Behavior

where φ = tan −1 CVT ωe , ω =

gm

C If we insert the above delay block between the output of the

g mVref

PD and the input to gm-C filter to model the delay associated

Finally, the control voltage Vctrl can be obtained by applying with the PD, as shown in Fig. 3, the input of gm-C filter can be

Vctrl = VT ln u and solved explicitly as calculated by combining (2) and (3), and be re-written as

mω p cos(ωet − ϕd )

(11)

Vgmc = Aα evctrl / VT u (t ) − e p +

−ω t

(8)

ω gm A × α

ωgmVref

t

ω 2

+ ω 2

m cos(ωe t − φ ) Aα −

VT e p

Vctrl = −VT ln + + Pe

VT ω V Vref

2

−ω t

ωe 2 + gm ref In steady state, the e p term can be ignored. By substituting Vpd

VT with Vgmc and solving (1), (2), (4), and (11), the steady-state

value of Vctrl can be obtained as:

B. First-order Steady-state Behavior

ω gmVref ω gmω p mA α

− t (12)

In steady state, the Pe V term in (8) can be neglected and

T

ωe VT ωe + ω p A α

2 2

**Vout can also be solved explicitly by combining and substituting Vctrl ,ss 2 = −VT ln [cos(ωet − ϕt )] +
**

ωgmVref

2 Vref

Vctrl of (8) into (1) and (3). + 1

ωeVT

(9)

(1 + m cos ωet )

Vout , ss1 = V cos ωct

m cos(ωe t − φ ) ref

1+

2

ωeVT Aω p cos(ωt − ϕd )

+ 1 Vdin (t ) = A cos(ωt ) Vdout (t ) =

ω gmVref

Delay Block

ω 2 + ωp2

ωp

A× s A× s ωp

Vdin ( s ) = s + ωp Vdout ( s ) = 2

s2 + ω2 s + ω2 s + ωp

Fig.2. Peak detector delay block diagram.

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III. AGC LOOP SETTLING TIME

**Vout A. First-order AGC Circuit Settling Time Calculation
**

Vin VGA

Specifications for an AGC circuit often involve certain

Peak requirements associated with the transient response, and one

Detector

important figure-of-merit is the settling time [3]. A simple way

Vpd

of measuring this is to apply a unit step response to the system,

Delay e − jω p t i.e.

Block

Vctrl

Vgmc Vin = A1 (1 + k × u (t ))cos ωct (13)

Gm

Vref

Where u(t) is the unit-step function and k is the input amplitude

C

variation factor. The first-order Vctrl transient response with

respect to input unit-step response is

Fig.3. Second-order AGC circuit block diagram. The dotted area represents the Vref k −(

ω gmVref

t)

(14)

new peak detector model including the delay of the peak detector. Vctrl , sr1 = VT ln( ) − ln(1 − ( )e VT )

A1 (1 + k )α 1+ k

where ϕ = tan −1 ωeVT + tan −1 ( ωe ) . When ω p is much greater and Vout can be solved by substituting (14) into (1)

t

ωgmVref ωp Vref cos ωc t (15)

Vout ,sr1 =

than ω e , (12) reduces to (8) as expected. k −(

ωgmVref

t)

1− ( )e VT

In a similar manner to Section II, Vout and Vpd can also be 1+ k

expressed explicitly by combining and substituting Vctrl of (12) Then the 1% settling time Ts [12] of the Vout,sr1’s envelope can

into (1) and (3). Equation (12) also shows that the loop’s overall be solved as

response could be severely impeded by a low ω e (corresponding VT k + 100 (16)

Ts = ln

to excessive loop delay). To validate our theory, the Vpd root ωgmVref k + 1

mean square error percentage with respect to (ωe/ ωp), from Not surprisingly, (16) shows that the settling time is not only

SPICE simulation and calculation, is shown in Fig. 4. It can be a function of ω gmVref / VT , but also a function of input amplitude

seen that the error percentage increases when (ωe/ ωp) increases, variation ratio k.

and calculation and simulation results agree closely.

B. Second-order AGC Circuit Settling Time Calculation

Similarly, the second-order AGC circuit settling time can

also be calculated by applying a unit step response to the circuit

in Fig.3. The second-order Vctrl transient response with respect to

80

input unit-step response can be shown as follows:

Root mean square error (%)

60

(17)

Theory

(wgm=40MHz)

Simulation Vref

(wgm=40MHz)

A1α (1 + k )

Vctrl , sr 2 (t ) = VT ln

40 ω VT

p

Vref ωgm

−ω t

e p ωgmVref 1 − VT t

1 + ω V − − e

ωV 1+ k

p T

−1 p T −1

20 ω gmVref ωgmVref

Theory

Simulation

where ωp represents the pole angular frequency of peak detector.

(wgm=80MHz)

(wgm=80MHz) Substituting (17) into (1) and (3), the envelope of Vout, Vpd , then

0 becomes

0.001 0.01 0.1 1

we/wp

**Fig.4. Second-order AGC circuit root mean square error percentage vs.
**

(ωe/ωp) from SPICE simulation and theory . The error percentage increases

when ωe increases. Simulation parameters: VT=0.6V, ωc=2GHz, Vref=0.24V,

A=1mV, gm=0.5mS and 1mS, C=2pF, α=0.1, m=0.9.

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(18) V. CONCLUSION

Vref An exact dynamic model of linear-in-dB Automatic Gain

Vpd , sr 2 (t ) = Control (AGC) circuit is proposed and validated. The explicit

ω pVT

−ω p t

ω V

Vref ωgm steady-state behavior and the overall loop settling time are

1 + e 1 − t

− ( gm ref − )e VT calculated for first-order and second-order AGC loops. The

ω pVT ω pVT 1+ k

ω V − 1 ω V −1 analysis shows that the overall loop settling time depends on the

gm ref gm ref input amplitude ratio, phase detector delay, and other loop

The settling time Ts is difficult to be expressed explicitly from parameters. This exact large-signal model can also be used for

(18) but it can be solved iteratively. Equation (18) shows that the the design of wideband closed-loop polar transmitters.

transient behavior is a function of ω gmVref / VT , input amplitude

variation ratio k and peak detector pole ωp. If ωp is very low, the REFERENCES

Vpd settling response is dominated by ωp rather than ω gmVref / VT .

[1] P. Huang, C. Huang and C. K. Wang, “A 155-MHz BiCMOS automatic

Therefore, to achieve a fast settling AGC circuit, it is important gain control amplifier,” IEEE Transactions of Circuits and Systems II,

to increase ωp [13], ωgm, and the ratio Vref/VT. Analog and Digital Signal Processing, Vol. 46, Issue 5, May 1999, pp.

643-647.

[2] S. Otaka, G. Takemura and H. Tanimoto, “A low-power low-noise

IV. AGC SIMULATIONS AND VERIFICATION OF ANALYSIS accurate linear-in-dB variable-gain amplifier with 500-MHz bandwidth,”

Behavioral level simulations are provided in this section to IEEE Journal of Solid-State Circuits, Vol.35, Issue, 12, Dec. 2000,

pp.1942-1948.

compare the first-order/second-order settling time simulation

results and theoretical results, where the second-order settling [3] J. Khoury, “On the design of constant settling time AGC Circuits,” IEEE

Transactions of Circuits and Systems, II: Analog and Digital Signal

time is calculated iteratively. The response of the AGC circuit is Processing, Vol. 45, Issue 3, March 1998, pp. 282-294.

shown in Fig. 5, where previous theories [1, 3-4] did not describe [4] M. Shiue , K.H. Huang, C. C. Lu, C. K. Wang, and W. I. Way, “A VLSI

the loop characteristics dependence on input amplitude variation design of dual-loop automatic gain control for dual-mode QAM/VSB

ratio k. Note that the first-order estimation is only valid for CATV modem,” IEEE ISCAS’98 Symposium Digest, June 1998, pp.490-

small (ωe/ωp) ratio .The theoretical calculation results predicted 493.

by our theory are close to SPICE behavioral level simulation [5] M. Ito, T. Tamawaki, M. Kasahara and S. Williams, “Variable gain

results. amplifier in polar loop modulation transmitter for EDGE,” Proceeding of

ESSCIRC 2005, Sept 2005, pp. 511-514.

[6] T. Sowlati, D. Rozenblit, R. Pullela, M. Damgaard, E. McCarthy and D.

Koh etal, “Quad-Band GSM/GPRS/EDGE polar transmitter,” IEEE

Journal of Solid-State Circuits, Vol. 39, No.12, Dec. 2004, pp. 2179-2189.

30

[7] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits,

Cambridge University Press, 2 nd Edition, 2004, p.60-64.

25 [8] R. E. Ziemer and W. H. Tranter, Principle of Communication, 5th edition,,

John Wiely & Son Inc., 2002, pp. 106-124.

Settling Time Ts (ns)

SPICE Simulation (ω e/ω p)=1/20

20 [9] P. V. O’Neil, Advanced Engineering Mathematics, PWS-KENT

Publishing Company, 4th Editon, 1995, pp.40-43.

15 Second Order Calculation (ω e/ω p)=1/20 [10] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and Design

of Analog Integrated Circuits, 4th editon, John Wiely & Son Inc., 2001,

pp.488-552.

10

[11] P. V. O’Neil, Advanced Engineering Mathematics, PWS-KENT

Previous Settling

Time Estimation [3] Publishing Company, 4th Editon, 1995, pp.115-158.

5 [12] G. F. Franklin, J. D. Powell and A. E. Naeini, Feedback Control of

First/Second Order Calculation Dyamic Systems, Addison-Wesley Publishing Company, 3rd edition, 1994,

And SPICE Simulation, (ω e/ω p)=1/100

0 pp. 85-165.

0.01 0.1 1 10 100 [13] E. A. Grain and M. Perrott, “A 3.125 Gb/s limiting amplifier in CMOS

with 42dB gain and 1µs offset compensation,” IEEE Journal of Solid-State

k+1 Circuits, Vol.41, No.2, Feb 2006, pp.443-451.

**Fig.5. Comparison of first-order and second-order AGC circuit settling time
**

simulation and calculation results for (ωe/ωp)=1/20 and 1/100. Settling time Ts

is a function of input amplitude variation ratio k. Simulation parameters:

VT=0.6V, ωc=2GHz, Vref=0.24V, A=1mV, gm=1mS, C=2pF, α=0.1, m=0.9.

684

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