20 views

Uploaded by api-19755952

save

- Chapter4 Adc&Dac
- Bel_16_ADC and DAC
- Walas (1)
- AN276(AD)
- KDGC 500 Control Panel Manual o DGC-2000 DIGITAL GENSET CONTROLLER
- Mindray VS800 Users-Manual
- 1984-09_HP Journal Papers
- An 639
- interfacing with adc.pdf
- c1
- 2N3791-&-2N3792
- pp5pulsemodulation-130717124158-phpapp02.pptx
- 3271369715deb1b52db741ee58176a4f4cf8
- Temperature Control System u
- Fx Plc Manual 4ad
- cyborgs
- Analog-To-Digital and Digital-To-Analog Converters – Electronics Post
- Linearizing RTD
- AD7828
- imaging
- Ad 7780
- Tutorial DAQ
- ADC 2010-2011 survey
- 3293500 Electronic Load Controller
- ECG Application Example Using LPC4370 and LabTool Hardware
- Adc 16071
- AD1871
- Biomedical
- Mbed Course Notes - Analog Input and Output
- 14-bit ADC
- 7
- ESTADO
- 0708003
- undangan
- 2018 Ganjil Untuk Mahasiswa
- Bahia Ligia Planos Privados de Saude
- task 3
- kepada.rtf
- La Repubblica cosmica
- Portada de Revista
- Formation des Entrepreneurs en Construction.pdf
- Información
- 5bCb3T6Uuv
- Cover
- PHP1.pdf
- Desy.faktor Yang Mempengaruhi Perubahan
- 桃花红
- Jose Huaracha_Erlinda Pauccara_Trabajo de Suficiencia Profesional_Título Profesional_2017
- QUIMICA
- Ensayo Taylor
- jerawat.docx
- 2_Metode Harga Pokok Pesanan.pdf
- Key Fendt.txt
- Activos de Psicopedagogia
- MAKALAH 1
- Papa y Proc.fyh Mary
- CRE 36 AH N (- +)
- mt 1 qp - EM.xlsx
- r3 dyno.pdf
- HORIZONTES CULTURALES 66.pdf
- 8
- 12
- 7
- 15
- 6
- 5
- detector
- 14
- getPDF17
- 10
- 16
- exact dynamics
- getPDF
- Design and implementation of L1-band CA-code GPS RF front-end chip
- 13
- fulltext1
- general class ab
- 3
- 1
- 4
- PRINT3
- vga for uwb system
- fully differential cmos
- PRINT1
- PRINT4
- gm Vs id design flow
- 2
- PRINT5
- PRINT2

You are on page 1of 5

**REQUIREMENTS FOR UWB DIGITAL RECEIVERS
**

Y. Vanderperren*, Geert Leust, W. Dehaene*

* Katholieke Univ. Leuven, EE Dept. (ESAT-MICAS) t Delft Univ. of Technology

Kasteelpark Arenberg 10, 3001 Heverlee, Belgium Faculty of EE, Mathematics and Computer Science

Email: yves.vanderperrengesat.kuleuven.be Mekelweg 4, 2628 CD Delft, The Netherlands

Fax: +32 16 32.17.85

**Keywords: A/D Resolution, Digital Receiver, Gain Control. Actual Slope * Flash
**

23- =112.3 bIdB 0 Folding

A Half-Flash

Abstract 21-

U Pipelined

*S s.t* . \ * SAR

Digital pulsed ultra wideband (UWB) receivers offer m 19- S$igma-Delta

* **0 dB

numerous advantages compared to architectures based on

0

17-

analogue correlation, but present unique implementation E 15-

challenges. The specification of the Analogue-to-Digital z 13-

Converter (ADC) resolution constitutes one of the most * ****** U EAA \'

3*

critical activities in the design of digital UWB receivers. Cla 11- * *1** ******0* *.9'uI

Moreover, multi-bit ADCs must be associated with an 9. * ** ** ****e "UUDAt

Automatic Gain Control block which avoids the sub-optimal

7.

regimes of the ADC dominated by quantisation or saturation *

.. *..

\

**noise. This paper shows how to determine the ADC resolution 0 I
**

60 70 80 90

20 30 40

requirements and the optimal Automatic Gain Control (AGC)

10 50

settings for the general class of digital receivers. We conclude 10logi0(fo) [dBsps]

that 3 bits provide sufficient resolution on condition that the Figure 1: ADC achievable sampling rates vs. resolution [3].

AGC scales the input signal at a reference root mean squared

(RMS) level of half the ADC saturation voltage. either a high (Nyquist) sample rate or multi-bit resolution but

not both. Several high speed 1-bit receiver architectures have

1 Introduction been proposed, for example in [13,6]. However, 1-bit

receivers suffer from poor robustness against interferers,

The design of UWB receivers presents unique challenges. which must be improved using notch filters in the RF front-

The most popular receiver is based on matched filtering end or by shaping appropriately the transmitted pulse. The

(correlation) with the transmitted pulse followed by a RAKE first solution comes at the cost of flexibility, whereas the

structure capturing the multipath diversity of the channel. second requires the transmitter to know the interference at the

However, the pulse distortion introduced by the transceiver receiver via a feedback loop, for example.

antennas and the channel can vary among the multipaths. As a

result, the RAKE receiver can not achieve the optimal Parallel multi-bit ADC architectures based on signal

performance. Moreover, sampling at twice the chip rate leads channelisation in time [6,1] or frequency domain [3,9] reach

to unaffordable sampling rates for high bit rate applications. an aggregate sampling rate equivalent to Nyquist's criterion

This issue is even exacerbated in fractionally spaced and support interference cancellation in the digital domain.

receivers. Transmitted reference (TR) systems [5] sample the However, this advantage comes at the cost of increased area

received signal at the pulse repetition rate and avoid the need and power consumption, as each ADC typically consumes

for local template generation, but require extremely wideband about 100 mW using state-of-the-art Flash ADCs, see e.g.

delay lines in the analogue domain which are particularly [14,12]. The sampling rate speed is relaxed in [7] by using a

difficult to realise. bank of discrete-frequency matched filters followed by

parallel ADCs. Nevertheless, all these solutions require

On the other hand, digital based receivers provide more careful control of the circuit mismatches between the parallel

flexibility and benefit from CMOS technology scaling, but branches.

require ADCs sampling at Nyquist rate which are hardly

realisable and highly power consuming. Flash ADCs Subsampling techniques provide an attractive alternative

constitute the standard solution for the sample rates and [15,2]. As an example, a receiver based on such techniques

resolution required for digital UWB architectures (Figure 1). has been proposed in [15] and can offer data rates in the order

As the ADC power consumption of Flash ADCs scales of magnitude of 100 Mb/s at sampling rates below 500 MHz.

linearly with the sampling rate and as a factor close to 4 with Few results have been published about the bit width

the bit width [16, 8], the UWB system architect can choose requirements of digital receivers for pulsed UWB [10,2].

196

Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on February 27, 2009 at 08:09 from IEEE Xplore. Restrictions apply.

However, no unified framework has been proposed yet which

takes into account the combined optimisation of the ADC and

the AGC parameters, using realistic pulses in the 3.1-10.6

GHz band and in multipath environment. Using the

methodology presented in this paper, we show that 3 bits -

10 ..

**provide sufficient resolution if the AGC scales the input CO
**

signal at a reference root mean squared (RMS) level of half -20 ..

the ADC saturation voltage.

2 Methodology

The nonlinear nature of the ADC makes a deterministic

analysis of the effect of quantisation on the performance

problematic. A statistical approach is traditionally taken,

where the quantisation error is modelled as an additive -60

2 4 6 8 10

uniform random noise with zero mean and power o(, = q2/12 (saturation level)/(RMS signal level)

for rounding ADCs, where q = R/2b is the quantisation step. R

= 2 Vsa, is the input range of the ADC, which clips the input Figure 2: Quantisation noise to signal ratio vs. Vsat/RMS,n, flo

signal below -Vsa, and above Vsa,. This noise modelling is channel.

appropriate if the quantisation step q is small compared to the

range R, but becomes less accurate as the bit resolution

decreases. As UWB signals are immersed in additive white 1

Gaussian noise (AWGN), the required ADC resolution is

moderate (< 5 bits) compared to classical narrowband

systems. Moreover, the multipath UWB channel modifies the 0.5

distribution of the samples over the ADC range, compared to

an ideal single path channel. The channel response must be E0 0

therefore taken into account in the bit width decision process.

As a result, we will determine the ADC precision E(U

requirements by simulation. -0.51

Contrary to narrowband fixed-point analysis, we cannot

assume quantisation to be the dominant source of noise. For -1

narrowband systems, the minimum SNR required at the 0 10 20 30 40 50

detection device in order to reach a desired bit error rate time [ns]

(BER) is identified, and the number of bits is then determined

so that the SNR remains above this minimum value. This Figure 3: AGC scaling the ADC input to Vsat, no channel.

approach is not suitable for UWB systems, since the AWGN

and interference noise are the dominant sources of noise at the

output of the ADC. Instead, we will observe the SNR L

degradation introduced by the quantisation and decide the h (t) =

1=1 a I (.(t -ri ) (2)

number of bits so that the decrease in SNR remains limited.

where we have grouped the multipaths from different clusters

Contrary to high speed 1-bit ADCs, narrowband interference in a single summation. We do not include in (1) the time

is not a critical problem with multi-bit ADCs. In particular, hopping or direct sequence spreading code for the sake of

the subsampling receiver presented in [15] can remove the simplicity, without restricting the scope of the results

interference in the digital domain or avoid it by choosing a presented in this paper.

band free from interferers. We will therefore leave the issue

of interference out of the scope of this paper. 4 ADC Requirements and AGC Settings

3 UWB Signal Model For a given number of bits, the ratio of the saturation level

Vsat to the signal standard deviation at the input of the ADC

The received signal is modelled as a stream of PPM and/or RMSi, must fall within a certain range in order to minimise

PAM pulses affected by AWGN n(t): the quantisation noise. If Vsa, IRMSi, tends to zero, the

probability of ADC saturation/clipping is high and the

s (t) = a,yL

Cp(t

c, - n Tf- tn -r) + n() (1) saturation noise power quickly increases. If the ratio is too

large, the quantisation noise to signal ratio increases as the

where cnE {0 ±, ±3F,...} and t E {0, A, 2A, ...} RMS signal level decreases. This behaviour is illustrated for

correspond to the pulse modulation. We use the standard different bit widths in figure 2. The role of the AGC is to set

IEEE channel models CMI - CM4 [4] as the channel model the signal RMS level to an optimal attack point of the ADC

197

Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on February 27, 2009 at 08:09 from IEEE Xplore. Restrictions apply.

1

0.5 ~0

0 z,

_ O .5

E

0

-0.5

20

-1 ......... ..... .... .... ..... ........ .................................

....

**0 10 20 30 40 50 RMS signal level M 0 -10 input SNR
**

[dB]

time [ns]

Figure 4: AGC scaling the ADC input to Vsai, channel model Figure 6: SNR at the ADC output vs. SNR at the ADC input

CMl (realisation 1). and RMS signal level, 1-bit ADC, channel model CMI

(realisation 1).

region region dominated

dominated by by quantisation optimal region

saturation noise noise

20 _

=-10 .......1b m0 10

z Z

0 c o

N

a .....

QL -10

0

-40 ...

-20

10

20

2 4 6 8 10 RMS signal level M 0 -10 input SNR [dB]

(saturation level)I(RMS signal level)

Figure 5: Quantisation noise to signal ratio vs. VSa,/ RMSj,, Figure 7: SNR at the ADC output vs. SNR at the ADC input

channel model CM (realisation 1). and RMS signal level, 4-bit ADC, channel model CMI

(realisation 1).

**RMSrej,X which results from the trade-off between minimising
**

quantisation noise and avoiding

Another aspect to take into account is the AWGN level.

the region of operation

**dominated by saturation noise, on the left of fig. 2.
**

Quantisation noise may be dominant in narrowband systems

if the SNR at the ADC input is high enough. This situation is

The effect of the transmission channel must be taken into much less likely to occur in UWB systems. As a result, the

account in this trade-off analysis, or a conservative choice required number of bits is determined so that the SNR

will result. As an example, figure 3 shows a typical received degradation due to quantisation is limited, e.g. less than 0.1

pulse in absence of noise. The AGC scales this pulse to the dB, over the range of SNR values which allow for reliable

input of the ADC such that any clipping is avoided, by fitting reception. In this paper, we do not include the spreading gain

the received signal to the whole range [- Vsai, Vsaut] where we for the sake of generality and consider an SNR range from

assume Vsat 1lV. Figure 4 shows the effect of a typical UWB -10 to 20 dB. The optimal ADC attack point corresponds to

channel model. The received signal is not only spread in time the AGC gain which minimises the SNR degradation.

but also along the vertical axis: the samples are more

uniformly spread over the input range of the ADC. As a

Figures 6-7 illustrate the relationship between the SNR at the

output (SNRO1,,) and at the input (SNRi,) of the ADC, for

result, the crest factor of the received signal Vpeak /RMS,n

decreases and affects the optimal attack point of the ADC, as

different signal RMS levels (i.e. different AGC gains). Three

it is visible from figure 5.

regions can be identified:

198

Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on February 27, 2009 at 08:09 from IEEE Xplore. Restrictions apply.

ADC RMSin,opt

Resolution CM] CM2 CM3 CM4

20

I bit 0.591 0.592 0.597 0.598

2 bits 0.572 0.573 0.571 0.571

3 bits 0.533 0.536 0.535 0.536

210~ ~ ~ ~ b~it~ t

4 bits 0.483 0.486 0.487 0.489

5 bits 0.429 0.438 0.441 0.444

**Table 1: Optimum RMS value at the ADC input.
**

z

ADC RMSEopt

co Resolution CMJ CM2 CM3 CM4

4 2bits I bit 1.496 1.479 1.507 1.502

2 bits 0.313 0.266 0.249 0.237

3 bits 0.074 0.064 0.062 0.063

RMS signal level 4 bits 0.010 0.013 0.014 0.017

5 bits 0.006 0.004 0.004 0.005

Figure 8: Root mean squared degradation of the overall SNR

due to quantisation, as a function of the input RMS level, Table 2: Root mean squared SNR degradation due to

channel model CMI (realisation 1). quantisation, at the optimum input RMS level of table 1.

* At high RMS levels (above 1 V), the output SNR at the clipping ratio. Smaller bit widths present a higher risk of

output of the ADC converges to zero due to the saturation falling into the situation where the quantisation noise or the

noise. saturation noise degrades the output SNR performance. As a

* At low RMS levels (below 0.2V approximately), the result, more severe constraints are set on the precision of the

output SNR converges also to zero, due to the high gain and the measured signal power. As shown in table 2, the

quantisation step with respect to the RMS level. root mean squared SNR degradation due to quantisation is

* At intermediate RMS levels (between 0.2V and lV), a negligible for b > 3 at the optimal RMSi, values corresponding

linear relationship exists between the SNR at the input and at to table 1.

the output of the ADC, which indicates that the degradation

introduced by quantisation is bounded. The degradation is 5 Conclusions

minimal for the optimal value RMSIj,,p, which minimises the

difference between the optimal linear relationship between Flash ADC architectures constitute the basic choice for the

the SNR at the input and the output of the ADC sample rates and resolution required for digital UWB

SNRoU, SNRin

= (3) architectures, but they normally achieve poor linearity for

high resolution. As we have shown in this paper that the bit

and the actual relationship characterised by the specific width requirement is moderate, this issue is not critical for

functionfADC plotted in figures 6-7 digital UWB receivers. Instead, power consumption is the

SNRolt =fADC(RMSin, SNRin) (4) major concern. It is therefore of uttermost importance to

minimise the bit width and scale the received signal with

We choose to minimise the Root Mean Squared Error for a respect to the ADC dynamic range, using techniques

given bit width b, i.e. appropriate to the UWB peculiarities, such as we have

presented in this paper. We have shown that a 3-bit ADC is a

RMSE(b) = [ [SNRn-fADC(b, RMS1n, SNRJn)]2 dSNRn ] 1/2 suitable choice provided that the AGC scales the input signal

(5) at a reference RMS level of half the ADC saturation voltage.

Figure 8 illustrates the RMSE for different bit widths and Acknowledgements

RMS,, values. Table I shows the average optimal values

RMS,n,opt which minimise (5) for 100 different realisations of This work has been developed in the context of the MEDEA+

the IEEE channel models [14]

UPPERMOST project. Y. Vanderperren gratefully acknowl-

RMSi,jop (b) = arg min [RMSE(b)] (6) edges the financial support from the IWT Belgium.

**For a given resolution, the optimal RMSn,op, is approximately References
**

the same for different channel models and channel

realisations. It decreases with increasing resolution, since [1] B. Blazquez, P. Newaskar, F. Lee, A. Chandrakasan. "A

smaller quantisation steps allow decreasing the RMS level, Baseband Processor for Pulsed Ultra-Wideband

preserving the accuracy for small values while decreasing the

199

Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on February 27, 2009 at 08:09 from IEEE Xplore. Restrictions apply.

Signals", IEEE Custom Integrated Circuits Conf:,

(2004).

[2] M. Chen, R. Brodersen. "A Subsampling UWB Impulse

Radio Architecture Utilizing Analytic Signaling", IEICE

Trans. Electronics; vol. E88-C(6), pp. 1114-1121,

(2005).

[3] L. Feng, W. Namgoong. "An Oversampled Channelized

UWB Receiver", IEEE Conf. Ultra Wideband Systems

and Technologies, pp. 410-414, (2004).

[4] J. Foerster. "Channel Modeling Sub-Committee Report

Final (IEEE P802.15-02/490rl-SG3a)", (2003).

[5] R. Hoctor, H. Tomlinson. "Delay-Hopped Transmitted-

Reference RF Communications", IEEE Conf Ultra

Wideband Systems and Technologies, pp. 265-270,

(2002).

[6] S. Hoyos, B. Sadler, G. Arce. "Monobit Digital

Receivers for Ultrawideband Communications", IEEE

Trans. on Wireless Comm., vol.4(4), pp. 1337-1344,

(2005).

[7] S. Hoyos, B. Sadler, G. Arce. "Ultra-wideband

multicarrier communication receiver based on analog to

digital conversion in the frequency domain", IEEE

Wireless Comm. and Networking Conf., pp. 782-787,

(2005).

[8] B. Le, T. Rondeau, J. Reed, C. Bostian. "Analog-to-

Digital Converters", IEEE Signal Processing Mag., vol.

22(6), pp. 69-77, (2005).

[9] H.-J. Lee, D. Ha, H.-S. Lee. "Toward digital UWB

radios: part I - Frequency Domain UWB Receiver with

I bit ADCs", IEEE Conf. Ultra Wideband Systems and

Technologies, pp. 248-252, (2004).

[10] P. Newaskar, R. Blazquez, A. Chandrakasan. "A/D

Precision Requirements For An Ultra-Wideband Radio

Receiver", IEEE Workshop on Signal Processing

Systems, vol. 1, pp. 270-275, (2002).

[11] I. O'Donnell, M. Chen, S. Wang, and R. Brodersen. "An

Integrated, Low Power, Ultra-Wideband Transceiver

Architecture", IEEE CAS Workshop on Wireless

Communications and Networking, (2002).

[12] C. Sandner, M. Clara, A. Santner, T. Hartig, F.Kuttner.

"A 6-bit 1.2-GS/s Low-Power Flash-ADC in 0.13-,um

Digital CMOS", IEEE Journ. Solid-State Circuits, vol.

40(7), pp. 1499-1505, (2005).

[13] L. Smaini, D. Helal. "RF Digital Transceiver for

Impulse Radio Ultra Wide Band Communications",

European Solid-State Circuits Conf. Workshop, (2004).

[14] R. Thirugnanam, D. Ha, S. Choi. "Design of a 4-bit 1.4

GSamples/s Low Power Folding ADC for DS-CDMA

UWB Transceivers", IEEE Int. Conf: on Ultra-

Wideband, pp. 536-541, (2005).

[15] Y. Vanderperren, W. Dehaene, G.Leus. "A Flexible

Low Power Subsampling UWB Receiver Based on Line

Spectrum Estimation Methods", IEEE Int. Conf: on

Communications, (2006).

[16] M. Vogels, G. Gielen. "Architectural Selection of A/D

Converters", Proc. Design Automation Conf, pp. 974-

977, (2003).

200

Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on February 27, 2009 at 08:09 from IEEE Xplore. Restrictions apply.

- Chapter4 Adc&DacUploaded byKrishna Dhoot
- Bel_16_ADC and DACUploaded byBharavi K S
- Walas (1)Uploaded byMakram Makram
- AN276(AD)Uploaded byalgnben1746
- KDGC 500 Control Panel Manual o DGC-2000 DIGITAL GENSET CONTROLLERUploaded bynoriegascribd
- Mindray VS800 Users-ManualUploaded byPercy De la Cruz
- 1984-09_HP Journal PapersUploaded byElizabeth Williams
- An 639Uploaded byisapuncuna6395
- interfacing with adc.pdfUploaded byRyan Harris
- c1Uploaded byChristo Jacob K
- 2N3791-&-2N3792Uploaded byJuan David Velasquez Bran
- pp5pulsemodulation-130717124158-phpapp02.pptxUploaded byFrima Setyawan Nur Rohman
- 3271369715deb1b52db741ee58176a4f4cf8Uploaded byRo Hen
- Temperature Control System uUploaded byAman Preet
- Fx Plc Manual 4adUploaded byThanh Nguyen
- cyborgsUploaded byShaik Bawajan
- Analog-To-Digital and Digital-To-Analog Converters – Electronics PostUploaded byDurga Devi
- Linearizing RTDUploaded bycheng_chan
- AD7828Uploaded bymeroka2000
- imagingUploaded bystaners63
- Ad 7780Uploaded byalcplm
- Tutorial DAQUploaded byPuspendra Singh Yadav
- ADC 2010-2011 surveyUploaded byjofinjv3194
- 3293500 Electronic Load ControllerUploaded bybgrao
- ECG Application Example Using LPC4370 and LabTool HardwareUploaded byNaren
- Adc 16071Uploaded byJavier Ruiz Thorrens
- AD1871Uploaded byFredi Carlos Afonso
- BiomedicalUploaded byRangarajan Parthasarathy
- Mbed Course Notes - Analog Input and OutputUploaded byamhosny64
- 14-bit ADCUploaded byMahesh Gowtham Reddy N

- 8Uploaded byapi-19755952
- 12Uploaded byapi-19755952
- 7Uploaded byapi-19755952
- 15Uploaded byapi-19755952
- 6Uploaded byapi-19755952
- 5Uploaded byapi-19755952
- detectorUploaded byapi-19755952
- 14Uploaded byapi-19755952
- getPDF17Uploaded byapi-19755952
- 10Uploaded byapi-19755952
- 16Uploaded byapi-19755952
- exact dynamicsUploaded byapi-19755952
- getPDFUploaded byapi-19755952
- Design and implementation of L1-band CA-code GPS RF front-end chipUploaded byapi-19755952
- 13Uploaded byapi-19755952
- fulltext1Uploaded byapi-19755952
- general class abUploaded byapi-19755952
- 3Uploaded byapi-19755952
- 1Uploaded byapi-19755952
- 4Uploaded byapi-19755952
- PRINT3Uploaded byapi-19755952
- vga for uwb systemUploaded byapi-19755952
- fully differential cmosUploaded byapi-19755952
- PRINT1Uploaded byapi-19755952
- PRINT4Uploaded byapi-19755952
- gm Vs id design flowUploaded byapi-19755952
- 2Uploaded byapi-19755952
- PRINT5Uploaded byapi-19755952
- PRINT2Uploaded byapi-19755952