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Design and Implementation of L1-band C/A-code GPS
RF' Front-End Chip

Jong-Moon Kim, Ho-Jun Song Young-Back Kim

Dept. of Electronics Engineering Navicom Co. Ltd
Chungnam National University Rearch Center
Taejon, Korea Taejon, Korea

Abstract BPSK modulated signal with a 2.046-MHz bandwidth
centered at 1575.42 MHz. The bit rate of the U A code
This paper describes the design and implementation (CoarsdAcquisition) is 1.023 MHz. Also, the signal
of an L1-band UA-code GPS RF front-end chip. The level of GPS L1 C/A signal received at the antenna is
chip incorporates a low-noise RF pre-amplifier, a about -130 dBm, while the white thermal noise level at
frequency synthesizer with a conventional voltage- the antenna with a bandwidth of about 2 M H z is -111
controlled oscillator, a variable gain amplifier, and an dBm [l]. Thus, the L1 signal is actually buried into
analog-to-digital converter. Only external requirements noise and can not be acquired directly. The data
are a temperature compensated crystal oscillator, a two- acquisition and tracking are performed by the digital
pole LC filter, a varactor-tuned LC tank circuit for correlator.
tuning the frequency of the VCO, and standard passive Total power gain requirement of the RF front-end
components for the PLL loop filter, the impedance chip to bring up the noise floor to approximately 0 dBm
matching and the power supply decoupling. The chip is about 110 dB [2].
has been implemented in a 0.8-pm BiCMOS process. The proposed GPS receiver consists of two down-
The chip size and operating current are 9 nun2 and 42 conversion stages incorporating three stages of
mA at 3.3 V, respectively. amplification, since a single down-conversion design
has the risk of gain instability and a triple down-
conversion design requires the complexity of overall
1 Introduction GPS system.
The block diagram of the RF front-end chip is shown
The fundamental GPS (Global Positioning System) in Fig. 2. The GPS L1 signal from the active antenna is
technique intends to get accurate position, velocity, and input to the RF front-end chip via an associated RF filter
time data by using one-way ranging signal from the such as ceramic or SAW filters. Then, this signal is
GPS satellites and is being widely used in car down-converted to the first intermediate frequency of
navigation systems, auto-vehicle location systems, 171.78 MHz by the first local oscillator signal of
intelligent transport systems, and so on. The GPS 1403.64 MHz generated by the on-chip phase-locked
ranging signal broadcasting from the satellites uses two loop. After rejecting the image signal and strong out-of-
frequencies: a primary signal at 1575.42 MHz (L1 band) band jamming signals by subsequent IF filtering, this
and a secondary signal at 1227.6 MHz (L2 band). These signal is again down-converted to the second IF signal
signals are generated synchronously. However, most of 3.675 MHz by the second local oscillator signal of
civilian users will only use the primary L1 signals since 175.455 MHz. Since the specifications of the second IF
the L2 signal is encrypted and allowed to only the filter is modest, it is fully integrated on chip. The first
authorized users. and second local oscillator signals are derived from the
In this paper, we describe a low power L1-band C/A- frequency synthesizer which includes a 1403.64-MHz
code GPS front-end chip is described. VCO, dividers and a phase detector on chip. Fig. 3
shows the designed differential Colpitts oscillator of
2 GPS Receiver which the frequency is controlled by an external
varactor-tuned LC tank circuit [4]. A 10.026-MHz
The block diagram of the generic GPS receiver is reference frequency is required for the PLL. In most
shown in Fig. 1. The L1 signal is a spread spectrum applications, the user will need an external source such

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I I m Channel 0 m

Digital Correlator Micro-
RF Front-end
Fig. 1 Block diagram of a generic GPS receiver

LC Filter
( 1 71.78MHz)

Fig. 3 VCO circuit
T6XO Cl&k Sarnpl& Clock
(10.OZ6MHrl (50 13MHr) (5.013MHr)

Fig. 2 Block diagram of RF front-end

as temperature compensated crystal oscillators, to
provide greater frequency stability. The dividers
generate two local oscillator signals 1403.64 MHz and
175.455 MHz. The first three dividers operating at
higher frequencies are implemented in the emitter-
coupled logic, and the last divider and the phase
detector operating at lower frequencies are realized in
the CMOS logic to reduce the power consumption. The
first RF mixer is preceded by the RF amplifier of
sufficient gain (about 20 dB) to significantly reduce the
effect of high noise figure in the mixer. The input
transistor of the RF amplifier has a large area for low
base resistance. The first RF mixer itself is a
conventional Gilbert-cell double-balanced mixer. The
collectors of the RF mixer are left open and inductively
coupled to Vcc. The output of the first RF mixer is then
input to the first IF filter centered at 171.78 MHz to
reject image signals and large out-of-band jamming Fig. 4 Layout of the fabricated RF chip
signals. This first IF filtering may be implemented by
ether SAW or LC filter, but in this receiver, a two-pole the variation of power supply voltage, temperature, and
LC filter is chosen to reduce the cost of the GPS process parameters. The second IF filter is fully
receiver. implemented by an on-chip active RC bandpass filter
The RF front-end chip also incorporates a variable centered at 3.675 MHz. This filter achieves bandpass
gain amplifier circuit with a dynamic range of 70 dB. filtering characteristics by combining the 6th
The peak of the second IF output signal is detected by a butterworth low pass filter and interstage coupling
capacitor and fed back to an automatic gain control capacitors [SI.Finally, the second IF signal is converted
circuit. Actually, since the variation of GPS signal levels to 2-bit digital signals. All circuits in the RF front-end
according to the position of the satellites is not serious, have a differential configuration to reduce the effects of
the VGA intends to compensate for the effects due to the substrate coupling noise and the power supply

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bouncing. Fig. 4 shows the layout of the fabricated RF
font-end chip. The VCO is located at the left upper
comer and the signal path is made to progress around
the periphery of the chip. The VCO has an internal -_-. .
.. . . -
.. -.. . ..- .. -. . . I
1 .-
bandgap reference circuit for stable operations. 1 ’ 9 9 3 6 4 0 -.?HZ . . -
-36’.50 a B m

3 Experimental Results
The RF chip has been fabricated in a 2-poly 2-metal
0.8-pm BiCMOS process. The unity gain frequency f
of the vertical NPN transistor is about 12 GHz. Fig. 5
shows the output spectrum of the VCO. The measured
phase noise is -85 dBc/Hz at lOKHz offset. Fig. 6 shows
the output spectrum of the first and second IF signal, CENTER 1.403640GHz SPAN 2.OOOMHZ
respectively. All spurii are 4 0 d B below the wanted R B W 3OkHZ V B W 30kHZ S W P 5 0 . 0 m a

signal output.
Fig. 5 Measured VCO spectrum
The measured dynamic range of the VGA according to
the control voltage is shown Fig. 7. Fig. 8 shows the
characteristics of the first LC filter and the second
internal filter, respectively. The final signal waveform
and its digital data after AID conversion are shown in
Fig. 9. The performance of the RF chip is summarized
in Table I.

4 Conclusions
An L1-band CIA-code GPS RF chip has been
I-\\ - -

implemented in a 0.8-pm BiCMOS process. Measured
results show that all circuits operate well as expected.

References CENTER 171
R E W 30Okb4z
V B W 300kHz

[ l ] B. W. Parkinson et al., GPS : Theory and
Applications Volume I, AIM, 1996.
[2] P. Mattos, “GPS 2 : Receiver Architecture,”
Electron. World, Wireless World, pp. 29-32, Jan.
[3] A. R. Alvarez, BiCMOS Technology and
Application, Second Edition, Kluwer Academic
Publishers, 1993.
[4] A. M. Murphy et al., “A Low-power Low-cost
Bipolar GPS Receiver Chip,” IEEE Journal of
Solid-State Circuits, Vol. 32, No. 4, pp. 587-591,
Apr. 1997.
[5] Francesco Piazza et al., “A 1.57-GHz Front-End for
Triple Conversion GPS Receiver,” IEEE Journal of
Solid-State Circuits, Vol. 33, No. 2, pp. 204-210.
Feb. 1998.
[6] Global Positioning Product Handbook, GEC CENTER 3 . 6 7 5 M H z SPAN 5 . 0 0 0 M H Z
Plessey, August 1996. R B W 3OkHz V E W 30kHz S W P 50.0ms

[7] R. G. Meyer et al., “A DC to 1-GHz Differential (b)
Monolithic Variable-Gain Amplifier,” IEEE Journal Fig. 6 Spectrum of the first and second IF signal
of Solid-state Circuits, Vol. 26. No. 11, pp. 1673- (a) first IF output (b)second IF output
1680, Nov. 1991.

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1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30
Control Vokage(v]

Fig. 7 Measured dynamic range of the VGA


Fig. 9 Final IF waveform and its digital data
(a) 3.675MHz IF signal
(b) its digital data after A/D conversion

10- I
Parameters Values
5- Chip Size
Operation Voltage
3 mm x 3 mm
2.5- 4.0 V
.- -
Operating Current @ 3.3 V, 27 "C 42 mA
z O:
Total Power Gain 113 dB
5- Dynamic Range of AGC 63 dB
Phase Noise of VCO @ f IOKHz - 85 dBc/Hz
-10 - Input -1 dB Compression - 30 dBm
.I5 ; 10

15 20

Fig. 8 Measured characteristics of the first and the
second IF filters.
(a) LC filter (b) internal filter

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