The Built In Self Test

Alek Veloff Computer Science and Engineering Tech University of Toledo, Toledo, OH Abstract
In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also goes into detail in the design of the modules in the architecture and how the process works.

Scott Stocker Computer Science and Engineering Tech. University of Toledo, Toledo, OH specific integrated circuits (ASIC) are starting to turn to FPGAs as a useful alternative [4]. As market share and uses increase for FPGA devices, testing has become more important for costeffective product development and error free implementation [7]. One of the most important functions of the FPGA is that it can be reprogrammed. This allows the FPGA’s initial capabilities to be extended or for new functions to be added. “The reprogrammability and the regular structure of FPGAs are ideal to implement low-cost, fault-tolerant hardware, which makes them very useful in systems subject to strict highreliability and high-availability requirements” [1]. FPGAs are high performance, high density, low cost, flexible, and reprogrammable. As FPGAs continue to get larger and faster, they are starting to appear in many mission-critical applications such as space applications and manufacturing of complex digital systems such as bus architectures for some computers [4]. A good deal of research has recently been devoted to FPGA testing to ensure that the FPGAs in these mission-critical applications will not fail. 3. Fault Models Faults may occur due to logical or electrical design error, manufacturing defects, aging of components, or destruction of components (due to exposure to radiation) [9]. FPGA tests

1. FPGA Basics A field-programmable gate array (FPGA) is a semiconductor device that can be used to duplicate the functionality of basic logic gates and complex combinational functions. At the most basic level, FPGAs consist of programmable logic blocks, routing (interconnects), and programmable I/O blocks [3]. Almost 80% of the transistors inside an FPGA device are part of the interconnect network [12]. FPGAs present unique challenges for testing due to their complexity. Errors can potentially occur nearly anywhere on the FPGA including the LUTs or the interconnect network. 2. Importance of Testing The market for reconfigurable systems, namely FPGAs, is becoming significant. Speed, which was once the greatest bottleneck for FPGA devices, has recently been addressed through advances in the technology used to build FPGA devices. As a result, many applications that used to use application

should detect faults affecting every possible mode of operation of its programmable logic blocks and also detect faults associated with the interconnects. PLB testing tries to detect internal faults in one or more than one PLB. Interconnect tests focus on detecting shorts, opens, and programmable switches stuck-on or stuck-off [1]. Because of the complexity of SRAM-based FPGA’s internal structure, many different types of faults can occur. Faults in SRAM-based FPGA’s can be classified as one of the following: • Stuck At Faults • Bridging Faults Stuck at faults, also known as transition faults, occur when normal state transition is unable to occur. The two main types are stuck at 1 and stuck at 0. Stuck at 1 faults result in the logic always being a 1. Stuck a 0 results in the logic always being a 0 [2]. The stuck at model seems simple enough, however, the stuck at fault can occur nearly anywhere within the FPGA. For example, multiple inputs (either configuration or application) can be stuck at 1 or 0 [4]. Bridging faults occur when two or more of the interconnect lines are shorted together. The operation effect is that of a wired and/or depending on the technology. In other words, when two lines are shorted together the output will be an AND or an OR of the shorted lines [9].

There are two basic types of testing methods: 1) On-line Testing – On-line testing occurs without suspending the normal operation of the FPGA. This type of testing is necessary for systems that cannot be taken down. Built in self test techniques can be used to implement online testing of FPGAs [9]. 2) Off-line Testing – Off-line testing is conducted by suspending the normal activity of the FPGA and entering the FPGA into a “test mode”. Off-line testing is usually conducting using an external tester but can also be done using BIST techniques [9]. FPGA testing is a unique challenge because many of the traditional testing methods are either unrealistic or simply would not work. There are several reasons why traditional techniques are unrealistic when applied to FPGAs: 1. A Large Number of Inputs Inputs for FPGAs fall into two categories: configuration inputs or application (user) inputs. Even small FPGAs have thousands of inputs for configuration and hundreds available for the application. If one were to treat an FPGA like a digital circuit, imagine the number of input combinations that would be needed to thoroughly test the device [4]! 2. Large Configuration Time The time necessary to configure the FPGA is relatively high (ranging anywhere from 100ms to a few seconds). As a result, one of the objectives for FPGA

4. Testing Techniques

testing should be to minimize the number of reconfigurations. This often rules out using manufacture oriented testing methods (which require a great number of reconfigurations) [4]. 3. Implementation Issues BIST methods aim for “a one size fits all” approach – meaning that one could write a BIST and apply it across any number of different FPGA devices. In reality, each FPGA is unique and may require code changes for the BIST. For example, the Virtex FPGA does not allow self loops in LUTs, while many other types of FPGAs allow this programming model [4]. Test quality can be broken into four key metrics [7]: 1. Test Effectiveness (TE) 2. Test Overhead (TO) 3. Test Length (TL) [usually refers to the number of test vectors applied] 4. Test Power The most important metric is Test Effectiveness. TE refers to the ability of the test to detect faults and be able to locate where the fault occurred on the FPGA device. The other metrics become critical in large applications where overhead needs to be low or the test length needs to be short in order to maintain uptime. Traditional methods for FPGA testing, both for PLBs and for interconnects, rely on externally applied vectors. A typical testing approach is to configure the device with the test circuit,

exercise the circuit with vectors, and interpret the output as either a pass or a fail. This type of test pattern allows for very high level of configurability but full coverage is difficult and there is little support for fault location and isolation [11]. Information regarding defect location is important because new techniques can reconfigure FPGAs to avoid faults [5]. Built-in self test methods do not require external equipment and can used for on-line or off-line testing [10]. Many applications of FPGAs rely on online testing to “protect against transient failures and permanent faults” [1]. Typically, BIST solutions lead to low overhead, large test length, and moderately high power consumption [2] 5. The BIST Architecture The BIST architecture can be simple or complicated based on the purpose of the test being performed on the circuit. Some can be specific such as architectures for a circular self-test path or a simultaneous self-test. A basic BIST architecture for testing an FPGA includes a controller, pattern generator, the circuit under test, and a response analyzer [6]. Below is a schematic of the architectural layout.

5.1 Test Pattern Generator

The test pattern generator (TPG) is important because it produces the test patterns that enter the circuit under test (CUT). It is initially a counter that sends a pattern into the CUT to search for and locate and faults. It also includes one output register and one set of LUT. The pattern generator has three different methods for pattern generation. One such method is called exhaustive pattern generation [8]. This method is the most effective because it has the highest fault coverage. It takes all the possible test patterns and applies them to the inputs of the CUT. Deterministic pattern generation is another form of pattern generation. This method uses a fixed set of test patterns that are taken from circuit analysis [8]. Pseudo-random testing is a third method used by the pattern generator. In this method, the CUT is simulated with a random pattern sequence of a random length. The pattern is then generated by an algorithm and implemented in the hardware. If the response is correct, the circuit contains no faults. The problem with pseudorandom testing is that is has a low fault coverage unlike the exhaustive pattern generation method. It also takes a longer time to test [8].
5.2 Test Response Analyzer

The two CUTs must be exact. The registered and unregistered outputs are then put together in the form of a shift register. The function generator within the response analyzer compares the outputs. The outputs are then ORed together and attached to a D flip-flop [9]. Once compared, the function generator gives a response back of a high or low depending on if faults are found or not. 6. The BIST Process In a basic BIST setup, the architecture explained above is used. The test controller is used to start the test process [9]. The pattern generator produces the test patterns that are inputted into the circuit under test. The CUT is only a piece of the whole FPGA chip that is being tested on and found within a configurable logic block or CLB [9]. The FPGA is not tested all at once but in small sections or logic blocks. A way of offline testing can also be used as an alternative. A section is “closed” off and called a STAR (selftesting area). This section is temporarily offline for testing and does not disturb the process of the rest of the FPGA chip [1]. After a test vector scans the CUT, the output of the test is analyzed in the response analyzer. It is compared against the expected output. If the expected output matches the actual output provided by the testing, the circuit under test has passed. Within a BIST block, each CUT is tested by two pattern generators. The output of a response analyzer is inputted to the pattern generator/response analyzer cell [6]. This process is repeated throughout the whole FPGA, a small section at a time. The output from the response analyzer is stored in memory for diagnosis [9]. The

The most important part of the BIST architecture is the test response analyzer (TRA). Like the pattern generator, its uses one output generator and one LUT. It is designed based on the diagnostic requirements [6]. The response analyzer usually contains comparator logic. Two comparators are used to compare the output of two CUTs.

test results are then reviewed. Below is a schematic sample of a BIST block.

7. Conclusion In conclusion, FPGA testing is becoming more and more important as FPGAs themselves grow to be faster and larger. Fault errors that occur within a chip need to be located and dealt with so that the FPGA can work properly. A built-in-self-test is one way of testing an FPGA internally without the use of external components. The BIST test uses architecture found within the FPGA to perform the testing. The FPGA is broken down into smaller section or logic blocks where the testing takes place. In each section, a pattern generator sends a test vector into the circuit being tested on. The output is then analyzed in the response analyzer and stored in memory where it is later evaluated. This process is continued until the whole FPGA chip is tested. The advantage of the BIST test is that it can be done while the FPGA is online. Another advantage is that the test is done internally and no expense is used on external components.

8. References
[1] Abramovici, M; Stroud, C; Emmert, J. OnLine BIST and BIST-Based Diagnosis of FPGA Logic Blocks. Visited at: http://www.eng.auburn.edu/users/strouce/class/bi st/tvlsi04.pdf, 2005. [2] Faith, Brian; Leland, Tim. Programmable Built in Self Test (BIST) for System Memory. Visited at: http://www.quicklogic.com/images/appnote30.pd f, 2005. [3] Field-programmable gate array. Wikipedia, the free encyclopedia. Visited at: http://en.wikipedia.org/wiki/FPGA, 2005. [4] Goyal, Saurabh; Choudhury, Mihir. Intel Student Research Contest – India Synopsis. Visited at: http://www.intel.com/research/documents/IITB_ prop.pdf, 2005. [5] Harris, I. G.; Tessier, R. Testing and Diagnosis of Interconnect Faults in ClusterBased FPGA Architectures. Visited at: http://www.cecs.uci.edu/journal_articles/tcad_fp ga.pdf, 2005. [6] Mohammed Y. Niamat and Prabhu Mohan. Logic BIST Architecture for FPGAs. 2001. [7] Parreira, A; Teixeira, J.P.Santos, M. Built-In Self-Test Preparation in FPGAs. Visited at: http://figaro.inesc.pt/~mabs/papers/FPL2004.pdf, 2005. [8] Peng, Zebo. “Built-in Self Test (BIST)”.Embedded Systems LaboratoryIDA. Visited at: http://www.ida.liu.se/~TDTS01/lectures/05/lec10 .pdf, 2005. [9] Sahni, Arunjit. Built In Self Test Implementatin for Testing the Interconnects of a Multiple-FPGA System. The University of Toledo. May 2005. [10] Stroud, C; Chen, P; Konala, S; Abramovici, M. Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks. Visited at: http://portal.acm.org/citation.cfm?doid=228370.2 28386, 2005. [11] Sundararajan, P; Guccione, S; McMillan, S. FPGA Device Test Using JBits. Visited at: http://klabs.org/richcontent/MAPLDCon01/Prese ntations/E/E5_Sundararajan_S.ppt, 2005. [12] Tahoori, Mehdi; Mitra, Subhasish. Application-Independent Testing of FPGA Interconnects. Visited at: http://ieeexplore.ieee.org/iel5/43/32559/0152244 3.pdf?arnumber=1522443, 2005.

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