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IP Core Design

Lecture 17
Introduction to AXI
Juinn-Dar Huang, Ph.D.
Assistant Professor
jdhuang@mail.nctu.edu.tw
November 2004
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1 copyright 2004
Outlines
AXI overview
Signal definitions
Channel handshaking
Addressing options
Slave responses
Protocol Details
Transaction ordering
Data transfers
Clock and reset
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2 copyright 2004
Background
AXI (Advanced eXtensible Interface) by ARM
Also known as AMBA 3.0
Debut in Embedded Professor Forum (EPF), 2003
Version 1.0 announced in March 2004
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3 copyright 2004
Objectives
Provide high bandwidth and low latency
Enable high frequency operations
Fit for devices with high initial latency
e.g., DRAM controllers
Provide flexibility of interconnect architectures
Be (functionally) backward-compatible with
existing AHB and APB
not plug-n-play
bus bridges are required
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4 copyright 2004
Key Features
Separate address/control and data phases
Separate read and write channels to enable more
efficient DMA controllers
Burst-based transactions with only start address
issued
Unaligned data transfers using separate byte-lane
strobes
Multiple outstanding transactions
Out-of-order transaction completion
Latency-insensitive protocol by register slicing
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5 copyright 2004
Channel Architecture
5 unidirectional channels
AXI
Master
AXI
Slave
Write Address/Control
AWREADY
Write Data
WREADY
Read Data
RREADY
Write Response
BREADY
Read Address/Control
ARREADY
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6 copyright 2004
Read Transaction (1/2)
AXI
Master
AXI
Slave
Read Address/Control
ARREADY
Read Data
RREADY
Master issues address and control
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7 copyright 2004
Read Transaction (2/2)
AXI
Master
AXI
Slave
Read Address/Control
ARREADY
Read Data
RREADY
Slave returns data and response
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8 copyright 2004
Write Transaction (1/3)
AXI
Master
AXI
Slave
Write Address/Control
AWREADY
Write Data
WREADY
Write Response
BREADY
Master issues address and control
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9 copyright 2004
Write Transaction (2/3)
AXI
Master
AXI
Slave
Write Address/Control
AWREADY
Write Data
WREADY
Write Response
BREADY
Master sends data
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10 copyright 2004
Write Transaction (3/3)
AXI
Master
AXI
Slave
Write Address/Control
AWREADY
Write Data
WREADY
Write Response
BREADY
Slave acknowledges
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11 copyright 2004
AMBA 2.0 AHB Burst
A31
Address and Data are linked together (by HREADY signal)
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12 copyright 2004
AXI Burst Start Address for a Burst
A31
Reduce the address channel utilization
Use Address/Control channel more efficiently
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13 copyright 2004
Outstanding Transactions
A31
Decouple the fixed link between address and data
no HREADY-like signal to synchronize the pipeline
Enable parallel processing of transactions
Avoid a high-initial-latency slave blocking the
channel
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14 copyright 2004
Out-of-Order Completion
A31
Fast slaves may return data before slow slaves
Complex slaves may return data out of order
extremely helpful to DMAC and DRAMC
Effectively reduce the transaction latency
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15 copyright 2004
Data Interleaving
A31
Further boost the utilization of data bus
Data within a burst is always in order
each transaction has a unique ID
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16 copyright 2004
Channel Handshaking
Two-way handshaking (VALIDREADY)
used in all 5 channels
source uses VALIDto indicate when valid data is
available
destination uses READY to indicate the data is
accepted
For read/write data channels
a LAST signal is used to indicate the last data transfer
is taking place
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17 copyright 2004
Channel Properties
Address channels
variable-length burst, 1-16 data transfers per burst
a transfer can be of 1, 2, 4, , 64, 128 bytes
3 burst modes - fixed, incrementing, wrapping
Write data channel
each byte lane has its own strobe signal
Byte Lane 4n+0
WSTRB[0]
Byte Lane 4n+1
WSTRB[1]
Byte Lane 4n+2
WSTRB[2]
Byte Lane 4n+3
WSTRB[3]
1
1
0
0
Though bus width is 32-bit,
Only bytes on 4n+0 and 4n+3 lanes
are valid for writes in this transfer
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18 copyright 2004
Interconnect Matrix
Master-like port
Slave-like port
Interconnection
shared bus architecture
multi-layer architecture
something in-between
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19 copyright 2004
Read Burst Example
4-beat read burst
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20 copyright 2004
Overlapping Read Burst Example
3-beat read burst + 2-beat read burst
Enable a slave to begin preparing data of the 2nd burst
before the completion of the 1st burst
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21 copyright 2004
Write Burst Example
4-beat write burst
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22 copyright 2004
Transaction Ordering (1/2)
Out-of-order transaction completion is allowed
how? transaction ID is required
Transfers with the same transaction ID must be
completed in order
no way to distinguish the transfer order within a
transaction
Applications
enable fast-responding slaves to complete in advance
of earlier transactions with slower slaves
complex slaves can return read data out-of-order
e.g., DRAM controllers
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23 copyright 2004
Transaction Ordering (2/2)
If a master wishes to have OOO transactions
capability to supply different ID tags is required
If a master requires no OOO transactions
all transactions with the same ID tag
For multi-master systems
interconnect is responsible for appending a Master ID
i.e., to ensure that ID tags from different masters are unique
Simple masters can issue all transactions with the
same ID tag
Simple slaves can respond transactions in order
regardless of the ID tag
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24 copyright 2004
Signals of Write Address Channel
Signal Source Description
AWID[3:0] M Write address ID.
AWADDR[31:0] M Write address. The 1st address in a write burst.
AWLEN[3:0] M Burst length. 1-16 transfers in a burst.
AWSIZE[2:0] M Burst size. 1, 2, 4, , 64, 128 bytes per transfer.
AWBURST[1:0] M Burst type. Fixed, incrementing, or wrapping.
AWVALID M Write address/control valid.
AWREADY S Write address/control accepted.
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25 copyright 2004
Signals of Write Data Channel
Signal Source Description
WID[3:0] M Write data ID. Must match AWID.
WDATA[31:0] M Write data. Can be 8, 16, , 512, 1024 bits wide.
WSTRB[3:0] M Write strobes. One strobe for each byte lane.
WLAST M Last write transfer in a burst.
WVALID M Write data valid.
WREADY S Write data accepted.
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26 copyright 2004
Signals of Write Response Channel
Signal Source Description
BID[3:0] S Write data ID. Must match AWID.
BRESP[1:0] S Write response.
BVALID S Write response valid.
BREADY M Write response accepted.
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27 copyright 2004
Signals of Read Address Channel
Signal Source Description
ARID[3:0] M Read address ID.
ARADDR[31:0] M Read address. The 1st address in a read burst.
ARLEN[3:0] M Burst length. 1-16 transfers in a burst.
ARSIZE[2:0] M Burst size. 1, 2, 4, , 64, 128 bytes per transfer.
ARBURST[1:0] M Burst type. Fixed, incrementing, or wrapping.
ARVALID M Read address/control valid.
ARREADY S Read address/control accepted.
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28 copyright 2004
Signals of Read Data Channel
Signal Source Description
RID[3:0] S Read data ID. Must match ARID.
RDATA[31:0] S Read data. Can be 8, 16, , 512, 1024 bits wide.
RRESP[1:0] S Read response.
RLAST S Last read transfer in a burst.
RVALID S Read data valid.
RREADY M Read data accepted.
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29 copyright 2004
Handshaking Process
VALID READY two-way handshaking
sources generate VALID to indicate when the data is
valid
destinations generate READY to indicate when the data
is accepted
No combination paths between masters and
slaves
all timing paths must be registered
Successful transfer must qualify both VALID and
READY
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30 copyright 2004
Handshaking Timing Diagrams
1. VALID before READY
2. READY before VALID
3. VALID with READY
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31 copyright 2004
Fast Handshaking
Two-way handshaking typically needs 2 cycles
1st cycle for VALIID high, and 2nd cycle for READY
If a slave can always accept any valid address
i.e., never require wait cycles
AWREADY/ARREADY can be always high for 1-cycle
handshaking
If a master can always accept any valid data
i.e., never require wait (busy) cycles
RREADY can be always high for 1-cycle handshaking
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32 copyright 2004
Dependency in Read Transactions
A slave can wait for ARVALID before asserting ARREADY
A slave must wait for ARVALID & ARREADY before
asserting RVALID
A master can wait for RVALID before asserting RREADY
ARVALID
RVALID
ARREADY RREADY
can wait
must wait
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33 copyright 2004
Dependency in Write Transactions
A slave can wait for AWVALID, WVALID, or both before
asserting AWREADY
A slave can wait for AWVALID, WVALID, or both before
asserting WREADY
A slave must wait for WVALID & WREADY before
asserting BVALID
A master can wait for BVALID before asserting BREADY
can wait must wait
AWVALID
WVALID
AWREADY WREADY
BVALID
BREADY
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34 copyright 2004
Burst in AXI
Masters provide the start address of a burst
Slaves are in charge to calculate the addresses of
subsequent transfers in a burst
Bursts can not cross 4KB boundary
i.e., address is allocated to a slave in 4KB unit
simplify the decoder within an interconnect
simplify the address generator within a slave
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35 copyright 2004
Burst Length
No early burst termination
allowed
For a write transfer, write
strobes can be used to
disable writes on certain byte
lanes
In a read transfer, a master
can just discard the read data
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36 copyright 2004
Burst Size
For incrementing and wrapping
bursts and transfer sizes are
smaller than the data bus width
transfers are on different byte lanes
for each beat
For fixed bursts
address remains constant within a
burst
every transfer uses the same byte
lanes
The size of any transfer can not
exceed the data bus width
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37 copyright 2004
Burst Type (1/2)
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38 copyright 2004
Burst Type (2/2)
Fixed burst
address remains constant within a burst
for FIFO-like devices
Incrementing burst
increment value depends on the transfer size
for typical sequential memory-like devices
Wrapping burst
wrap boundary = transfer_size x number_transfer
two restrictions
the start address must be aligned to the transfer size
burst length must be 2, 4, 8, or 16 only
for cache line refill
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39 copyright 2004
Advanced Controls
Cache support
ARCACHE[3:0], AWCACHE[3:0]
bufferable; cacheable; read allocate; write allocate
Access protection
ARPROT[2:0], AWPROT[2:0]
normal or privileged; secure or not; instruction or data
Atomic operation
ARLOCK[1:0], AWLOCK[1:0]
normal, exclusive, or locked access
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40 copyright 2004
Slave Responses (1/2)
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41 copyright 2004
Slave Responses (2/2)
Read response is returned along with read data
different responses for different transfers in a burst
Write response is returned via the dedicated Write
Response channel
just one response available for an entire burst
No early burst termination allowed even if there
are transfer errors
Masters support multiple outstanding transactions
must be able to handle an erroneous earlier transaction
while later transactions are underway
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42 copyright 2004
Response Type
OKAY
everything is fine
EXOKAY
SLVERR (slave error)
FIFO/buffer overflow or underflow
unsupported transfer size
try to write a read-only region
try to access an address where no registers are there
access timeout
DECERR (decoder error)
no slave presented at that address
Protocol Details
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44 copyright 2004
Transaction Ordering Rules
Transactions from different masters have no ordering
restrictions
Transactions from the same master but with different IDs
have no ordering restrictions
Write transactions with the same AWID must complete in
order
Read transactions with the same ARID must complete in
order
a salve must complete transactions with the same ARID in order
an interconnect must ensure read transactions from different
slaves in order
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45 copyright 2004
Read and Write Ordering
No ordering restrictions between read and
write transactions
If a given order is required
the master must ensure the earlier transaction is
complete before issuing the later transaction
A read transaction is completed when the last
data/response transfer is received
A write transaction is completed when the write
response is received
sending out all write data is not an end
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46 copyright 2004
ID Tag Width
Suggestions
Support transaction ID up to 4 bits for a master
16 outstanding transactions at most for a master
Support up to 16 master ports for an interconnect
Master IDup to 4 bits
Support 8-bit transaction ID for a slave
Master Slave
Interconnect
4-bit 8-bit
Master
4-bit
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47 copyright 2004
Narrower Transfers
32-bit data bus
5-beat transfer
starting address is 4n+0
transfer size is 1-byte
64-bit data bus
3-beat transfer
starting address is 8n+4
transfer size is 4-byte
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48 copyright 2004
Unaligned Transfers (1/2)
WSTRB[3:0] = 4b1110
for the 1st transfer
WSTRB[3:0] = 4b1000
for the 1st transfer
Masters must ensure that
the low-order address must be consistent with byte lane strobes
Or, slaves can just ignore the low-order address and
refer byte lane strobes only
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49 copyright 2004
Unaligned Transfers (2/2)
WSTRB[7:0] = 4h0F
for the 1st transfer
WSTRB[7:0] = 4h80
for the 1st transfer
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50 copyright 2004
System Clock
ACLK
all inputs are sampled on the rising edge of ACLK
all outputs changes just after the rising edge of ACLK
strictly synchronous design fashion
no combinational paths between master and slave I/Os
all timing paths must be registered
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51 copyright 2004
System Reset
ARESETn
active-low signal
can be asserted asynchronously
must be deasserted synchronously
During reset
masters must drive ARVALID, AWVALID and WVALID
low
slaves must drive RVALID and BVALID low