MSE 894: POWER CONVERSION IN ALT ENERGY
RING 2014
Project Report 2
IPD and APOD Modulation Schemes for
Multilevel Diode Clamped Inverters
SUBMI TTED BY: VI J AYARAGHAVAN RAVI
SFU I D: 301229846
Email: vravi@sfu.ca
Date: July 04, 2014
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ABSTRACT
In this project the multilevel diode clamped inverter is studied. The simulation are
carried out using MATLAB Simulink. The diode clamped inverters are modulated
using Pulse Width Modulation technique. The types of modulation studied in this
project are In Phase Disposition (IPD) and Alternative Phase Opposite Disposition
(APOD). The IPD modulation has a series of carrier waves which are in phase
whereas the APOD has alternate carrier waves in phase and the immediate next
carrier completely out of phase. The multilevel inverters are highly popular in high
power electronics applications. There are many uses of multilevel inverters in
industry especially in applications that operate in Megawatts. First, a three level
diode clamped inverter is implemented and the harmonic effects are studied under
IPD and APOD modulation schemes. Then, the study is extended to a four level
diode clamped inverter and its harmonic effects are studied. Finally, comparisons
are drawn between the various scenarios from the obtained results. It is observed
that the IPD modulation scheme gives better overall harmonics.
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INTRODUCTION
The general structure of the multilevel inverter is to synthesize a sinusoidal
voltage from several levels of voltages typically separated by capacitors. The so
called “multilevel” starts from three levels. A threelevel inverter, also known as a
“neutralclamped” inverter, consists of two capacitor voltages in series and uses
the center tap as the neutral. Each phase leg of the threelevel inverter has two
pairs of switching devices in series. The center of each device pair is clamped to
the neutral through clamping diodes. The output obtained from a threelevel
inverter is a quasisquare wave output if fundamental frequency switching is used.
Multilevel inverters are being considered for an increasing number of applications
due to their high power capability associated with lower output harmonics and
lower commutation losses. Multilevel inverters have become an effective and
practical solution for increasing power and reducing harmonics of AC load. The
main multilevel topologies are classified into three categories: diode clamped
inverters, flying capacitor inverters, and cascaded H bridge inverters. In a three
phase inverter system, the number of main switches of each topology is equal.
Comparing with the number of other components, for example, clamping diodes
and dclink capacitors having the same capacity per unit, diode clamped inverters
have the least number of capacitors among the three types but require additional
clamping diodes.
The diode clamped inverter, particularly the threelevel one, has drawn much interest
in motor drive applications because it needs only one common voltage source. Also,
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simple and efficient PWM algorithms have been developed for it, even if it has
inherent unbalanced dclink capacitor voltage problem. However, it would be a
limitation to applications beyond fourlevel diode clamped inverters for the reason
of reliability and complexity considering dclink balancing and the prohibitively
high number of clamping diodes. Multilevel PWM has lower dv/dt than that
experienced in some twolevel PWM drives because switching is between several
smaller voltage levels.
THEORETICAL ANALYSIS
Below is the diagram of a three level diode clamped inverter. The diodes DZ1 and
DZ2 are the clamping diodes. The switches S1, S2, S3 and S4 control the operation
of the inverter and the line voltage VAZ is dependent on them.
Fig 1 Three level diode Clamped Inverter
The operating status of the switches in the 3 level inverter can be represented by
switching states shown in table below. Switching state ‘1’ denotes the switch ‘ON’
if the upper two switches S1 and S2 are On the inverter terminal voltage VAZ,
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which is the voltage at terminal A with respect to the neutral point Z, is +E,
whereas the lower two switches S3 and S4 conduct, leading to VAZ = –E.
Switching state ‘0’ signifies that the switch ‘OFF’ and VAZ is clamped to zero
through the clamping diodes ie when the switches S2 and S3 are ‘ON’. Depending
on the direction of load current iA, one of the two clamping diodes is turned on. For
instance, a positive load current (iA > 0) forces DZ1 to turn on, and the terminal A is
connected to the neutral point Z through the conduction of DZ1 and S2. It can be
observed from Table that switches S1 and S3 operate in a complementary manner.
With one switched on, the other must be off. Similarly, S2 and S4 are a
complementary pair as well.
S1 S2 S3 S4 VAZ
1 1 0 0 E
0 1 1 0 0
0 0 1 1 E
Table 1 Switching states of three level Inverter
Fig 2 Four Level Diode Clamped Inverter
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The fourlevel diode clamped inverter. The inverter is composed of six active
switches and a number of clamping diodes per phase. The dc capacitors Cd are
shared by all three phases. It is assumed in the following analysis that the voltage
across each capacitor is E and the total dc voltage Vd is equally divided by the
capacitors (Vd = 3E). The switch operating status and the inverter terminal voltage
VAN of the fourlevel inverter are summarized below.
S1 S2 S3 S1

S2

S3

VAN
1 1 1 0 0 0 3E
0 1 1 1 0 0 2E
0 0 1 1 1 0 E
0 0 0 1 1 1 0
Table 2 Switching state of four level inverter
Where ‘1’ signifies that an active switch is turned on while “0” indicates that the
switch is off. When the top three switches in leg A are on (S1 = S2 = S3 = “1”), VAN
is 3E whereas the conduction of the bottom three switches makes VAN to be zero.
When the inverter terminal A is connected to node X or Y of the capacitor circuit
through the conduction of the middle three switches and clamping diodes, VAN will
be equal to 2E or E. Clearly, the waveform of VAN is composed of four voltage
levels: 3E, 2E, E, and 0. It can also be observed from the table that in the fourlevel
inverter, three switches conduct at any time instant and switch pairs (S1, S_ 1), (S2,
S_ 2), and (S3, S_ 3) operate in a complementary manner. It should be pointed out
that the clamping diodes may withstand different reverse blocking voltages. For
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instance, when the inverter operates with S1 = S2 = S3 = “1”, the anode of the
clamping diodes D1 and D2 is connected to the positive dc bus. The voltage
applied to D1 and D2 is then E and 2E, respectively. In practice, the voltage rating
for all the clamping diodes is normally selected to be the same as the active
switches. As a result, two diodes should be in series for D2 (denoted by D2 × 2 in
the figure). The two inverters shown above can be modulated using the IPD or the
APOD modulation schemes.
In Phase Disposition 2 carrier waveforms in phase are arranged for a three level
inverter and 3 carrier waves are arranged for four level inverter.
The following formula is applicable to sub harmonic PWM strategy i.e. IPD and
APOD The frequency modulation index mf = fcr/fm The Amplitude modulation
index m
a
= 2 x A
m
/ (m1) A
c
Where
fc – Frequency of the carrier signal
fm – Frequency of the reference signal
Am –Amplitude of the reference signal
Ac – Amplitude of the carrier signal
m – Number of levels.
The frequency and amplitude modulation is adjusted by adjusting the amplitude
and frequency values of the respective Simulink blocks. The rules for Alternate
Phase opposite disposition is same except for the opposite waves are in phase.
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CALCULATIONS
A1) The Value input voltage Vd for ma = 1 is
Vd =
Vrms
0.707
=
6.6 x 10e3
0.707
= 9335 V
A2) Base Power =
5
3
=1.66x10
6
VA/phase
Base Voltage =
6.6
√3
= 3.81x10
3
V/phase
Base Current =
= 435.69A
Base Impedance =
Base Voltage
Base Current
=
3.81x10e3
435.69
= 8.744Ω
Since it is RL balanced Load.
Base Resistance = 8.744Ω
Base Inductance =
8.744
2xπx60
= 0.023196H = 23.19mH
Power Factor = 0.95
Power Factor =
Apparent Power
0.95 =
1.66x10e6
True Power (Pt) = 1.58 x 10
6
Load resistance =
Pt
=
(3.81103)2
1.58x10e6
= 9.18 Ω
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Load Inductance =
9.18
2xπx60
= 0.02437 H = 24.37mH.
B1). The Simulation results using In Phase Disposition modulation scheme f m =
60, fcr = 900 and ma = 1.0 are as shown below
Arranged as (vg1, vg2, vAN, vAB, and iA) respectively.
Harmonic spectra of vAB
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and iA
B2) scheme f m = 20, fcr = 900 and ma = 0.3
Arranged as (vg1, vg2, vAN, vAB, and iA) respectively.
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Harmonic spectra of vAB
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And harmonic spectra of iA shown below
C1)
The Simulation results using Alternate Phase Opposition Disposition modulation
scheme f m = 60, fcr = 900 and ma = 1.0 are as shown below
Arranged as (vg1, vg2, vAN, vAB, and iA) respectively.
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Harmonic spectra of vAB
and iA
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C2) scheme f m = 20, fcr = 900 and ma = 0.3
Arranged as (vg1, vg2, vAN, vAB, and iA) respectively.
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Harmonic spectra of vAB
And harmonic spectra of iA shown below
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Analysis:
The inverter conditions are same the only change is the modulation scheme. In part
C1 we can observe the vAB THD for C1 is 39.86% which is higher than the vAB THD
for B1 which is 34.83%. Also the higher order harmonics are more prominent in C1
than that of B1. On the other hand when we compare the iA THD for C1 is 17.37%
which is also slightly higher than the THD for B1 which is 17.17%. This proves that
B1 which uses IPD modulation scheme gives a much better harmonic profile than
APOD.
Also on general comparison between the waveforms obtained at various modulation
indices. It is found that the harmonics are much better at higher modulation index as
in the case C1 and B1 than the lower modulation index (C2, B2) This is probably
because as the modulation index increases the Amplitude of the modulating wave is
greater.
D1) Four level Inverter with IPD modulation scheme.
The Simulation results using In Phase Disposition modulation scheme f m = 60, fcr
= 900 and ma = 1.0 are as shown below
Arranged as (vg1, vg2, vAN, vAB, and iA) respectively.
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Harmonic spectra of vAB
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and iA
D2) scheme f m = 20, fcr = 900 and ma = 0.3
Arranged as (vg1, vg2, vAN, vAB, and iA) respectively.
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Harmonic spectra of vAB
And harmonic spectra of iA shown below
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Analysis
On comparing the three level and four level inverters under the same modulating
scheme and operating conditions it is observed that the iA THD of D1 is 13.17%
which is much lower than the iA THD of B1 which is 17.17%. Also the harmonics
vAB of D1 is 29.01% which is much lower than the vAB THD of B1 34.83%. This
shows that the higher level filters have lower THD than the lower level filters.
However it comes at a cost as the higher level filters become increasingly difficult
to design as they employ more clamping diodes than the lower level diodes.
However when the waveforms at lower modulation indices are compared it is found
that the four level inverters (D2) have a little lower iA THD than the three level
inverter (B2). Though it is a little lower the corresponding Current waveforms are
almost the same. But the vAB THD of D2 is a lot lower than that of B2.
CONCLUSION
Thus, a simple Matlab Simulink model is built to implement a three level and four
level diode clamped inverter. A brief overview of the modulation scheme is
explained and the IPD and APOD modulation schemes are tested on both the
inverters. A Matlab/Simulink based model for implementation is presented in the
appendix that follows. The simulations are done for varying values of ma, fm and fcr.
Also the values of are plotted in the sequence specified in the book. The presented
model gives an insight into the multilevel inverters and the modulation schemes
employed thereof. By varying the magnitude of the carrier and modulating wave the
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different modulation index can be achieved. Also the carrier frequency and the
frequency of the modulating wave is specified. From the results obtained it can be
concluded that the IPD scheme gives an overall better harmonics than APOD. Also
the Four level inverter gives much lower THD than the three level inverter.
APPENDIX
TopLevel block diagram of the three level Inverter.
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Three level Diode clamp inverter implementation.
In phase disposition modulation scheme implementation.
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Alternative phase opposite disposition implementation.
Top level diagram of four level inverter.
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Four level diode clamped inverter implementation.