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ELECTRICAL AND ELECTRONIC ENGINEERING

Intel 8086 Instruction


Format
The 8086 instruction size vary from 1-6 bytes as shown in figure 1(a)
yte 1
!ccu"ies 6 bits #efining the o"eration carrie# out by the instruction
$ bit #efines whether o"eran# in byte % is source or #estination register& $'1( #estination register&
) wor# *byte o"eration& )'0 8 bit #ata hence 8 bit o"eration
yte %
+ontains three fiel#s
o ,o#e (,!$)- s"ecifies whether o"eran# is a register or memory& .efer figure 1 (b)&
o .egister (./0) #efines the first o"eran# which is s"ecifie# by the $ fiel# as source or
#estination& .efer figure 1 (c)
o .*, fiel# together with ,!$ fiel# #efines the secon# fiel#& $e"en#ing on the mo#e fiel#(
.*, fiel# will in#icate the #irection of the instruction will ta1e& If ,!$ selects memory then
.*, in#icates how the effective a##ress will be calculate#& Figure % gives the combinations of
byte % instruction formulations&
yte 2 through 6
!"tional fiel#s that normally contain the #is"lacement value of the memory o"eran# an# *or the actual
value of an imme#iate constant o"eran#&
/3am"les-
z ,!4 +5( 6 o"-co#e'100010( if $'0 hence register s"ecifie# by ./0 in byte % is a source
o"eran#& In byte % since the secon# o"eran# is a register then ,!$'11 an# .*,'101& The
instruction'10001000 11011101 (byte 1 byte %) ' 88$$
1
Ty"es
Intel 8086 categorises the instructions into si3 ty"es namely Transfer( arithmetic( logic( 7um"s( misc an#
"rocessor control grou"s&
Transfer grou"- transfers #ata to or from registers from or to memory* I! #evices&
8rithmetic grou"-$oes com"utational activities an# any shifting or rotation re9uire# #uring com"utation&
6ogic grou"- $oes an# logic o"erations re9uire# on o"eran#s
:um" * 6oo" grou"- +on#ition or uncon#itional 7um"s * loo"s as well as branching from the main "rogram
belong to this grou" of instructions
,iscellaneous (,isc) g"- contains instructions li1e ;!< (no o"eration)( 6/8 (loa# effective a##ress) an# I;T
(interru"t)&
<rocessor control grou"- =se# to #irectly control the state of some flags( to #isable * enable interru"ts an# to
synchronise the "rocessor to e3ternal "eri"herals& These instructions inclu#e> ?T+
(set carry flag)( +6+ (clear carry flag( +,+ (com"lement the state of carry flag)(
?T$ (set #irection flag ($F) to 1 or #ecrement string "ointer( )8IT( +6$( ?TI( +6I(
56T( /?+( 6!+@& Refer to instruction set provided.
Flowcharts
)hen a "rogrammer is confronte# by a com"le3 tas1 there is nee# to brea1 #own the tas1 into smaller
manageable units& !ne metho# of brea1ing involves #evelo"ing an# outline of each unit& The outlines are then
se9uence# to allow the "roblem be solve# correctly& !ne metho# of outlining the "roblem is by use of
flowcharts& 8 flowchart is a bloc1 #iagram using stan#ar# symbols to re"resent o"erations& ?ome of the symbols
are shown below&
%
Addressin !odes
The "ower of any instruction set is base# on the ty"es of instructions an# the number of a##ressing mo#es& The
8086 has 1% basic a##ressing mo#es that can be grou"e# into five namely-
1& 8ccessing imme#iate an# register #ata (.egister an# imme#iate mo#es)
%& 8ccessing #ata in memory (,emory mo#es)
2& 8ccessing I*! "orts (I*! mo#es)
A& .elative a##ressing mo#e
B& Im"lie# a##ressing mo#e
Reister and i""ediate "odes
The register a##ressing mo#e uses registers as source an# #estination& Imme#iate a##ressing has the 8- or
16-bit #ata s"ecifie# by the instruction& N# /ven though the #ata is s"ecifie# in the instruction( the #ata
must be locate# in the memory a##resse# by the 8086 +? an# I< registers&
!e"or$ "odes
/3ecution unit (/=) has #irect access to all registers an# #ata for registers an# imme#iate o"eran#s& 5owever
the /= cannot access the memory o"eran#s& It must use the I=& The I= generates the "hysical a##ress from
the effective an# +? base a##ress& There are si3 (6) a##ressing mo#es in this category&
%. Direct "e"or$ addressin
8 16-bit effective a##ress is ta1en #irectly from the #is"lacement fiel# of the instruction& The
#is"lacement may be 16-bit (unsigne#) or 8-bit signe# is store# in the location following the instruction
o"-co#e& This /8 is the #istance of the memory location from the current value of the #ata segment&
/3am"le
,!4 C%0005D(8E >/8 is %0005 being the !FF?/T value in $?&
&. Reister Indirect Addressin
In this mo#e( the /8 is s"ecifie# in either a "ointer or an in#e3 register& <ointers are E an# < while
In#e3 registers are (?I) an# ($I)&
/3am"le-
,!4 C$ID(E > The inst& +o"ies contents of E (as register) into an /8 location given by $I
'. #ased Addressin
The /8 is generate# by a##ing a #is"lacement (unsigne# 16-bit or signe# 8-bit) value to the contents of
E or <& The segment registers are $? an# ??& )hen memory is accesse#( use E an# $? while
when the ?tac1 is accesse# use < an# ??& The stac1 can be accesse# by the "rogrammer without
affecting its o"erations since ?< is not interfere# with&
/3am"le-
,!4 86( 86<58 CED >86<58 is an 8-bit #is"lacement while E contains /8&
(. Inde)ed Addressin
The /8 is calculate# by a##ing a #is"lacement (unsigne# 16- or signe# 8-bit) to the contents of $I or
?I
/3am"le-
,!4 5( ?T8.T C?ID> contents "ointe# by $? F /8 (#is"lacement ?T8.T F ?I) co"ie# to
5
*. #ased Inde)ed Addressin
/8 is com"ute# by a##ing the base register (E or <)( an In#e3 register (?I or $I)( an# a
#is"lacement (unsigne# 16-or signe# 8-bit)&
/3am"le-
,!4 86<58 C?ID CED( +6&
ase# In#e3e# a##ressing mo#e "rovi#es a convenient way for a subroutine to a##ress an array
allocate# on a stac1&
2
++ For ,oth ( and * addressin "odes EA-RA.! where RA is reference address and !
the "odifier.
/. 0trin Addressin
=ses in#e3 registers& The string instructions assume ?I to "oint to the first byte or wor# of the
source o"eran# an# $I to "oint to the first byte or wor# of #estination o"eran#& The contents of ?I an#
$I are automatically incremente# (by clearing $F to 0 by +6$ instruction) or #ecremente# (by setting
$F to 1 by ?.$ instruction)& ?egment register for the source is $? but can be overri##en while the
#estination segment is /? that cannot be overri##en& $I must always "oint to the #estination o"eran#&
$F'0( C$?D '%0005( C?ID'0B005( C/?D'A0005( C$ID'02005( %0B005'285& The value 285
is move# to (/? (A0000 shifte# A left) F$I (offset 02005) A02005
1. Input output 2I3O4 Addressin
There are two ty"es of I*! a##ressing- $irect an# In#irect&
$irect "ort mo#e
The "ort number is an 8-bit imme#iate o"eran# (0-%BB access "orts)
o /3am"le- !=T 0B5(86> contents of 86 out"ut to 8-bit "ort 0B5
In#irect "ort mo#e
<ort number is ta1en from $E allowing 6A@ 8-bit "orts or 2%@ 16-bit "orts
o /3am"le- $E'B0005( then I; 86( $E> 8-bit contents from
B000 "ort to 86& If instruction is- I; 8E( $E> "ort B0005
an# B001 are loa#e# to 86 an# 85 res"ectively&
GG An$ transfers "ust alwa$s use AL or A5.
6. Relative Addressin
This mo#e of a##ressing re9uire a signe# 8-bit #is"lacement relative to <+
/3am"le- :;+ ?T8.T> 7um" if no carry I< F 8-bit signe# value of ?T8.T& !therwise ne3t
instruction is e3ecute#&
7. I"plied Addressin
This mo#e of a##ressing has no o"eran#s& /3am"le +6+> clears carry flag to zero& !ther e3am"les are
+6$( ?T$( /?+( 6!+@( ;!<( )8IT( an# +6I&
++ Notice the flow of readin or decodin an instruction8 fro" riht to left. ++
9irtual !e"or$
Is the memory management techni9ue that allows all memory (main an# mass storage #evices) to be
a##resse# as "art of one large logical a##ress s"ace& The logical a##ress s"ace is larger than the
micro"rocessorHs "hysical a##ress s"ace&
)hen the micro"rocessor out"uts an a##ress( the ,,= fetches the #escri"tor for the a##resse# "age or
segment& The #escri"tor inclu#es a bit that in#icates if the re9ueste# #ata is "resent in main memory or
if it is in mass storage #evices& ,,= aborts current instruction if the #ata is not in the main memory
an# re9uests the !? to rea# the re9uire# "age from the mass storage #evice& 8fter rea#ing the "age
into the main memory( the instruction can be restarte# or continue#& The a""lication "rogram #oes not
#istinguish between #ata or co#e in the main memory an# in mass storage& 8#vantage is that larger
"rograms than main memory can be e3ecute# through swa""ing of "ages&
A