You are on page 1of 7

ELECTRICAL AND ELECTRONIC ENGINEERING

Memory Mapping
The way in which the various memory chips are arranged within the available address space is
described as a system memory map. This map illustrates how ROM, RAM and I/O chips are
distributed throughout the memory.
Not all the available space is normally used and in some microcontroller systems some overwrite may
also be present. Overwrite occurs when only limited address decoding is used so that a memory I
can have an !image" space within the memory map.
Memory map is usually divided into #$ or %$ bloc&s. The bloc&s can 'urther be divided into pages.
(loc&s o' addressing can also be assigned on a 'unctional basis. )hen this is done, it is *uite possible
that a 'unctional bloc& may cross the boundary into another chip. It is also possible to have more than
one 'unctional bloc& o' addresses assigned in a single memory chip.
Linear Decoding
+ses unused address lines o' the microprocessor as chip select lines 'or the memory chips.
Although the #, bit address bus can be connected to ,%$ bytes o' memory, only ,$ o' memory can
be connected using this method o' decoding.
I' unused address lines are not utilised in the chip select, the !don"t care" lines causes a waste o'
memory and con'usion since the same memory location can be addressed by various address
locations. -.g. I' A#. is not connected, //// and 0/// are same location causing 'old bac& o'
memory.
1
hip 1elect 2ines Address 2ines 3evice 1elected Address Assignment
A#.4A## A#/
///// #
///// #
A54A/
//////////
##########
6I7 / /%//
899
////# /
////# /
//////////
########## 6I7 #
/0//
/(99
///#/ /
///#/ /
//////////
########## 6I7 :
#///
#;99
//#// /
//#// /
//////////
########## 6I7 ;
:///
:;99
/#/// /
/#/// /
//////////
########## 6I7 %
%///
%;99
#//// /
#//// /
//////////
########## 6I7 .
0///
0;99
Example 1
A %$( memory in a microprocessor system consists o' ; RAM and one ROM chip where each is
#$(. 3raw the memory address map 'or this scheme. Assign the proper starting and end 'or each chip
and the 'unction allocated to each chip. 9igure : shows the memory mapping and address allocation
'or each.
Example 2
A %$ -7ROM chip and two RAM chips are used in a #,$ memory scheme. The top %$ memory
addresses are saved 'or 'uture e<pansion. -7ROM contains subroutines, tables and constants in the
ne<t %$ bloc&. The lowest 0$ memory is allocated to the two RAM chips 'or the user. 3raw the
address mapping.
2
1ince all 'our chips can store %/5, bytes, we can divide the chips and reserved space into 'our pages
o' %$ each as shown in 'igure ;.
Not all mapping have e*ual memory allocations. It is 'or the designer to address the memories
se*uentially avoiding sparsely distributed address space.
Decoding and Decoders
A microcomputer may contain several RAM, ROM chips in addition to a number o' I/O chips. )hen
memory is to be addressed, the address output by the microprocessor must be able to select the
desired chip. 1ignals associated with selection o' memory/ I/O in con=unction with other bits o' the
address must be used to select the >chip select? 1 or >chip enable? - 'or the particular chip.
3ecoders are normally used 'or this purpose. 3ecoders have their own chip enable signals that need to
be active when using them as select devices.
Non-Asol!"e Address Decoding
)hen a decoder is used 'or selecting memory chips, there may arise a situation that not all the address
lines are used by the decoder. This is termed as non absolute decoding. Re'er to 'igure %.
Asol!"e decoding >#!lly Decoding$
Absolute decoding happens when all the address lines are used 'or the purpose o' decoding.
1election o' memory chips can e''ectively be done by decoder devices. )henever a speci'ic code is
input to a decoder, only the output line corresponding to the input code is activated. The remaining
output lines are deactivated. )e are thus able to select a particular chip depending on the input
combination o' the select signals. Re'er to 'igure . and ,.
I%O In"er&aces
These are modes o' addressing where various I/O devices are inter'aced to the microprocessor. There
are two methods namely Memory mapped I/O or Isolated I/O techni*ues.
Memory4Mapped I/O
This techni*ue treats all I/O device addresses as memory addresses.
3
Example '
A hardware designer is to inter'ace a %$( o' -7ROM and three :$( o' RAM to an Intel 0/0,
microprocessor.
#? 3esign the hardware pieces 'or the system
:? 3raw the address mapping 'or the system.
1olution@ 9igure 8 shows the hardware pieces while Table : shows the address mapping
4
6I7 A#. AA#: A## A A0 A8 A A% A; AA/ Address
5
RAM# ////
////
////
/###
/
9
/
9
////6
/8996
RAM : ///#
///#
////
/###
/
9
/
9
#///6
#8996
RAM ; //#/
//#/
////
/###
/
9
/
9
:///6
:8996
-7ROM //##
//##
////
####
/
9
/
9
;///6
;9996
Example (
An eight bit microprocessor is inter'aced to two >:? :$ ROM chips, 'our >%? %$ RAM chips
and one peripheral device. Assuming the memories have typical access /control signals@
#? 3esign the hardware pieces 'or the system
:? 3raw the address mapping 'or the system. >#; mar&s?
Address Mapping
6
6I7 A#.4A#: A##4A0 A84A% A;4A/ Address
ROM # )
)
* ) ) )
* 1 1 1
)
#
)
#
))))+
),##+
ROM : 1
1
* ) ) )
* 1 1 1
)
#
)
#
1)))+
1###+
RAM # 2
2
)
#
)
#
)
#
2)))+
2###+
RAM : '
'
)
#
)
#
)
#
')))+
'###+
RAM ; (
(
)
#
)
#
)
#
()))+
(###+
RAM % -
-
)
#
)
#
)
#
-)))+
-###+
0:.. 77I .
.
* * **))
**)1
**1)
**11
.)))+
.))1+
.))2+
.))'+
Table # ( mar/s
Need to determine the number o' address lines re*uired 'or the types o' memory devices.
The don"t care states have been assumed to be Beros. ' mar/s
01ado2 RAM and 3IO0
(IO1 routines 'or accessing to 'loppy and hard dis& drives or the graphic adapters are located in
ROM. Moreover, these routines are 're*uently called by the operating system or application programs
and thus slow program e<ecution.
1hadowing is the process o' moving code or data 'rom the slow ROM into 'aster main memory
>Ta&ing 3RAM, RAM, -7ROM/ROM access times are 8/, :. and ://n1 respectively?.
Re4!iremen"s5
#. 1o'tware that does the trans'er
:. Memory controller to map ROM address space onto the RAM area to which the ROM data
have been moved.
Re*uirement >#? is carried out by (IO1 during booting while >:? is carried out by memory controller
that maps the RAM area onto the address o' the original ROM address.
)ith most memory controllers you can move individual sections o' ROM address space into the
shadow RAM. Cou may move (IO1 reserved 'or -DA and EDA to shadow RAM. It is sometimes
impossible to map certain parts o' the ROM address space. This applies to 1mall omputer 1ystem
Inter'ace >11I? host adapters which carry out memory mapped I/O 'or data trans'er between 7 and
11I. Never map the address area o' a 11I host adapter that uses memory mapped I/O onto the
shadow RAM.
Expanded Memory 0peci&ica"ion or E6 Memory 0ys"em 7EM0$
This e<tra memory >up to ,%$b? inserted into the 'irst megabyte o' real mode operation o' the
microprocessor. The siBe can be set by =umpers or (IO1 setup program. The area between ,%/$b and
#Mb reserved 'or ROM is used. on'irm that the entire memory section occupied by -M1 is really
'ree, otherwise address con'licts occur and the 7 would crash. -M1 window is divided into pages
with each having #,$b at most. The start address o' each page can be de'ined by so'tware commands
that control the logic o' the e<panded memory such that each page can be moved within the much
larger physical e<panded memory.
7