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NOTE: For detailed information on purchasing options, contact your

local Allegro field applications engineer or sales representative.


Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a
product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information
included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result from its use.
Recommended Substitutions:
BiMOS II Latched Drivers
A5800 and A5801
For new customers or new applications, refer to the A6800 and A6801.
Date of status change: October 31, 2005
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Discontinued Product
UCN5800A
BiMOS II LATCHED DRIVERS
UCN5800L
Always order by complete part number, e.g., UCN5801EP .
The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOS ICs
merge high-current, high-voltage outputs with CMOS logic. The CMOS
input section consists of 4 or 8 data (D type) latches with associated com-
mon CLEAR, STROBE, and OUTPUT ENABLE circuitry. The power
outputs are bipolar npn Darlingtons. This merged technology provides
versatile, flexible interface. These BiMOS power interface ICs greatly benefit
the simplification of computer or microprocessor I/O. The UCN5800A and
UCN5800L each contain four latched drivers; the UCN5801A, UCN5801EP,
and UCN5801LW contain eight latched drivers.
The UCN5800A/L and UCN5801A/EP/LW supersede the original
BiMOS latched-input driver ICs (UCN4400A and UCN4801A). These
second-generation devices are capable of much higher data input rates and
will typically operate at better than 5 MHz with a 5 V logic supply. Circuit
operation at 12 V affords substantial improvement over the 5 MHz figure.
The CMOS inputs are compatible with standard CMOS and NMOS
circuits. TTL circuits may mandate the addition of input pull-up resistors.
The bipolar Darlington outputs are suitable for directly driving many periph-
eral/power loads: relays, lamps, solenoids, small dc motors, etc.
All devices have open-collector outputs and integral diodes for
inductive load transient suppression. The output transistors are
capable of sinking 500 mA and will withstand at least 50 V in the OFF state.
Because of limitations on package power dissipation, the simultaneous
operation of all drivers at maximum rated current can only be accomplished
by a reduction in duty cycle. Outputs may be paralleled for higher load
current capability.
The UCN5800A is furnished in a standard 14-pin DIP; the UCN5800L
and UCN5801LW in surface-mountable SOICs; the UCN5801A in a 22-pin
DIP with 0.400" (10.16 mm) row centers; the UCN5801EP in a 28-lead
PLCC.
FEATURES
I To 4.4 MHz Data Input Rate
I High-Voltage,
High-Current Outputs
I CMOS, NMOS,
TTL Compatible Inputs
I Output Transient Protection
I Internal Pull-Down Resistors
I Low-Power CMOS Latches
I Automotive Capable
2
3
4
5
6
7 8
9
10
11
12
13
14
SUPPLY
GROUND
CLEAR
OUT
1
OUT
2
OUT
3
Dwg. PP-014A
OUT
4
1
14 1
COMMON
OUTPUT
ENABLE
IN
1
STROBE
IN
2
IN
3
IN
4
V
DD
L
A
T
C
H
E
S
D
a
t
a

S
h
e
e
t
2
6
1
8
0
.
1
0
B
*
ABSOLUTE MAXIMUM RATINGS
at +25C Free-Air Temperature
Output Voltage, V
CE
. . . . . . . . . . . . . . 50 V
Supply Voltage, V
DD
. . . . . . . . . . . . . . 15 V
Input Voltage Range,
V
IN
. . . . . . . . . . . -0.3 V to V
DD
+ 0.3 V
Continuous Collector Current,
l
C
. . . . . . . . . . . . . . . . . . . . . . 500 mA
Package Power Dissipation,
P
D
. . . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
T
A
. . . . . . . . . . . . . . . . -20C to +85C
Storage Temperature Range,
T
S
. . . . . . . . . . . . . . . -55C to +150C
Caution: CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Note the UCN5800A (DIP) and the UCN5800L
(SOIC) are electrically identical and share a
common terminal number assignment.
5800 AND
5801
5800 AND 5801
BiMOS II
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
FUNCTIONAL BLOCK DIAGRAM
Copyright 1985, 2002 Allegro MicroSystems, Inc.
50 75 100 125 150
2.5
0.5
0
A
L
L
O
W
A
B
L
E

P
A
C
K
A
G
E

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N

I
N

W
A
T
T
S
AMBIENT TEMPERATURE IN C
2.0
1.5
1.0
25
Dwg. GP-023-1A
22-PIN DIP, RJA = 56C/W
28-LEAD PLCC, RJA = 68C/W
14-PIN DIP, RJA = 73C/W
14-LEAD SOIC, RJA = 120C/W
24-LEAD SOIC, RJA = 85C/W
COMMON
GROUND
STROBE
OUTPUT ENABLE
IN
N
COMMON MOS CONTROL TYPICAL MOS LATCH TYPICAL BIPOLAR DRIVE
OUT
N
Dwg. FP-016-1
CLEAR
SUPPLY
V
DD
TYPICAL INPUT CIRCUIT
Dwg. EP-010-4A
IN
V
DD
5800 AND 5801
BiMOS II
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at T
A
= +25C, V
DD
= 5 V (unless otherwise noted).
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Leakage Current I
CEX
V
CE
= 50 V, T
A
= +25C 50 A
V
CE
= 50 V, T
A
= +70C 100 A
Collector-Emitter V
CE(SAT)
I
C
= 100 mA 0.9 1.1 V
I
C
= 200 mA 1.1 1.3 V
I
C
= 350 mA, V
DD
= 7.0 V 1.3 1.6 V
Input Voltage V
IN(0)
1.0 V
V
IN(1)
V
DD
= 12 V 10.5 V
V
DD
= 10 V 8.5 V
V
DD
= 5.0 V (See Note) 3.5 V
Input Resistance r
IN
V
DD
= 12 V 50 200 k
V
DD
= 10 V 50 300 k
V
DD
= 5.0 V 50 600 k
Supply Current I
DD(ON)
V
DD
= 12 V, Outputs Open 1.0 2.0 mA
V
DD
= 10 V, Outputs Open 0.9 1.7 mA
V
DD
= 5.0 V, Outputs Open 0.7 1.0 mA
I
DD(OFF)
V
DD
= 12 V, Outputs Open, Inputs = 0 V 200 A
V
DD
= 5.0 V, Outputs Open, Inputs = 0 V 50 100 A
Clamp Diode I
R
V
R
= 50 V, T
A
= +25C 50 A
V
R
= 50 V, T
A
= +70C 100 A
Clamp Diode Forward Voltage V
F
I
F
= 350 mA 1.7 2.0 V
NOTE: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic 1.
Saturation Voltage
Leakage Current
(Each
Stage)
(Total)
1 2 3 4
5
6
7
8
9
10
11
1
2
1
3
1
4
1
5
1
6
1
7
1
8
19
20
21
22
23
24
25
2
6
2
7
2
8
G
R
O
U
N
D
O
U
T
P
U
T
E
N
A
B
L
E
S
T
R
O
B
E
K
S
T
V
D
D
O
E
Dwg. PP-037
L
A
T
C
H
E
S
N
C
N
C
N
C
N
C
N
C
N
C
S
U
P
P
L
Y
L
A
M
P

D
I
O
D
E
C
O
M
M
O
N
C
C
L
E
A
R
OUT
1
I
N
8

O
U
T
8

OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
IN1
IN2
IN3
IN4
IN5
IN6
IN7
UCN5801EP
(additional pinout diagrams
are on next page)
5800 AND 5801
BiMOS II
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
TRUTH TABLE
OUT
N
IN
N
STROBE CLEAR ENABLE t-1 t
0 1 0 0 X OFF
1 1 0 0 X ON
X X 1 X X OFF
X X X 1 X OFF
X 0 0 0 ON ON
X 0 0 0 OFF OFF
X = irrelevant.
t-1 = previous output state.
t = present output state.
OUTPUT
CLEAR
STROBE
OUTPUT
ENABLE
IN
N
OUT
N
A C B C B
G
D E
F
A C B
G
E
TIMING CONDITIONS
(Logic Levels are V
DD
and Ground)
A. Minimum Data Active Time Before Strobe Enabled
(Data Set-Up Time) .......................................................... 50 ns
B. Minimum Data Active Time After Strobe Disabled
(Data Hold Time) .............................................................. 50 ns
C. Minimum Strobe Pulse Width .................................................. 125 ns
D. Typical Time Between Strobe Activation and
Output On to Off Transition ............................................ 500 ns
E. Minimum Time Between Strobe Activation and
Output Off to On Transition ............................................ 500 ns
F. Minimum Clear Pulse Width .................................................... 300 ns
G. Minimum Data Pulse Width ..................................................... 225 ns
Information present at an input is transferred to its latch when the
STROBE is high. A high CLEAR input will set all latches to the output
OFF condition regardless of the data or STROBE input levels. A high
OUTPUT ENABLE will set all outputs to the OFF condition, regardless
of any other input conditions. When the OUTPUT ENABLE is low, the
outputs depend on the state of their respective latches.
Dwg. No. A-10,895A
UCN5801A
2 21
22
SUPPLY
CLEAR 1
OUTPUT
ENABLE
STROBE V
DD
3
4
5
6
7 16
17
18
19
20 OUT
1
OUT
2
OUT
3
OUT
4
IN
1
IN
2
IN
3
IN
4
7
8
9
10
11 12
13
14
15
GROUND
OUT
5
OUT
6
OUT
7
Dwg. PP-015
OUT
8
COMMON
IN
5
IN
6
IN
7
IN
8
L
A
T
C
H
E
S
2 23
24
SUPPLY
CLEAR 1
OUTPUT
ENABLE
STROBE V
DD
3
4
5
6
7
21
22 OUT
1
OUT
2
OUT
3
OUT
4
IN
1
IN
2
IN
3
IN
4
7
8
9
10
11 GROUND
OUT
5
OUT
6
OUT
7
Dwg. PP-015-1
OUT
8
COMMON
IN
5
IN
6
IN
7
IN
8
L
A
T
C
H
E
S
NO
CONNECTION
NO
CONNECTION
NC NC 12 13
18
19
20
14
15
16
17
UCN5801LW
5800 AND 5801
BiMOS II
LATCHED DRIVERS
TYPICAL APPLICATION
UNIPOLAR STEPPER-MOTOR DRIVE
Dwg. No. B-1537
1
2
3
4
5
6
7 8
9
10
11
12
13
14
OUT 2
OUT 3
OUT 4
OUT 1
+30 V
IN 1
IN 2
IN 3
IN 4
STROBE
CLEAR
OUTPUT ENABLE (ACTIVE LOW)
L
A
T
C
H
E
S
UCN-5800A
V
DD
V
DD
+30 V

STROBE
IN 1
IN 2
IN 3
IN 4
OUT 1
OUT 2
OUT 3
OUT 4
Dwg. GP-060
STROBE
IN 1
IN 2
IN 3
IN 4
OUT 1
OUT 2
OUT 3
OUT 4
Dwg. GP-060-1
UNIPOLAR WAVE DRIVE UNIPOLAR 2-PHASE DRIVE
5800 AND 5801
BiMOS II
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
UCN5800A
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Exact body and lead configuration at vendors option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
0.014
0.008
0.300
BSC
Dwg. MA-001-14A in
0.430
MAX
0.100
BSC
14
1 7
0.280
0.240
0.210
MAX
0.070
0.045
0.015
MIN
0.022
0.014
0.005
MIN
0.150
0.115
8
0.775
0.735
0.355
0.204
7.62
BSC
Dwg. MA-001-14A mm
10.92
MAX
14
1 7
7.11
6.10
5.33
MAX
1.77
1.15
0.39
MIN
0.558
0.356
2.54
BSC
0.13
MIN
3.81
2.93
8
19.68
18.67
5800 AND 5801
BiMOS II
LATCHED DRIVERS
NOTES: 1. Exact body and lead configuration at vendors option within limits shown.
2. Lead spacing tolerance is non-cumulative.
0 TO 8
0.3444
0.3367
0.2440
0.2284
0.050
0.016
Dwg. MA-007-14 in
0.050
BSC
0.0098
0.0075
1 2 3
0.1574
0.1497
0.020
0.013
0.0688
0.0532
0.0040 MIN.
14 8
8.75
8.55
6.20
5.80
1.27
0.40
0 TO 8
Dwg. MA-007-14A mm
1.27
BSC
0.25
0.19
1 2 3
4.00
3.80
0.51
0.33
1.75
1.35
0.10 MIN.
14 8
UCN5800L
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
5800 AND 5801
BiMOS II
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
UCN5801A
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Exact body and lead configuration at vendors option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
22
1 2 3 11
9.65
8.39
5.33
MAX
0.070
0.030
28.44
26.67
0.39
MIN
0.558
0.356
2.54
BSC
0.13
MIN
4.06
2.93
0.381
0.204
10.16
BSC
Dwg. MA-002-22 mm
12.70
MAX
12
22
1 2 3 11
0.380
0.330
0.210
MAX
0.070
0.030
0.015
MIN
0.022
0.014
0.100
BSC
0.005
MIN
0.160
0.115
0.015
0.008
0.400
BSC
Dwg. MA-002-22 in
0.500
MAX
12
1.120
1.050
5800 AND 5801
BiMOS II
LATCHED DRIVERS
UCN5801EP
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Exact body and lead configuration at vendors option within limits shown.
2. Lead spacing tolerance is non-cumulative.
18 12
0.020
MIN
0.050
BSC
1 28
INDEX AREA
Dwg. MA-005-28A in
0.026
0.032
0.013
0.021
26
25
19 11
4
5
0.165
0.180
0.495
0.485
0.456
0.450
0.495
0.485
0.456
0.450
0.219
0.191
0.219
0.191
0.51
MIN
4.57
4.20
1.27
BSC
12.57
12.32
11.582
11.430
1 28
INDEX AREA
Dwg. MA-005-28A mm
0.812
0.661
0.331
0.533
12.57
12.32
26
25
19
18 12
11
4
5
11.58
11.43
5.56
4.85
5.56
4.85
5800 AND 5801
BiMOS II
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
UCN5801LW
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
NOTES: 1. Exact body and lead configuration at vendors option within limits shown.
2. Lead spacing tolerance is non-cumulative.
0 TO 8
1 2 3
0.020
0.013
0.0040 MIN.
0.0125
0.0091
0.050
0.016
Dwg. MA-008-24A in
0.050
BSC
24 13
0.2992
0.2914
0.419
0.394
0.6141
0.5985
0.0926
0.1043
0 TO 8
1
24
2 3
0.51
0.33
0.10 MIN.
0.32
0.23
1.27
0.40
Dwg. MA-008-24A mm
1.27
BSC
13
7.60
7.40
10.65
10.00
15.60
15.20
2.65
2.35
5800 AND 5801
BiMOS II
LATCHED DRIVERS
This page intentionally left blank
5800 AND 5801
BiMOS II
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
POWER
INTERFACE DRIVERS
Function Output Ratings* Part Number

SERIAL-INPUT LATCHED DRIVERS


8-Bit (saturated drivers) -120 mA 50 V 5895
8-Bit 350 mA 50 V 5821
8-Bit 350 mA 80 V 5822
8-Bit 350 mA 50 V 5841
8-Bit 350 mA 80 V 5842
8-Bit (constant-current LED driver) 75 mA 17 V 6275
8-Bit (constant-current LED driver) 120 mA 24 V 6277
8-Bit (DMOS drivers) 250 mA 50 V 6595
8-Bit (DMOS drivers) 350 mA 50 V 6A595
8-Bit (DMOS drivers) 100 mA 50 V 6B595
10-Bit (active pull-downs) -25 mA 60 V 6810
12-Bit (active pull-downs) -25 mA 60 V 5811
16-Bit (constant-current LED driver) 75 mA 17 V 6276
20-Bit (active pull-downs) -25 mA 60 V 6812
32-Bit (active pull-downs) -25 mA 60 V 6818
32-Bit 100 mA 30 V 5833
32-Bit (saturated drivers) 100 mA 40 V 5832
PARALLEL-INPUT LATCHED DRIVERS
4-Bit 350 mA 50 V 5800
8-Bit -25 mA 60 V 5815
8-Bit 350 mA 50 V 5801
8-Bit (DMOS drivers) 100 mA 50 V 6B273
8-Bit (DMOS drivers) 250 mA 50 V 6273
SPECIAL-PURPOSE DEVICES
Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259
Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V 6A259
Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259
Addressable 28-Line Decoder/Driver 450 mA 30 V 6817
* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
Complete part number includes additional characters to indicate operating temperature range and package style.
Internal transient-suppression diodes included for inductive-load protection.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from
the detail specifications as may be required to permit improvements in the design of its products.
The information included herein is believed to be accurate and reliable. However, Allegro
MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or
other rights of third parties which may result from its use.