ATOM 20100909 D-Wave Unit Cell Overview I Richard Harris

Experimental Investigation of an Eight Qubit Unit Cell
in a Superconducting Optimization Processor

Part I: Hardware Design
Richard Harris, Fabio Altomare, Andrew Berkley, Paul Bunyk,
Suz Gildert, Mark Johnson, Eric Ladizinsky, Trevor Lanting
and Elena Tolkacheva
D-Wave Systems Inc.
Burnaby, BC Canada
September 2010
Primary Reference: Harris et al., Phys. Rev. B 82, 024511 (2010)
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 1 / 45
Outline
1
Introduction to Quantum Annealing (QA)
2
Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3
Scalable Control and Readout Architecture
4
Summary
Outline
1
2
Interqubit Couplers
Inductance Tuner
Readout
3
4
Summary
Spin-1/2 in a Magnetic Field
An otherwise free spin-1/2 subjected to a magnetic eld:
=0
=-g
B
B
z
B=Bz
Spin-1/2
c
c
c
c
,
Energy eigenstates are coincident with the spin basis (| ,| ),
independent of eld orientation.
Ising Spin in a Magnetic Field
Consider a spin-1/2 at the center of a tetragonal crystal unit cell. Crystal
eld (symmetry) constrains spin to point along longest axis.
=
cf
=-g
B
(
B
ll
z
+B
t
x
)
B
ll
c
c
c
c
,
B
t
Spin-1/2 in a
tetragonal crystal
+
c
c

Field orientation matters:
For B
t
B
||
, ground state is (| +| )/
2.
For B
t
B
||
, ground state is either | or | .
Ising Spin Glass (ISG)
A non-magnetic crystal with randomly distributed spin-1/2 dopants.
Ising Spin Glass (ISG)
A non-magnetic crystal with randomly distributed spin-1/2 dopants.
J
12
J
23
J
13
H
ISG
=
i ,j >i
J
(i )
z

(j )
z
Spin-spin interactions give rise to interactions J
with random sign and

magnitude. Ground state is disordered (glassy).
Finding the Ground State via Quantum Annealing (QA)
Finding the ground state of an ISG is experimentally challenging. One
approach is to use B
t
to perform quantum annealing (QA):
B
t
pJ
ij
/g
B
J
12
J
23
J
13
H
QSG
g
B
B
t
(i )
x
t
B
t
~ J
ij
/g
B
J
12
J
23
J
13
H
QSG
=
i ,j >i
J
(i )
z

(j )
z
g
B
B
t
(i )
x
t
B
t
`J
ij
/g
B
J
12
J
23
J
13
H
QSG

i ,j >i
J
(i )
z

(j )
z
t
B
t
=0
J
12
J
23
J
13
H
ISG
=
i ,j >i
J
(i )
z

(j )
z
t
B
t
=0
J
12
J
23
J
13
For QA experiments on a bulk ISG (LiHo
x
Y
1x
F
4
) see Brooke et al.,
Science 284, 779 (1999).
Application of Ising Spin Glass Physics
There are commercial applications, such as optimization and machine
learning, that involve solving problems of the form
E(s) =
i
h
i
s
i
+
i ,j >i
K
s
i
s
j
, (1)
where s
i
= 1 and 1 h
i
, K
+1. The optimal solution s

gs
minimizes
E(s). Substituting s
i

(i )
z
yields an ISG Hamiltonian
H
ISG
(t)
E
0
(t)
=
i
h
i
(i )
z
+
i ,j >i
K
(i )
z

(j )
z
, (2)
where E
0
(t) has units of energy. Now |s
gs
is the ground state of an ISG.
Applying a global transverse eld (t) allows one to implement QA:
H
QSG
(t)
E
0
(t)
=
i
h
i
(i )
z
+
i ,j >i
K
(i )
z

(j )
z
(t)
(i )
x
. (3)
See Farhi et al., Science 292, 472 (2001) for details.
Why Implement QA?
Reason 1:
QA is a physically motivated method of harnessing quantum resources.
Moreover, thermodynamics need not always thwart the intended
computation [see Amin et al. Phys. Rev. Lett. 100, 060503 (2008)].
Reason 2:
Valuable real-world optimization problems can be cast as an Ising spin
glass. Why not build hardware that excels at solving such problems?
Reason 3:
Implementing QA is an excellent warmup exercise before implementing
even harder architectures. For example, universal adiabatic quantum
computation [see Biamonte and Love, Phys. Rev. A 78, 012352 (2008)].
Outline
1
2
Interqubit Couplers
Inductance Tuner
Readout
3
4
Summary
Implementing a Programmable QSG
D-Wave builds programmable hardware whose low energy Hamiltonian
H
QSG
(t)
E
0
(t)
=
i
h
i
(i )
z
+
i ,j >i
K
(i )
z

(j )
z
(t)
(i )
x
can be used for solving optimization problems. We have adopted a
top-down approach in which the QSG architecture drives the design.
Specic ingredients that must be incorporated into the hardware:
Quantum Ising spins (qubits) that can be annealed ().
Local biases on each spin (h
i
).
Tunable couplings between spins (K
).
A means of unambiguously reading the nal spin conguration |s.
Additional constraints:
The design must be robust against realistic fabrication variations.
The design must be realistically scalable up to 1000s of qubits.
Analog Components of a QA Processor Qubits (Quantum Ising Spins)
Outline
1
2
Interqubit Couplers
Inductance Tuner
Readout
3
4
Summary
rf-SQUID Flux Qubit
A Josephson junction of critical current I
c
in a superconducting loop of inductance
L
body
. Loop is subjected to an external
ux bias
x
q

0
/2 (
0
h/2e ).
I
c
F
q
x
j
q
L
body
cc
c
Persistent current I
p
q
phase drop
q
:
I
p
q
I
c
sin(
q
) =
q
/2
x
q
L
body
-3 -2 -1 0 1 2 3
0
5
10
15
20
I
q
(mA)
p
E
/
h

(
G
H
z
)
c
c
F
q
= F
0
/2
x
-3 -2 -1 0 1 2 3
0
5
10
15
20
I
q
(mA)
p
E
/
h

(
G
H
z
)
c
c
F
q
t F
0
/2
x
Bistable potential supports two countercirculating states | and | .
Flux Qubits as Quantum Ising Spins
Low energy Hamiltonian is that of a qubit or a quantum Ising spin:
H
q
=
1
2
[
q
z
+
q
x
]
q
= 2
I
p
q
x
q
0
/2
-3 -2 0 2 3
0
5
10
15
20
I
q
(mA)
p
E
/
h

(
G
H
z
)
e
q

1
e
q
2
+D
q
2

F
q
t F
0
/2
x
-|
I
q|
p
+
|
I
q|
p
Parameter Qubit Quantum Ising Spin
q
Bias Energy Longitudinal Field (g
B
)
q
Tunneling Energy Transverse Field (g
B
)
I
p
q
Persistent Current g
B
I
p
q
and
q
are the dening properties of any ux qubit.
CCJJ Flux Qubit
We use a compound-compound Josephson junction (CCJJ) rf SQUID in
our designs. One can dene a net phase
q
across the entire CCJJ:
I
1
I
2
F
L
x
F
q
x
j
q
I
3
I
4
F
R
x
F
ccjj
x
L
body
L
ccjj
/2 L
ccjj
/2
I
c
F
q
x
j
q
L
body
@
I
c
=Fcn(F
L,
F
R,
F
ccjj
)
x x x
Key advantages of the CCJJ rf SQUID ux qubit:
The ux
x
ccjj
allows one to tune
q
(transverse eld).
The ux biases (
x
L
,
x
R
) can be used to mitigate the eects of
variations in junction critical current, I
1
= I
2
= I
3
= I
4
.
One can homogenize the net I
c
(
x
L
,
x
R
) between multiple CCJJ ux
qubits by carefully choosing (
x
L
,
x
R
).
See Harris et al. Phys. Rev. B, 81 134510 (2010) for details.
CCJJ Flux Qubit Parameters
The CCJJ ux qubit provides tunable
q
(
x
ccjj
) [transverse eld].
However,
I
p
q
x
ccjj
[g
B
] is also altered by this control.
H
q
=
1
2
[
q
z
+
q
x
] ,
q
= 2
I
p
q
x
q
0
q
0.63 0.625 0.62 0.615 0.61

10
5
10
6
10
7
10
8
10
9
10
10
x
ccjj
/
0
q
/
h
(
H
z
)
Bistable
1QLZ
2QLZ
x
ccjj
Locked
2QLZ
x
ccjj
Unlocked
0.65 0.64 0.63 0.62 0.61 0.6 0.59
0
0.25
0.5
0.75
1
1.25
1.5

Bistable Monostable
x
ccjj
/
0
|
I
pq
|
(
A
)
q
0
q
1
q
2
q
3
q
4
q
5
q
6
q
7
Living with this latter phenomenon adds complexity to implementing QA
with ux qubits [see Harris et al., Phys. Rev. B 82, 024511 (2010)].
Analog Components of a QA Processor Interqubit Couplers
Outline
1
2
Interqubit Couplers
Inductance Tuner
Readout
3
4
Summary
Interqubit Couplers
M
ij
Coupler
{
Qubit i Qubit j
F
co
x
M
co,l
M
co,r
3 2 1 0 1 2 3
0
5
10
15
20
3 2 1 0 1 2 3
0
5
10
15
20
0 0.2 0.4 0.6
4
2
0
2

+M
AFM
M
AFM
x
co
/
0
M
i
j
(
p
H
)
A two-junction rf SQUID provides a sign and magnitude tunable mutual
inductance
M
= M
co,l
M
co,r
(
x
co
) ,
where
(
x
co
) represents a tunable linear magnetic susceptibility (units of
H
1
). Maximum antiferromagnetic (AFM) coupling strength is denoted as
M
AFM
. We generally restrict operation M
AFM
M
M
AFM
.
A Network of Inductively Coupled Flux Qubits
Combining multiple qubits and couplers yields a QSG. The low energy
Hamiltonian for general bias conditions can be written as
H
0
(t) =
1
2
i
(t)
(i )
z
+
q
(t)
(i )
x
i ,j >i
J
(t)
(i )
z

(j )
z
. (4)
i
(t) 2
I
p
q
(t)
x
i
(t)
0
i
I
p
q
(t)
2
Eq. (4) has terms of the same symmetry as the QSG Hamiltonian:
H
0
(t)
E
0
(t)
=
i
h
i
(i )
z
+
i ,j >i
K
(i )
z

(j )
z
(t)
(i )
x
(5)
One then needs to choose a convenient E
0
(t) to map problem instances
(h
i
, K
) onto the hardware controls

x
i
(t) and M
. Living with ux qubits

(not real quantum Ising spins) requires additional hardware . . .
Analog Components of a QA Processor Persistent Current Compensation
Outline
1
2
Interqubit Couplers
Inductance Tuner
Readout
3
4
Summary
Mapping ISG Problems onto Hardware (1)
Let us complete the mapping of problem instance specications onto
hardware settings: (h
i
, K
) (
x
i
(t), M
). Dene E
0
(t) M
AFM
|I
p
q
(t)|
2
,
where M
AFM
is the maximum AFM interqubit coupling.
H
0
(t)
E
0
(t)
=
i
h
i
(i )
z
+
i ,j >i
K
(i )
z

(j )
z
(t)
(i )
x
(6a)
Simply solving for QSG parameters h
i
, K
, and (t) yields the following:

h
i
=

i
(t)
2E
0
(t)
=

x
i
(t)
0
i
M
AFM
|I
p
q
(t)|
(6b)
K
=
J
(t)
E
0
(t)
=
M
M
AFM
(6c)
(t) =

q
(t)
2E
0
(t)
=

q
(t)
2M
AFM
|I
p
q
(t)|
2
(6d)
Consider the forms of h
i
, K
, and (t) carefully . . .

First, look at the transverse component that is meant to facilitate QA:
(t) =

q
(t)
2E
0
(t)
=

q
(t)
2M
AFM
|I
p
q
(t)|
2
0.63 0.625 0.62 0.615 0.61
10
5
10
6
10
7
10
8
10
9
10
10
x
ccjj
/
0
q
/
h
(
H
z
)
Bistable
1QLZ
2QLZ
x
ccjj
Locked
2QLZ
x
ccjj
Unlocked
0.65 0.64 0.63 0.62 0.61 0.6 0.59
0
0.25
0.5
0.75
1
1.25
1.5

Bistable Monostable
x
ccjj
/
0
|
I
pq
|
(
A
)
q
0
q
1
q
2
q
3
q
4
q
5
q
6
q
7
Sweeping the ux bias
x
ccjj
from right to left in time t ensures that
(t = 0) 1 and (t = t
f
) 1, thus implementing QA.
Next, look at the problem instance parameters:
K
=
J
(t)
E
0
(t)
=
M
M
AFM
h
i
=

i
(t)
2E
0
(t)
=

x
i
(t)
0
i
M
AFM
|I
p
q
(t)|
0.65 0.64 0.63 0.62 0.61 0.6 0.59
0
0.25
0.5
0.75
1
1.25
1.5

Bistable Monostable
x
ccjj
/
0
|
I
pq
|
(
A
)
q
0
q
1
q
2
q
3
q
4
q
5
q
6
q
7
The problem parameters h
i
and K
are supposed to be time-independent.

This comes out very naturally for K
, but not so for h

i
.
There is an imbalance in h
i
since
i
(t)
I
p
q
(t)
while J
(t)
I
p
q
(t)
2
.
One needs to correct this with
x
i
(t)
0
i

I
p
q
(t)
.
Persistent Current Compensator (IPC)
Flux bias needed to implement persistent current compensation on qubit i :
x
i
(t) = h
i
M
AFM
|I
p
q
(t)| +
0
i
. (7)
0
i
is a trivial static ux oset (more later). Supply the time-dependent
portion via an external current bias I
g
(t) = |I
p
q
(t)| (where 1)
through a tunable mutual inductance
M
i
(
x
IPC
) = h
i
M
AFM
/ (8)
I
g
(t)
M
i
{
IPC
F
IPC
x
F
q
x
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.2
0.15
0.1
0.05
0
0.05
0.1
x
Ip,i
/
0
M
i
(
p
H
)

+M
AFM
/
M
AFM
/
M
0
M
1
M
2
M
3
M
4
M
5
M
6
M
7
For complete details, see Harris et al., Phys. Rev. B 82, 024511 (2010).
Analog Components of a QA Processor Inductance Tuner
Outline
1
2
Interqubit Couplers
Inductance Tuner
Readout
3
4
Summary
Analog Components of a QA Processor Inductance Tuner
Inductance Tuner
Interqubit couplers inductively load the qubits. Changing coupler
i
will
change L
q
, thus altering
q
(
x
ccjj
) (transverse eld) and
I
p
q
(
x
ccjj
)
(g
B
).
n
F
LT
F
LT
x
M
co,1 M
co,n
=
L
body
L
ccjj
/2 L
ccjj
/2
0.4 0.2 0 0.2 0.4
0
4
8
12
16
x
LT
/
0
L
q
(
p
H
)
Provide an inductance tuner (LT) with which one can compensate L
q
to
render
q
(
x
ccjj
) and
I
p
q
(
x
ccjj
)
independent of coupler settings.

L
q
= L
body
+ L
ccjj
/4 +
n
i =1
M
2
co,i
i
+
L
LT
cos
x
LT
/
0
(9)
Analog Components of a QA Processor Readout
Outline
1
2
Interqubit Couplers
Inductance Tuner
Readout
3
4
Summary
Analog Components of a QA Processor Readout
QFP-Enabled Readout
Qubits are localized into | or | by the QA algorithm (
q
0). We
use a quantum ux parametron (QFP) as a type of preamplier of the
qubits nal state to boost the delity to in excess of 99.99% in practice.
i
ro
(t)
QFP
v
ro
(t)
Qubit dc SQUID
F
latch
x
F
ro
x
c
c
Basic readout operation:
1
QFP is annealed in the presence of | or | by ramping
x
latch
from
0
/2 to
0
, thus latching QFP state into its own | or | .
2
Latched state of QFP is then read by a dc SQUID using
conventional switching measurement.
See Berkley et al., arXiv:0905.0891 (2009) for details.
(accepted in Supercond. Sci. Technol.)
Analog Components of a QA Processor Schematic Layout of Analog Components
Outline
1
2
Interqubit Couplers
Inductance Tuner
Readout
3
4
Summary
Ingredients for a QA Processor
The complete qubit has a CCJJ, L tuner (LT),
I
p
q
compensator (IPC),
and readout (RO). Each qubit is subjected to two time-dependent current
biases, I
g
(t) that provides the
I
p
q
-compensation signal and I

CCJJ
that
provides the annealing signal
x
ccjj
(t).
F
ccjj
x
I
g
CCJJ
LT
IPC
RO
Coupler Qubit
Qubits need to be arranged on a lattice connected by couplers to form a
QA processor . . .
Schematic Layout - Eight Qubit Unit Cell
q
0
RO
CCJJ
LT
IPC
Take the CCJJ rf SQUID and stretch out its body.
Replicate four vertical qubits q
0
q
3
spaced evenly apart.
Overlay four horizontal qubits q
4
q
7
.
Overlay internal couplers (ICO) at intersections of qubit bodies.
Overlay portions of external couplers (XCO) at extrema of qubits.
q
0
q
1
q
2
q
3
RO
CCJJ
LT
IPC
0
q
3
4
q
7
.
q
0
q
1
q
2
q
3
q
4
q
5
q
6
q
7
RO
CCJJ
LT
IPC
0
q
3
4
q
7
.
q
0
q
1
q
2
q
3
q
4
q
5
q
6
q
7
RO
CCJJ
LT
ICO
IPC
0
q
3
4
q
7
.
q
0
q
1
q
2
q
3
q
4
q
5
q
6
q
7
RO
CCJJ
LT
ICO
XCO
XCO
IPC
0
q
3
4
q
7
.
Schematic Layout - Multiple Unit Cells
Larger processors are made by tiling the unit cell to the top, bottom, left,
and right. Shown is a 128-qubit 352-coupler array.
Outline
1
2
Interqubit Couplers
Inductance Tuner
Readout
3
4
Summary
A 128-qubit processor requires 1632 control signals to operate. It is not
practical to rout one external bias per signal for many reasons:
Processor must be thermalized to a mixing chamber of a dilution
refrigerator, limited heat load.
Processor active circuit size O(mm
2
), limited room for passing signals
onto chip (wirebonds).
Limited space on chip available for wiring channels. Crosstalk is a
serious issue.
One needs to adopt more ecient strategies for controlling the processor:
Use programmable on-chip non-volatile memory to supply
time-independent biases.
Share currents for time-dependent biases among multiple devices
(works with superconducting circuits).
Control of Qubits and Couplers
Required signals:
5 static (but programmable) ux biases per qubit, 1 per coupler.
2 time-dependent current biases per qubit.

CCJJ Minor
DAC
CCJJ Minor
DAC
L Tuner
DAC
|I
q | Comp.
DAC
p
Qubit Flux
DAC
Coupler
DAC
I
g
(t)
I
ccjj
(t)
F
ccjj
x Qubit
Coupler
We use programmable magnetic memory (PMM) to provide static uxes
and shared current biases to provide the time-dependent signals.
Programmable Magnetic Memory (PMM)
Static ux biases provided by digital-to-analog converters (DACs). Inputs
to DACs store integer ux quanta (
0
h/2e). DACs are addressable by
using a demultiplexing circuit that routs single ux quanta (SFQ). Memory
is non-volatile and demultiplexing circuit is quiet when not in use.
See Johnson et al., Supercond. Sci. Technol. 23, 065004 (2010).
Global Analog Bias Lines
Sharing of current bias lines between multiple qubits provides a signicant
reduction in the number of external biases needed to run the processor.
Annealing Bias I
ccjj
(t)

I
ccjj
(t)
CCJJ
Qubit 1
CCJJ
Qubit 2
CCJJ
Qubit n
I
p
q
-Compensation Bias I
g
(t) =
I
p
q
(t)
I
g
(t)
Body
Qubit 1
Body
Qubit 2
Body
Qubit n
M
1
M
2
M
n
See Johnson et al., Supercond. Sci. Technol. 23, 065004 (2010).
XY Addressable Readout
Use a single common QFP latch across entire chip. Share dc SQUID
current (ux) biases as columns (rows).
c
c
c
c
c
c
c
c
Current Bias
Column 1
Current Bias
Column 2
Flux Bias
Row 1
Flux Bias
Row 2
QFP Latch
RO
11
RO
12
RO
21
RO
22
See Berkley et al., arXiv:0905.0891 for details.
Complete Eight Qubit Unit Cell
q
0
q
1
q
2
q
3
q
4
q
5
q
6
q
7
RO
CCJJ
LT
ICO
XCO
XCO
IPC
q
0
q
1
q
2
q
3
q
4
100 mm
q
5
q
6
q
7
Complete unit cell with PMM circuitry.
Complete Multiple Unit Cells
Complete 128-qubit chip with PMM circuitry.
A Scalable QA Processor Architecture
How well does the architecture scale?
Element Count
Qubits 128
Couplers 352
QFPs 128
dc SQUIDs 128
PMM 992
A 128-qubit processor requires only 84 dierential external biases to
calibrate and operate (compare with the initial estimate of 1632).
Not Covered in this Presentation . . .
There are many other parts needed
to realize a functional QA processor:
Circuit Design and Layout
Fabrication
Cryogenics
Wiring/Filtering
Magnetic Shielding
Room Temperature
Electronics
Calibration Methods
Software
Summary
Outline
1
2
Interqubit Couplers
Inductance Tuner
Readout
3
4
Summary
Summary
Summary
Key conclusions thusfar:
An architecture that enables quantum annealing of a lattice of
coupled ux qubits has been described.
A scalable control and readout architecture has been developed.
Prototype processors based upon this design have been fabricated.
Does it work? This is the topic of Part II . . .
Summary
Useful References
Qubits
Harris et al. Phys. Rev. B, 81 134510 (2010).
Couplers
Harris et al. Phys. Rev. B, 80 052506 (2009).
Scalable Control Circuitry
Johnson et al., Supercond. Sci. Technol. 23, 065004 (2010).
XY-Addressable Readout
Berkley et al., arXiv:0905.0891 (2009).
(accepted in Supercond. Sci. Technol.)
Unit Cell Architecture
Harris et al., Phys. Rev. B 82, 024511 (2010).

ATOM 20100909 D-Wave Unit Cell Overview I Richard Harris

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ATOM 20100909 D-Wave Unit Cell Overview I Richard Harris

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Experimental Investigation of an Eight Qubit Unit Cell

in a Superconducting Optimization Processor

with random sign and

+1. The optimal solution s

0.63 0.625 0.62 0.615 0.61

) onto the hardware controls

. Living with ux qubits

, and (t) yields the following:

, and (t) carefully . . .

are supposed to be time-independent.

, but not so for h

independent of coupler settings.

-compensation signal and I

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