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VHDL

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CONTENTS
1. INTRODUCTION TO VLSI 3
2. BASIC COMPONENTS OF A VHDL MODEL 13
3. BASIC LANGUAGE ELEMENTS 18
4. MODELING TYPES 32
5. GENERICS AND CONFIGURATIONS 52
6. SUBPROGRAMS AND PACKAGES 59
. ADVANCED FEATURES 68

CHAPTER 1
2
INTRODUCTION TO VLSI
I!"#$%&'"($!
Integrated circuits were made possible by experimental discoveries which showed
that semiconductor devices could perform the functions of vacuum tubes, and by mid-
20th-century technology advancements in semiconductor device fabrication. The
integration of large numbers of tiny transistors into a small chip was an enormous
improvement over the manual assembly of circuits using discrete electronic components.
The integrated circuits mass production capability, reliability, and building-bloc!
approach to circuit design ensured the rapid adoption of standardi"ed I#s in place of
designs using discrete transistors. There are two main advantages of I#s over discrete
circuits - cost and performance. #ost is low because the chips, with all their components,
are printed as a unit by photolithography and not constructed a transistor at a time.
$erformance is high since the components switch %uic!ly and consume little power,
because the components are small and close together. &s of 200', chip areas range from a
few s%uare mm to around 2(0 mm
2
, with up to 1 million transistors per mm
2
.
A%)*!'+, (! I!"+-#*"+% '(#'&(",
&mong the most advanced integrated circuits are the microprocessors, which
control everything from computers to cellular phones to digital microwave ovens. )igital
memory chips are another family of integrated circuit that is crucially important to the
modern information society. *hile the cost of designing and developing a complex
integrated circuit is %uite high, when spread across typically millions of production units
the individual I# cost is minimi"ed. The performance of I#s is high because the small
si"e allows short traces, which in turn allows low power logic +such as #,-./ to be used
at fast switching speeds.
I#s have consistently migrated to smaller feature si"es over the years, allowing
more circuitry to be pac!ed on each chip. &s the feature si"e shrin!s, almost everything
improves - the cost per unit and the switching power consumption go down, and the
speed goes up. 0owever, I#s with nanometer-scale devices are not without their
1
problems, principal among which is lea!age current, although these problems are not
insurmountable and will li!ely be solved or at least ameliorated by the introduction of
high-! dielectrics. .ince these speed and power consumption gains are apparent to the
end user, there is fierce competition among the manufacturers to use finer geometries.
This process, and the expected progress over the next few years, is well described by the
International Technology 2oadmap for .emiconductors, or IT2..
SSI. MSI. LSI
The first integrated circuits contained only a few transistors. #alled 3S/*001S'*0+
I!"+-#*"($!3 +SSI/, they used circuits containing transistors numbering in the tens...I
circuits were crucial to early aerospace pro4ects, and vice-versa. 5oth the ,inuteman
missile and &pollo program needed lightweight digital computers for their inertially-
guided flight computers6 the &pollo guidance computer led and motivated the integrated-
circuit technology, while the ,inuteman missile forced it into mass-production.These
programs purchased almost all of the available integrated circuits from 17'0 through
17'1, and almost alone provided the demand that funded the production improvements to
get the production costs from 810009circuit +in 17'0 dollars/ to merely 82(9circuit +in
17'1 dollars/.
The next step in the development of integrated circuits, ta!en in the late 17'0s,
introduced devices which contained hundreds of transistors on each chip, called
:M+%(&/1S'*0+ I!"+-#*"($!3 +MSI/. They were attractive economically because while
they cost little more to produce than ..I devices, they allowed more complex systems to
be produced using smaller circuit boards, less assembly wor!, and a number of other
advantages. ;urther development, driven by the same economic factors, led to 3L*#-+1
S'*0+ I!"+-#*"($!3 +LSI/ in the mid 17<0s, with tens of thousands of transistors per chip.
=.I circuits began to be produced in large %uantities around 17<0, for computer main
memories and poc!et calculators.
VLSI
>
The final step in the development process, starting in the 17?0s and continuing
on, was 3@ery =arge-.cale Integration3 +@=.I/, with hundreds of thousands of
transistors, and beyond +well past several million in the latest stages/. ;or the first time it
became possible to fabricate a #$A on a single integrated circuit, to create a
microprocessor. In 17?' the first one megabit 2&, chips were introduced, which
contained more than one million transistors. ,icroprocessor chips produced in 177>
contained more than three million transistors.This step was largely made possible by the
codification of 3design rules3 for the #,-. technology used in @=.I chips, which made
production of wor!ing devices much more of a systematic endeavour.
ULSI. 2SI. SOC
To reflect further growth of the complexity, the term ULSI that stands for 3U0"#*1
L*#-+ S'*0+ I!"+-#*"($!3 was proposed for chips of complexity more than 1 million of
transistors. 0owever there is no %ualitative leap between @=.I and A=.I, hence normally
in technical texts the 3@=.I3 term covers A=.I as well, and 3A=.I3 is reserved only for
cases when it is necessary to emphasi"e the chip complexity, e.g. in mar!eting.
The most extreme integration techni%ue is 3*4+#1,'*0+ (!"+-#*"($! +2SI/, which
uses whole uncut wafers containing processors as well as memory. &ttempts to ta!e this
step commercially in the 17?0s +e.g. by Bene &mdahl/ failed, mostly because of defect-
free manufacturability problems, and it does not now seem to be a high priority for
industry.The *.I techni%ue failed commercially, but advances in semiconductor
manufacturing allowed for another attac! on the I# complexity, !nown as S5,"+/1$!1
C6(7 +SOC/ design. In this approach, components traditionally manufactured as separate
chips to be wired together on a printed circuit board are designed to occupy a single chip
that contains memory, microprocessor, peripheral interfaces, Input9-utput logic control,
data converters, and other components, together composing the whole electronic system.
(
O"6+# %+)+0$7/+!",
In the 17?0s programmable integrated circuits were developed. These devices
contain circuits whose logical function and connectivity can be programmed by the user,
rather than being fixed by the integrated circuit manufacturer. This allows a single chip to
be programmed to implement different =.I-type functions such as logic gates, adders,
and registers. #urrent devices named ;$B&s +;ield $rogrammable Bate &rrays/ can now
implement tens of thousands of =.I circuits in parallel and operate up to >00 ,0". The
techni%ues perfected by the integrated circuits industry over the last three decades have
been used to create microscopic machines, !nown as ,C,.. These devices are used in a
variety of commercial and defense applications, including pro4ectors, in! 4et printers, and
accelerometers used to deploy the airbag in car accidents. In the past, radios could not be
fabricated in the same low-cost processes as microprocessors. 5ut since 177?, a large
number of radio chips have been developed using #,-. processes. Cxamples include
Intels )C#T cordless phone, or &theross ?02.11 card.
M$$#+8, L*3
'
The growth of complexity of integrated circuits follows a trend called 3,oores
=aw3, first observed by Bordon ,oore of Intel. ,oores =aw in its modern interpretation
states that the number of transistors in an integrated circuit doubles every two years. 5y
the year 2000 the largest integrated circuits contained hundreds of millions of transistors.
It is difficult to say whether the trend will continue.
P$7&0*#("5 $4 IC,
-nly a half century after their development was initiated, integrated circuits have
become ubi%uitous. #omputers, cellular phones, and other digital appliances are now
inextricable parts of the structure of modern societies. That is, modern computing,
communications, manufacturing and transport systems, including the Internet, all depend
on the existence of integrated circuits. Indeed, many scholars believe that the digital
revolution brought about by integrated circuits was one of the most significant
occurrences in the history of man!ind.
265 VLSI9
Integration improves the designD
lower parasitics E higher speed.
lower power.
physically smaller.
Integration reduces manufacturing cost-no manual assembly.
C6*00+!-+, (! VLSI D+,(-!
,ultiple levels of abstractionD transistors to #$As.
,ultiple and conflicting constraintsD low cost and high performances are often at
odds.
.hort design timeD =ate products are often irrelevant.
<
D+*0(!- 3("6 C$/70+:("5
)ivide-and-con%uerD limit the number of components you deal with at any one time.
Broup several components into larger componentsD
transistors form gates6
gates form functional units6
functional units form processing elements, etc.
T$71%$3! ),. B$""$/1&7 D+,(-!
Top-down design adds functional detail.
#reate lower levels of abstraction from upper levels.
5ottom-up design creates abstractions from low-level behavior.
Bood design needs both top-down and bottom-up efforts.
D+,(-! S"#*"+-(+,
I# design productivity depends on the efficiency with which the design may be
converted from concept to architecture, to logic and memory, to circuit and hence to a
physical layout.
& good design strategy with a good design system should provide for consistent
descriptions in various abstraction levels.
The role of good design strategies is to reduce complexity, increase productivity, and
assure wor!ing product.
)esign is a continuous trade-off to achieve ade%uate results forD
$erformance - speed, power, function, flexibility
.i"e of die +hence cost of die/
Time to design
Case of test generation and testability
?
H*#%3*#+ D+,'#(7"($! L*!-*&-+, ;HDL,<
ICCC standardi"ed =anguage

VHDL

V+#(0$-HDL
26*" (, VHDL9
VHDL= V0.I# Hardware Description Language
FVHSIC= Very High Speed Integrated Circuit
)eveloped originally by )&2$&
Ffor specifying digital systems
International ICCC standard +ICCC 10<'-1771/
0ardware )escription, .imulation, .ynthesis
$ractical benefitsD
Fa mechanism for digital design and reusable design documentation
F,odel interoperability among vendors
FThird party vendor support
F)esign re-use.
VHDL ),. C>P*,'*0
C>P*,'*0=
F$rocedural programming languages.
FTypically describe procedures for computing a maths function or manipulation of data.
+e.g., sorting, matrix computing/
F& program is a recipe or a se%uence of steps for how to perform a computation or
manipulate data.
VHDL=
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F a language to describe digital systems.
F$urposesD simulation and synthesis of digital systems.
D+,(-! F0$3
SPECIFICATION
This is the stage at which we define what are the important parameters of the
system9design that you are planning to design. & simple example would beD I want to
design a counter6 it should be > bit wide, should have synchronous reset, with active high
enable6 when reset is active, counter output should go to 303.
HIGH LEVEL DESIGN
This is the stage at which you define various bloc!s in the design and how they
communicate. =ets assume that we need to design a microprocessorD high level design
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means splitting the design into bloc!s based on their function6 in our case the bloc!s are
registers, &=A, Instruction )ecode, ,emory Interface, etc.
MICRO DESIGN>LO2 LEVEL DESIGN
=ow level design or ,icro design is the phase in which the designer describes
how each bloc! is implemented. It contains details of .tate machines, counters, ,ux,
decoders, internal registers. It is always a good idea to draw waveforms at various
interfaces. This is the phase where one spends lot of time.
RTL CODING
In 2T= coding, ,icro design is converted into @erilog9@0)= code, using
synthesi"able constructs of the language. Gormally we li!e to lint the code, before
starting verification or synthesis.
SIMULATION
.imulation is the process of verifying the functional characteristics of models at
any level of abstraction. *e use simulators to simulate the 0ardware models. To test if
the 2T= code meets the functional re%uirements of the specification, we must see if all
the 2T= bloc!s are functionally correct. To achieve this we need to write a "+,"?+!'6,
which generates cl!, reset and the re%uired test vectors. *e use the waveform output
from the simulator to see if the )AT +)evice Ander Test/ is functionally correct.
SYNTHESIS
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.ynthesis is the process in which synthesis tools li!e design compiler or .ynplify
ta!e 2T= in @erilog or @0)=, target technology, and constrains as input and maps the
2T= to target technology primitives. .ynthesis tool, after mapping the 2T= to gates, also
do the minimal amount of timing analysis to see if the mapped design is meeting the
timing re%uirements. ;I/7$#"*!" "6(!- "$ !$"+ (,. ,5!"6+,(, "$$0, *#+ !$" *3*#+ $4 3(#+
%+0*5,. "6+5 $!05 @!$3 $4 -*"+ %+0*5,<.
F$#/*0 V+#(4('*"($!= #hec! if the 2T= to gate mapping is correct.
S'*! (!,+#"($! = Insert the scan chain in the case of &.
PLACE A ROUTE
The gatelevel netlist from the synthesis tool is ta!en and imported into place and
route tool in @erilog netlist format. &ll the gates and flip-flops are placed6 cloc! tree
synthesis and reset is routed. &fter this each bloc! is routed. The $H2 tool output is a
B). file, used by foundry for fabricating the &.I#.
GATE LEVEL SIMULATION ;OR< SDF>TIMING SIMULATION
There is another !ind of simulation, called "(/(!- ,(/&0*"($!, which is done after
synthesis or after $H2 +$lace and 2oute/. 0ere we include the gate delays and wire
delays and see if )AT wor!s at rated cloc! speed.
POST SILICON VALIDATION
-nce the chip +silicon/ is bac! from fab, it needs to put in real environment and
tested before it can be released into ,ar!et. .ince the speed of simulation with 2T= is
very slow +number cloc!s per second/, there is always possibility to find a bug in $ost
silicon validation.
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N$"+D &s design becomes complex, we write SELF CHECKING TESTBENCH,
where test bench applies the test vector, then compares the output of )AT with expected
values.
CHAPTER 2
BASIC COMPONENTS OF A VHDL MODEL
The purpose of @0)= descriptions is to provide a model for digital circuits and
systems. This abstract view of the real physical circuit is referred to as entity. &n entity
normally consists of five basic elements, or design units.
In @0)= one generally distinguishes between the external view of a module and
its internal description. The external view is reflected in the entity declaration, which
represents an interface description of a blac! box. The important part of this interface
description consists of signals over which the individual modules communicate with each
other.
The internal view of a module and, therefore, its functionality is described in the
architecture body. This can be achieved in various ways. -ne possibility is given by
coding a behavioral description with a set of concurrent or se%uential statements. &nother
possibility is a structural description, which serves as a base for the hierarchically
designed circuit architectures. Gaturally, these two !inds of architectures can also be
11
combined. The lowest hierarchy level, however, must consist of behavioral descriptions.
-ne of the ma4or @0)= features is the capability to deal with multiple different
architectural bodies belonging to the same entity declaration.
5eing able to investigate different architectural alternatives permits the
development of systems to be done in an efficient top-down manner. The ease of
switching between different architectures has another advantage, namely, %uic! testing. In
this case, it is necessary to bind one architecture to the entity in order to have a uni%ue
hierarchy for simulation or synthesis. *hich architecture should be used for simulation or
synthesis in con4unction with a given entity is specified in the configuration section. If
the architecture body consists of a structural description, then the binding of architectures
and entities of the instantiated submodules, the so-called components, can also be fixed
by the configuration statement.
The pac!age is the last element mentioned here. It contains declarations of
fre%uently used data types, components, functions, and so on. The pac!age consists of a
pac!age declaration and a pac!age body. The declaration is used, li!e the name implies,
for declaring the above-mentioned ob4ects. This means, they become visible to other
design units. In the pac!age body, the definition of these ob4ects can be carried out, for
example, the definition of functions or the assignment of a value to a constant. The
partitioning of a pac!age into its declaration and body provides advantages in compiling
the model descriptions.
E!"("5 D+'0*#*"($!
&n entity declaration specifies the name of an entity and its interface. This
corresponds to the information given by the symbols in traditional design methods based
on drawing schematics. .ignals that are used for communication with the surrounding
modules are called ports.
1>
I!"+#4*'+ $4 * 4&001*%%+# /$%&0+
E:*/70+ =
entity ;A==&))C2 is
port + &, 5, # D in bit 6
.A,, #&22I D out bit /6
end ;A==&))C26
The module ;A==&))C2 has five interface ports. Three of them are the input
ports &, 5 and # indicated by the @0)= !eyword (!. The remaining two are the output
ports .A, and #&22I indicated by $&". The signals going through these ports are
chosen to be of the type bit. This is one of the predefined types besides integer, real and
others types provided by @0)=. The type bit consists of the two characters 0 and 1 and
represents the binary logic values of the signals.
Cvery port declaration implicitly creates a signal with the name and type
specified. It can be used in all architectures belonging to the entity in one of the following
port modesD
(!D The port can only be read within the entity and its architectures.
$&"D This port can only be written.
(!$&"D This port can be read and written. This is useful for modeling bus systems.
?&44+#D The port can be read and written. Cach port must have only one driver.
S5!"*: =
1(
+!"("5 entity name (,
J generics K
J ports K
J declarations +types, constants, signals/ K
J definitions +functions, procedures/ K
J ?+-(! -- normally not used
statements K
+!% J entity name K B
A#'6("+'"&#+
The second important component of a @0)= description is the architecture. This
is where the functionality and the internal implementation of a module are described. In
general, a complex hierarchically structured system may have the topology.
H(+#*#'6('*0 '(#'&(" %+,(-!
.D structural description
5D behavioral description
59.D mixed description
In order to describe such a system both behavioral and structural descriptions are
re%uired. & behavioral description may be of either concurrent or se%uential type.
-verall, @0)= architectures can be classified into the three main typesD
1'
)ata flow modeling.
5ehavioral modeling.
.tructural modeling.
S5!"*: =
*#'6("+'"&#+ architecture name $4 entity name (,
J arch declarative part K
?+-(!
J arch statement part K
+!% J architecture name K B
The architecture specifies the implementation of the entity entity name. & label
architecture name must be assigned to the architecture. In case there are multiple
architectures associated with one entity this label is then used within a configuration
statement to bind one particular architecture to its entity. The architecture bloc! consists
of two partsD the arch declarative part before the !eywords ?+-(! and the arch statement
part after the !eywords ?+-(!. In the declaration part local types, signals, components etc.
are declared and subprograms are defined. The actual model description is done in the
statement part. In contrast to programming languages li!e #, the ma4or concern of @0)=
is describing hardware which primary wor!s in parallel and not in a se%uential manner.
Therefore, a special simulation algorithm is used to achieve a virtual concurrent
processing. This algorithm is explained in the following section.
C$!4(-&#*"($! =
It is used to create a configuration for an entity. To binding of components used in
the selected architecture body to other entities.
P*'@*-+ D+'0*#*"($! =
1<
It contains a set of declarations that may possibly be shared by many design units.
P*'@*-+ B$%5 =
It contains the behavior of the subprogram and the values of the deferred
constants declared in a pac!age declaration.
CHAPTER 3
BASIC LANGUAGE ELEMENTS
This describes the facilities in @0)=, which are drawn from the familiar
programming language repertoire. If you are familiar with the &da programming
language, you will notice the similarity with that language. This is both a convenience
and a nuisance. The convenience is that you donLt have much to learn to use these @0)=
facilities. The problem is that the facilities are not as comprehensive as those of &da,
though they are certainly ade%uate for most modeling purposes.
L+:('*0 E0+/+!",
C$//+!",
#omments in @0)= start with two ad4acent hyphens +M--L/ and extend to the end
of the line. They have no part in the meaning of a @0)= description.
I%+!"(4(+#,
Identifiers in @0)= are used as reserved words and as programmer-defined
names. They must conform to the ruleD
=etter N J underline K letterOorOdigit P
Gote that case of letters is not considered significant, so the identifiers cat and #at are the
same. Anderline characters in identifiers are significant, so ThisOGame and ThisGame are
different identifiers.
1?
N&/?+#,
=iteral numbers may be expressed either in decimal or in a base between two and
sixteen. If the literal includes a point, it represents a real number, otherwise it represents
an integer. )ecimal literals are defined byD
integer J integer K J exponent K
E:*/70+ =
0 1 121O>('O<?7 7?<C' -- integer literals
0.0 0.( 2.<1?O2? 12.>C-7 -- real literals
5ased literal numbers are defined byD
base Q basedOinteger J basedOinteger K Q J exponent K

The base and the exponent are expressed in decimal. The exponent indicates the power of
the base by which the literal is multiplied. The letters & to ; +upper or lower case/ are
used as extended digits to represent 10 to 1(.
E:*/70+ =
2Q1100O0100Q 1'Q#>Q >Q101QC1 -- the integer 17'
2Q1.1111O1111O111QCR11 1'Q;.;;QC2 -- the real number >07(.0
C6*#*'"+#,
=iteral characters are formed by enclosing an &.#II character in single-%uote
mar!s.
E:*/70+ =
& S
S"#(!-,
=iteral strings of characters are formed by enclosing the characters in double-
%uote mar!s. To include a double-%uote mar! itself in a string, a pair of double-%uote
mar!s must be put together. & string can be used as a value for an ob4ect which is an array
of characters.
17
E:*/70+ =
3& string3
33 -- empty string
3& string in a stringD 33& string33. 3 -- contains %uote mar!s
B(" S"#(!-,
@0)= provides a convenient way of specifying literal values for arrays of type
bit.
S5!"*: =
baseOspecifier 3 bitOvalue 3

5ase specifier 5 stands for binary, - for octal and T for hexadecimal.
E:*/70+, =
5310101103 -- length is <
-312'3 -- length is 7, e%uivalent to 53001O010O1103
T3('3 -- length is ?, e%uivalent to 530101O01103
D*"* T57+, *!% O?C+'",
@0)= provides a number of basic, or scalar, types, and a means of forming
composite types. The scalar types include numbers, physical %uantities, and enumerations
and there are a number of standard predefined basic types. The composite types provided
are arrays and records. & data type can be defined by a type declarationD
"57+ identifier (, typeOdefinition B
T57+D%+4(!("($! =
scalarOtypeOdefinition
compositeOtypeOdefinition
S'*0*#D"57+D%+4(!("($! =
20
integerOtypeOdefinition
physicalOtypeOdefinition
floatingOtypeOdefinition
enumerationOtypeOdefinition
C$/7$,("+D"57+D%+4(!("($! =
arrayOtypeOdefinition
recordOtypeOdefinition
I!"+-+# T57+,
&n integer type is a range of integer values within a specified range.
S5!"*: =
"57+ identifier (, #*!-+ rangeOconstraintB


The expressions that specify the range must of course evaluate to integer numbers. Types
declared with the !eyword "$ are called ascending ranges, and those declared with the
!eyword %$3!"$ are called descending ranges. The @0)= standard allows an
implementation to restrict the range, but re%uires that it must at least allow the range F
21><>?1'>< to R21><>?1'><.
E:*/70+ =
type byteOint is range 0 to 2(( 6
type signedOwordOint is range F12<'? to 12<'< 6
type bitOindex is range 11 downto 0 6
There is a predefined integer type called integer. The range of this type is implementation
defined, though it is guaranteed to include F21><>?1'>< to R21><>?1'><.
P65,('*0 T57+,
21
& physical type is a numeric type for representing some physical %uantity, such as
mass, length, time or voltage. The declaration of a physical type includes the
specification of a base unit, and possibly a number of secondary units, being multiples of
the base unit.
S5!"*: =
"57+ identifier (, #*!-+ rangeOconstraint
&!(",
baseOunitOdeclaration
N secondaryOunitOdeclaration P
+!% &!(",
E:*/70+ =
type length is range 0 to 1C7
units
um6
mm E 1000 um6
cm E 10 mm6
m E 1000 mm6
in E 2(.> mm6
ft E 12 in6
yd E 1 ft6
rod E 17? in6
chain E 22 yd6
furlong E 10 chain6
end units6
type resistance is range 0 to 1C?
units
ohms6
!ohms E 1000 ohms6
22
,ohms E 1C' ohms6
end units6
The predefined physical type time is important in @0)=, as it is used extensively to
specify delays in simulations. Its definition isD
type time is range implementationOdefined
units
fs6
ps E 1000 fs6
ns E 1000 ps6
us E 1000 ns6
ms E 1000 us6
sec E 1000 ms6
min E '0 sec6
hr E '0 min6
end units6
F0$*"(!- P$(!" T57+,
& floating point type is a discrete approximation to the set of real numbers in a
specified range. The precision of the approximation is not defined by the @0)= language
standard, but must be at least six decimal digits. The range must include at least F1C1? to
R1C1?.
S5!"*: =
"57+ identifier (, #*!-+ rangeOconstraint B
E:*/70+, =
type signalOlevel is range F10.00 to R10.00 6
type probability is range 0.0 to 1.0 6
There is a predefined floating point type called real. The range of this type is
implementation defined, though it is guaranteed to include F1C1? to R1C1?.
21
E!&/+#*"($! T57+,
&n enumeration type is an ordered set of identifiers or characters. The identifiers
and characters within a single enumeration type must be distinct, however they may be
reused in several different enumeration types.
S5!"*: =
"57+ identifier (, ; enumerationOliteral / B
E:*/70+ =
type logicOlevel is +un!nown, low, undriven, high/6
type aluOfunction is +disable, pass, add, subtract, multiply, divide/6
type octalOdigit is +0, 1, 2, 1, >, (, ', </6
There are a number of predefined enumeration types, defined as followsD
type severityOlevel is +note, warning, error, failure/6
type boolean is +false, true/6
type bit is +0, 1/6
type character is + GA=, .-0, .TT, CTT, C-T, CGU, &#V, 5C=, 5.,
0T, =;, @T, ;;, #2, .-, .I, )=C, )#1, )#2, )#1,
)#>, G&V, .IG, CT5, #&G,C,, .A5, C.#, ;.$,
B.$, 2.$, A.$, , W, 3, Q, 8, X, H, , +, /,
S, R, ,, -, ., 9, 0, 1, 2, 1, >, (, ', <, ?, 7,
D, 6, Y, E, Z, [, \, &, 5, #, ), C, ;, B,
0, I, ], V, =, ,, G, -,$, U, 2, ., T, A,
@, *, T, I, ^, J, _, K, `, O, a, a, b, c, d,
e, f, g, h, i, 4, !, l, m, n, o, p, %, r, s, t,
u, v, w, x, y, ", N, b, P, c, )C=/6
2>
Gote that type character is an example of an enumeration type containing a mixture of
identifiers and characters. &lso, the characters 0 and 1 are members of both bit and
character . *here 0 or 1 occur in a program, the context will be used to determine which
type is being used.
A##*5,
&n array in @0)= is an indexed collection of elements all of the same type.
&rrays may be one-dimensional +with one index/ or multidimensional +with a number of
indices/. In addition, an array type may be constrained, in which the bounds for an index
are established when the type is defined, or unconstrained, in which the bounds are
established subse%uently.
S5!"*: =
"57+ identifier (, *##*5 indexOconstraint $4 element_subtypeOindicationB
E:*/70+ =
type word is array +11 downto 0/ of bit6
type memory is array +address/ of word6
type transform is array +1 to >, 1 to >/ of real6
type registerOban! is array +byte range 0 to 112/ of integer6
&n example of an unconstrained array type declarationD
type vector is array +integer range YZ/ of real6
The symbol MYZL +called a box/ can be thought of as a place-holder for the index
range, which will be filled in later when the array type is used. ;or example, an ob4ect
might be declared to be a vector of 20 elements by giving its type asD
vector+1 to 20/
There are two predefined array types, both of which are unconstrained. They are defined
asD
type string is array +positive range YZ/ of character6
2(
type bitOvector is array +natural range YZ/ of bit6
The types positive and natural are subtypes of integer. The type bitOvector is
particularly useful in modeling binary coded representations of values in simulations of
digital systems. &n element of an array ob4ect can referred to by indexing the name of the
ob4ect. ;or example, suppose a and b are one and two-dimensional array ob4ects
respectively. Then the indexed names a+1/ and b+1, 1/ refer to elements of these arrays.
;urthermore, a contiguous slice of a one-dimensional array can be referred to by using a
range as an index. ;or example a +? "$ 1(/ is an eight-element array which is part of the
array . .ometimes you may need to write a literal value of an array type. This can be done
using an array aggregate, which is a list of element values. .uppose we have an array
type declared asD
type a is array +1 to >/ of character6
and we want to write a value of this type containing the elements f, o, o, d in that
order. *e could write an aggregate with positional association as followsD
+f, o, o, d/
In this case, the index for each element is explicitly given, so the elements can be
in any order. $ositional and named association can be mixed within an aggregate,
provided all the positional associations come first. &lso, the word $"6+#, can be used in
place of an index in a named association, indicating a value to be used for all elements
not explicitly mentioned. ;or example, the same value as above could be written asD
+f, > EZ d, others EZ o/
R+'$#%,
@0)= provides basic facilities for records, which are collections of named
elements of possibly different types.
S5!"*: =
"57+ identifier (,
2'
#+'$#%
elementOdeclaration
N elementOdeclaration P
+!% #+'$#%
E:*/70+ =
type instruction is
record
opOcode D processorOop 6
addressOmode D mode 6
operand1, operand2D integer range 0 to 1( 6
end record6
*hen you need to refer to a field of a record ob4ect, you use a selected name. ;or
example, suppose that r is a record ob4ect containing a field called f. Then the name r.f
refers to that field. &s for arrays, aggregates can be used to write literal values for
records. 5oth positional and named association can be used, and the same rules apply,
with record field names being used in place of array index names.
S&?"57+,
The use of a subtype allows the values ta!en on by an ob4ect to be restricted or
constrained subset of some base type.
S5!"*: =
,&?"57+ identifier (, J resolution_function_name K range J constraint K 6
There are two cases of subtypes. ;irstly a subtype may constrain values from a
scalar type to be within a specified range.
E:*/70+ =
subtype pinOcount is integer range 0 to >006
2<
subtype digits is character range 0 to 76
.econdly, a subtype may constrain an otherwise unconstrained array type by
specifying bounds for the indices.
E:*/70+ =
subtype id is string+1 to 20/6
subtype word is bitOvector+11 downto 0/6
There are two predefined numeric subtypes, defined asD
subtype natural is integer range 0 to highestOinteger 6
subtype positive is integer range 1 to highestOinteger 6
O?C+'" D+'0*#*"($!,
&n ob4ect is a named item in a @0)= description which has a value of a specified
type. There are three classes of ob4ectsD
#onstants
@ariables
.ignals
C$!,"*!",
)eclaration and use of constants and variables is very much li!e their use in
programming languages. & constant is an ob4ect which is initialised to a specified value
when it is created, and which may not be subse%uently modified.
S5!"*: =
'$!,"*!" identifierOlist D subtypeOindication J DE expression K 6
2?
#onstant declarations with the initialising expression missing are called deferred
constants, and may only appear in pac!age declarations. The initial value must be given
in the corresponding pac!age body.
E:*/70+ =
constant e D real DE 2.<1?2?6
constant delay D Time DE ( ns6
constant maxOsi"e D natural6
V*#(*?0+,
& variable is an ob4ect whose value may be changed after it is created.
S5!"*: =
)*#(*?0+ identifierOlist D subtypeOindication J DE expression K 6
The initial value expression, if present, is evaluated and assigned to the variable
when it is created. If the expression is absent, a default value is assigned when the
variable is created. The default value for scalar types is the leftmost value for the type,
that is the first in the list of an enumeration type, the lowest in an ascending range, or the
highest in a descending range. If the variable is a composite type, the default value is the
composition of the default values for each element, based on the element types.
E:*/70+ =
variable count D natural DE 06
variable trace D traceOarray6
&ssuming the type traceOarray is an array of boolean, then the initial value of the variable
trace is an array with all elements having the value false.
S(-!*0,
.ignals represent wires in a logic circuit. .ignals can be declared in all declarative
regions in @0)= except for functions and procedures. &ssignments to signals are not
immediate, but scheduled to be executed after a delta delay.
27
S5!"*: =
,(-!*0 identifierOlist D subtypeOindication J DE expression K 6
E:*/70+ =
signal foo D bitOvector +0 to (/ DE 530000003 6
signal aux D bit 6
signal maxOvalue D integer 6
The declaration assigns a name to the signal foo 6 a type, with or without a range
restriction +bitOvector+0 to (//6 and optionally an initial value. Initial values on signals are
usually ignored by synthesis. .ignals can be assigned values using an assignment
statement +e.g., aux YE L0L 6/. If the signal is of an array type, elements of the signalLs
array can be accessed and assigned using indexing or slicing methods.
E:7#+,,($!, *!% O7+#*"$#,
Cxpressions in @0)= are much li!e expressions in other programming languages.
&n expression is a formula combining primaries with operators. $rimaries include names
of ob4ects, literals, function calls and parenthesi"ed expressions.
O7+#*"$#, *!% 7#+'+%+!'+
The logical operators *!%, $#, !*!%, !$#, :$# and !$" operate on values of type
bit or boolean, and also on one-dimensional arrays of these types. ;or array operands, the
operation is applied between corresponding elements of each array, yielding an array of
10
the same length as the result. ;or bit and boolean operands, *!%, $#, !*!%, and !$# are
Mshort-circuitL operators, that is they only evaluate their right operand if the left operand
does not determine the result. .o *!% and !*!% only evaluate the right operand if the left
operand is true or 1, and $# and !$# only evaluate the right operand if the left operand is
false or 0.
The relational operators E, 9E, Y, YE, Z and ZE must have both operands of the
same type, and yield boolean results. The e%uality operators +E and 9E/ can have operands
of any type. ;or composite types, two values are e%ual if all of their corresponding
elements are e%ual. The remaining operators must have operands which are scalar types
or one-dimensional arrays of discrete types.
The sign operators +R and F/ and the addition +R/ and subtraction +F/ operators
have their usual meaning on numeric operands. The concatenation operator +H/ operates
on one-dimensional arrays to form a new array with the contents of the right operand
following the contents of the left operand. It can also concatenate a single new element to
an array, or two individual elements to form an array. The concatenation operator is most
commonly used with strings.
The multiplication +S/ and division +9/ operators wor! on integer, floating point
and physical types types. The modulus +/$%/ and remainder +#+// operators only wor!
on integer types. The absolute value +*?,/ operator wor!s on any numeric type. ;inally,
the exponentiation +SS/ operator can have an integer or floating point left operand, but
must have an integer right operand. & negative right operand is only allowed if the left
operand is a floating point number.
11
CHAPTER 4
MODELING TYPES
DATAFLO2 MODELING
This !ind of description specifies a dataflow through the entity based on
concurrent signal assignment statements. & structure of the entity is not explicitly defined
by this description but can be derived from it. &s an example, consider the following
implementation of the entity ;A==&))C2.
E:*/70+ =
architecture #-G#A22CGT of ;A==&))C2 is
begin

.A, YE & xor 5 xor # after ( ns6
#&22I YE +& and 5/ or +5 and #/ or +& and #/ after 1 ns6
end #-G#A22CGT6
Two concurrent signal assignment statements describe the model of the entity
;A==&))C2. The symbol YE indicates the signal assignment. This means that the value
on the right side of the symbol is calculated and subse%uently assigned to the signal on
the left side. & concurrent signal assignment is executed whenever the value of a signal in
the expression on the right side changes. In general, a change of the current value of a
signal is called an event. )ue to the fact that all signals used in this example are declared
as ports in the entity declaration.
12
The arch declarative part remains empty. Information about a possibly existing
delay time of the modeled hardware is provided by the after clause. If there is an event on
one of the inputs &, 5 or # at time T, the expression & xor 5 xor # is computed at this
time T, but the target signal +the output .A,/ is scheduled to get this new value at time T
R ( ns. The signal assignment for #&22I is handled in exactly the same way except for
the smaller delay time of 1 ns. If explicit information about the delay time is missing then
it is assumed to be 0 ns by default. Gevertheless, during the @0)= simulation the signal
assignment is executed after an infinitesimally small delay time, the so-called delta-delay.
This means that the signal assignment is executed immediately after an event on a signal
on the right side is detected and the calculation of the new expression value is performed.
S5!"*: =
J label = K signal name EF J "#*!,7$#" K expression J *4"+# time expression K B
Ap to now the label was not used. *ith this element it is possible to assign a label
to the statement, which can be useful for documentation. ;urthermore, it is possible to
assign several events with different delay times to the target signal. In this case the values
to be assigned and their delay times have to be sorted in ascending order. The !eyword
transport affects the handling of multiple signal events coming in short time one after
another.
E:*/70+ =
architecture @C21 of ,AT is
begin
-AT$AT YE & 6
end @C216
C$!%("($!*0 S(-!*0 A,,(-!/+!" ,"*"+/+!"
In this case there are different assignment statements related to one target signal.
The selection of one assignment statement is controlled by a set of conditions condition.
11
The conditional signal assignment statement can be compared with the well-!nown if -
elsif - else structure.
S5!"*: =
J label = K signal name EF expression 36+! condition +0,+
expression 36+! condition +0,+

expression B
The conditional signal assignment is activated as soon as one of the signals belonging to
the condition or expression changes.
E:*/70+ =
^ YE & when +T Z 1/ else
5 when +T Y 1/ else
# 6
Cach time one signal either in expression or condition changes its value the
complete statement is executed. .tarting with the first condition, the first true one selects
the expression that is computed and the resulting value is assigned to the target signal
signal name.
S+0+'"+% S(-!*0 A,,(-!/+!" ,"*"+/+!"
*ith this statement a choice between different assignment statements is made.
The selection of the right assignment is done by the value of select expression. The
statement resembles a case structure.
S5!"*: =
J label = K 3("6 selectOexpression ,+0+'"
signal name EF expression 36+! value .
expression 36+! value ,
expression 36+! others B
1>
The selected signal assignment is activated as soon as one of the signals belonging to the
selection condition or expression changes.
E:*/70+ =
with ,I.C= select
^ YE & when 1( ,
5 when 22 ,
# when others 6
U!*44+'"+% S"*"+/+!"
Go action to be ta!e place in a se%uential statement and execution continues with
the next statement. It is represented by using the !eyword &!*44+'"+%.
It is used in a conditional or selected signal assignment statement where, for certain
conditions. It may be useful or necessary to explicitly specify that no action needs to be
performed.
E:*/70+ =

with muxOsel select
^ YE & when :00d,
5 when :01d,
# when :10d,
unaffected when others 6
B0$'@ ,"*"+/+!"
& bloc! statement defines an internal bloc! representing a portion of a design.
5loc!s may be hierarchically nested to support design decomposition.
In order to efficiently group concurrent assignments, bloc! statements may be
used. & bloc! may contain declarations of data types, signals, and so on, all of which are
locally used. The body of the bloc! statement contains any of the concurrent statements
mentioned previously.
1(
& guarded bloc! contains an additional boolean expression guard expression,
which drives an implicit signal BA&2) of boolean type. This signal can be used within a
bloc! for the control of concurrent assignments. If concurrent statements have an
associated BA&2) signal, they are !nown as Buarded .ignal &ssignments.
S5!"*: =
=abel D bloc! J + guard expression / K
J use clause K
J subprogram decl , subprogram body K
J type decl K
J subtype decl K
J constant decl K
J signal decl K
J component decl K
begin
J concurrent statements K
end bloc! J label K 6
Buarded .ignal &ssignment is a special form of the concurrent assignment. The
assignment is activated after the BA&2) signal, which must be of the boolean type, is
evaluated to true. The BA&2) signal can be explicitly declared and used6 however, it is
more common to use it implicitly within a Buarded 5loc!.
S5!"*: =
J label D K signal name YE guarded expression J after time expr K 6
E:*/70+ =
A1 D bloc! + cl!EM1L and not cl!Lstable /
1'
signal temp D stdOlogic 6
begin
temp YE guarded ) 6
U YE temp 6
UL YE not temp
end bloc! A1 6

&ny declarations appearing within the bloc! are visible only within the bloc!, that is,
between bloc! eeeee. end bloc!.
BEHAVIORAL MODELING
5ehavioral descriptions are based on the process environment. & process
statement as a whole is treated as a concurrent statement within the architecture.
Therefore, in the simulation time a process is continuously executed and it never gets
finished. The statements within the process are executed se%uentially without the advance
of simulation time. To ensure that simulation time can move forward every process must
provide a means to get suspended. Thus, a process is constantly switching between the
two statesD the execution phase in which the process is active and the statements within
this process are executed, and the suspended state. The change of state is controlled by
two mutually exclusive implementationsD
*ith a list of signals in such a manner that an event on one of these signals
invo!es a process. This can be compared with the mechanism used in con4unction
with concurrent signal assignment statements. There, the statement is executed
whenever a signal on the right side of the assignment operator YE changes its value.
In case of a process, it becomes active by an event on at least one signal belonging
to the sensitivity list. &ll statements between the !eywords begin and end process
are then executed se%uentially.
S5!"*: =
J proc label = K 7#$'+,, ; sensitivity list <
1<
J proc declarative part K
?+-(!
J se%uential statement part K
+!% 7#$'+,, J proc label K B
The sensitivity list is a list of signal names within round brac!ets, for Cxample
; &, 5, # <.
*ith wait statements in such a way that the process is executed until it reaches a
wait statement. &t this instance it gets explicitly suspended. The statements within
the process are handled li!e an endless loop which is suspended for some time by a
wait statement.
S5!"*: =
J process label = K 7#$'+,,
J proc declarative part K
?+-(!
J se%uential statements K
3*(" ...B -- at least one wait statement
J se%uential statements K
+!% 7#$'+,, J proc label K B
The structure of a process statement is similar to the structure of an architecture.
In the process declarative part various types, constants and variables can be declared6
functions and procedures can be defined. The se%uential statement part contains the
description of the process functionality with ordered se%uential statements. &n
implementation of the full adder with a se%uential behavioral description is given belowD
1?
E:*/70+ =
architecture .CUACGTI&= of ;A==&))C2 is
begin
process +&, 5, #/
variable TC,$ D integer6
variable .A, #-)C D bit vector+0 to 1/ DE 3010136
variable #&22I #-)C D bit vector+0 to 1/ DE 3001136
begin
if & E 1 then
TC,$ DE 16
else
TC,$ DE 06
end if6
if 5 E 1 then
TC,$ DE TC,$ R 16
end if6
if # E 1 then
TC,$ DE TC,$ R 16
end if6 -- variable TC,$ now holds the number of ones
.A, YE .A, #-)C+TC,$/6
#&22I YE #&22I #-)C+TC,$/6
end process6
end .CUACGTI&=6
The functionality of this behavioral description is based upon a temporary
variable TC,$ which counts the number of ones on the input signals. *ith this number
one element, or one bit, is selected from each of the two predefined vectors .A, #-)C
and #&22I #-)C. The initiali"ation of these two vectors reacts the truthtable of a full-
adder module. The reason for this unusual coding is the attempt to explain the
characteristics of a variable. & variable differs not only in the assignment operator +DE/
17
from that of a signal +YE/. It is also different with respect to time when the new computed
value becomes valid and, therefore, readable to other parts of the model.
Cvery variable gets the new calculated value immediately, whereas the new signal
value is not valid until the beginning of the next delta-cycle, or until the specified delay
time elapses. If the above example had been coded with a signal as the temporary counter
instead of the variable, then the correct functionality of this architecture as a full adder
could not be ensured. &fter an event at time T on one of the input signals &, 5 or #,
which are members of the sensitivity list, the process is executed once. The simulation
continues with executing the second if statement at time T because computing a
se%uential statement does not advance the simulation time. Therefore, the signal TC,$
still holds the same value it had before the process activationW This means that the
intended counting of ones does not wor! with TC,$ declared as signal.
In general, signal assignment statements within a process have to be handled with
care, especially if the target signal will be read or rewritten in the following code before
the process gets suspended. If this effect is ta!en into consideration, the process statement
provides an environment in which a person familiar with programming languages li!e #
or $ascal can easily generate a @0)= behavioral description. This remar!, however,
should not be understood that the process statement is there for people switching to
@0)=. In reality, some functions can be implemented much more easily in a se%uential
manner.
E:*/70+ =
architecture .CUACGTI&= of );; is
begin
process +#=V, G2/
begin
if +G2 E 0/ then
U YE +others EZ 0/6
elsif +#=Vevent and #=V E 1/ then
U YE )6
>0
end if6
end process6
end .CUACGTI&=6
In the above example, the attribute #=Vevent is used to detect an edge on the
#=V signal. This is e%uivalent to an event on #=V. The ability to detect edges on signals
is based upon the storage of all events in event %ueues for every signal. Therefore, old
values can be compared with the actual ones or even read. In contrast, variables always
get the new assigned value immediately and the old value is not stored. .ubse%uently,
during the simulation more memory is re%uired for a signal for a variable. In complex
system descriptions this fact should be ta!en into consideration.
S+G&+!"(*0 S(-!*0 A,,(-!/+!" ,"*"+/+!"
The syntax of a se%uential signal assignment is very similar to the concurrent
assignment statement, except for a label which can not be used.
S5!"*: =
signal name EF J "#*!,7$#" K expression J *4"+# time expr K B
V*#(*?0+ A,,(-!/+!" ,"*"+/+!"
& variable assignment statement is very similar to a signal assignment. &s already
mentioned, a variable differs from a signal in that it gets its new value immediately upon
assignment. Therefore, the specification of a delay time in a variable assignment is not
possible. &ttention must be paid to the assignment operator which is DE for a variable and
YE for a signal.
S5!"*: =
variable name =F expression B
2*(" ,"*"+/+!"
>1
This statement may only be used in processes without a sensitivity list. The
purpose of the wait statement is to control activation and suspension of the process.
S5!"*: =
2*(" J $! signal names K B
2*(" J &!"(0 condition K
2*(" J 4$# time expression K B
The arguments of the wait statement have the following interpretationsD
on signal namesD
The process gets suspended at this line until there is an event on at least one signal
in the list signal names. The signal names are separated by commas6 brac!ets are not
used. It can be compared to the sensitivity list of the process statement.
until conditionD
The process gets suspended until the condition becomes true.
for time expressionD
The process becomes suspended for the time specified by time expression.
without any argumentD
The process gets suspended until the end of the simulation.
& sensitivity list of a process is functionally e%uivalent to the wait on ... appearing at the
end of the process. There are four different ways to use the wait-statementD
wait on &, 56
suspends a process until an occurrence of a change is registered. 0ere, execution will
resume when a new event is detected on either signal & or 5.
wait until T Z 106
>2
suspends a process until the condition is satisfied6 in this case, until the value of a signal
is Z 10.
wait for 10 ns6

suspends a process for the time specified6 here, until 10 ns of simulation time elapses.
wait6
suspends a process indefinitely. . . .ince a @0)=-process is always active, this statement
at the end of a process is the only way to suspend it. This techni%ue may be used to
execute initiali"ation processes only once.
The example below models an architecture, which simulates a $roducer9#onsumer
problem using two processes. The processes are synchroni"ed through a simple
handsha!e protocol, which has two wires, each with two active states.
E:*/70+ =
entity $2- #-G is
...
end $2- #-G 6
architecture 5C0&@ of $2- #-G is
signal $2-)D boolean DE false6 --item produces a semaphore
signal #-G.D boolean DE true6 --item consumes a semaphore
begin
$2-)A#C2D process producer model
begin
$2-) YE false6
wait until #-G.6 ----produce item
$2-) YE true6
wait until not #-G.6
end process6
#-G.A,C2D process consumer model
>1
begin
#-G. YE true6
wait until $2-)6
#-G. YE false6
...consume item
wait until not $2-)6
end process6
end 5C0&@6
I41+0,+ ,"*"+/+!"
This branching statement is e%uivalent to the ones found in other programming
languages and, therefore, needs no further explanation.
S5!"*: =
(4 condition "6+!
se%uential statements B
J +0,(4 condition "6+!
se%uential statements B K
J +0,+
se%uential statements B K
+!% (4 B
C*,+ ,"*"+/+!"
This statement is also identical to its corresponding e%uivalent found in other
programming languages.
S5!"*: =
>>
'*,+ expression (,

36+! choices FH se%uential statements B
J 36+! others FH se%uential statements B K
+!% '*,+ B
Cither all-possible values of expression must be covered with choices or the case
statement has to be completed with an others branch.
E:*/70+ =
case 5#) is ------)ecoderD 5#) to <-.egment
when 300003 EZ =C) DE 3111111036
when 300013 EZ =C) DE 3110000036
when 300103 EZ =C) DE 3101101136
when 300113 EZ =C) DE 3111001136
when 301003 EZ =C) DE 3110010136
when 301013 EZ =C) DE 3011011136
when 301103 EZ =C) DE 3011111136
when 301113 EZ =C) DE 3110001036
when 310003 EZ =C) DE 3111111136
when 310013 EZ =C) DE 3111011136
when others EZ =C) DE 3-------36 ------dont care
end case6
N&00 ,"*"+/+!"
This statement is used for an explicit definition of branches without any further
commands. Therefore, it is used primarily in case statements, and also in if clauses.
S5!"*: =

!&00 B
>(
L$$7 ,"*"+/+!"
This is a conventional loop structure found in other programming languages.
S5!"*: =
J loop label = K 36(0+ condition 0$$7 b --controlled by condition
4$# identifier (! value1 to b downto value2 0$$7 b --with counter
0$$7 --endless loop
se%uential statements
+!% 0$$7 J loop label K B
E:*/70+ =
] D E 0 6
A1 D while ] Y 20 loop

] D E ] R 2 6

end loop A1 6
The while...loop statement has a 5oolean iteration scheme. If the iteration
condition evaluates true, executes the enclosed statements once. The iteration condition is
then reevaluated. &s long as the iteration condition remains true, the loop is repeatedly
executed. *hen the iteration condition evaluates false, the loop is s!ipped and execution
continues with the next loop iteration.

for i in 0 to 1 loop

^ + i / D E & + i / and 5 + i / 6

end loop 6
The for...loop statement has an integer iteration scheme. The integer range determines the
number of repetitions.
>'
^ D E 2 6 sum D E 1 6
@1 D loop
^ D E ^ R 1 6
sum D E sum S ( 6

exit when sum Z 100 6
end loop @1 6
The basic loop statement has no iteration scheme. It executes enclosed statements
repeatedly until it encounters an exit or next statement.

E:(" *!% N+:" ,"*"+/+!"
*ith these two statements a loop iteration can be terminated before reaching the
!eyword end loop. *ith next the remaining se%uential statements of the loop are s!ipped
and the next iteration is started at the beginning of the loop. The exit directive s!ips the
remaining statements and all remaining loop iterations. In nested loops both statements
s!ip the innermost enclosing loop if loop label is left out. -therwise, the loop labeled
loop label is terminated. The optional condition expression can be specified to determine
whether or not to execute these statements.
S5!"*: =
!+:" J loop label K J 36+! condition K B
E:*/70+ =
for I in 0 to ,&T =I, loop
if +)-GC+I/ E true/ then
next6 -----]ump to end loop
end if6
U+I/ YE &+I/6
end loop6
=1D while ] Y 10 loop outer loop
><
=2D while V Y 20 loop inner loop...
next =1 when ] E V6 4ump out of the inner loop...
end loop =26
end loop =16 ------4ump destination
S5!"*: =
+:(" J loop label K J 36+! condition K B
E:*/70+=
for I in 0 to ,&T =I, loop
if +U+I/ YE 0/ then
exit6 ------4ump out of the loop
end if6
U+I/ YE +& S I/6
end loop6 ------4ump destination
STRUCTURAL DESCRIPTION
In structural descriptions the implementation of a system or model is described as
a set of interconnected components, which is similar to drawing schematics. .uch a
description can often be generated with a @0)= netlister in a graphical development
tool. .ince there are many different ways to write structural descriptions, to explain all of
them in one section would be more confusing than enlightening. Therefore, only one
alternative approach is presented here.
S"#&'"&#*0 (/70+/+!"*"($! $4 * 4&00 *%%+#
&s an introductive example, consider the implementation of a full-adder circuit. The
components 0& and T-2 are assumed to be predefined elements.
E:*/70+ =
>?
architecture .T2A#TA2&= of ;A==&))C2 is
signal .1, #1, #2 D bit 6
component 0&
port + I1, I2 D in bit 6 ., # D out bit / 6
end component 6
component -2
port + I1, I2 D in bit 6 T D out bit / 6
end component6
begin
IG.T 0&1 D 0& port map + I1 EZ 5, I2 EZ #, . EZ .1, # EZ #1 / 6
IG.T 0&2 D 0& port map + I1 EZ &, I2 EZ .1, . EZ .A,, # EZ #2 / 6
IG.T -2 D -2 port map + I1 EZ #2, I2 EZ #1, T EZ #&22I/ 6
end .T2A#TA2&= 6
C$/7$!+!" %+'0*#*"($!
In the declarative part of the architecture, all ob4ects which are not yet !nown to
the architecture have to be declared. In the example above, these are the signals .1, #1
and #2 used for connecting the components together, excluding the ports of the entity
;A==&))C2. In addition, the components 0& and T-2 have to be declared. The
declaration of a component consists of declaring its interface ports and generics to the
actual model.
-ften used components could be selected from a library of gates defined in a
pac!age and lin!ed to the design. In this case the declaration of components usually is
done in the pac!age, which is visible to the entity. Therefore, no further declaration of the
components is re%uired in the architecture declarative part.
The actual structural description is done in the statement part of the architecture
by the instantiation of components. The components reference names IG.T 0&1, IG.T
0&2 and IG.T T-2, also !nown as instance names, must be uni%ue in the architecture.
The port maps specify the connections between different components, and between the
components and the ports of the entity. Thus, the components ports +so-called formals/
are mapped to the signals of the architecture +so-called actuals/ including the signals of
>7
the entity ports. ;or example, the input port I1 of the half adder IG.T 0&1 is connected
to the entity input signal 5, input port I2 to #, and so on. The instantiation of a
component is a concurrent statement. This means that the order of the instances within
the @0)= code is of no importance.
S5!"*: =

'$/7$!+!" component name
J -+!+#(' ; generic list = type name J =F expression K B I
generic list = type name J =F expression K < B K
J 7$#" ; signal list = mode type name B
signal list = mode type name <B K
+!% '$/7$!+!" B
C$/7$!+!" (!,"*!"(*"($!
& component instantiation statement defines a subcomponent of the design entity
in which it appears, associates signals or values with the ports of that subcomponent, and
associates values with generics of that subcomponent. This subcomponent is one instance
of a class of components defined by a corresponding component declaration, design
entity, or configuration declaration.
S5!"*: =
component label = component name 7$#" /*7 ; &ssociation-list < B
The &ssociation of ports to the connecting signals during the instantiation can be
done through the positional notation. &lternatively, it may be done by using the named
notation, using the already familiar format
T3$ "57+, $4 *,,$'(*"($!
$ositional &ssociation
Gamed &ssociation
(0
P$,("($!*0 A,,$'(*"($!
Cach actual in the component instantiation is mapped by position with each port in the
component declaration. The ordering of the actuals is therefore important.
A! *,,$'(*"($!10(," 4$#/
actual1, actual2 , actual1, eeee actualn

E:*/70+ =
@1 D nand2 port map + .1, .2, .1 / 6
If a port in a component instantiation is not connected to any signal. This purpose the
!eyword O7+! is used.

@1 D nand2 port map + .1, open, .1 / 6
N*/+% A,,$'(*"($!
The ordering of the association is not important since the mapping between the actuals
and formals is explicitly specified
A! *,,$'(*"($!10(," 4$#/
formal1 EZ actual1, formal2 EZ actual2 ,ee. formaln EZ actualn


E:*/70+ =
component nand2
port + &, 5 D in stdOlogic 6
# D out stdOlogic / 6
end component 6
(1
begin
@1D nand2 port map +& EZ .1, 5 EZ.2, # EZ .1 / 6
It is important to note that the symbol EZ is used within a port map in contrast to the
symbol YE used for concurrent or se%uential signal assignment statements. If one of the
ports has no signal connected to it, a reserved word open may be used. & function call can
replace the signal name. This allows direct type conversions at the component
instantiation.
CHAPTER 5
GENERICS AND CONFIGURATIONS
GENERICS
It allow static information to be communicated to a bloc! from its environment
for all architectures of a design unit. These include timing information li!e setup, hold,
delay times, part si"es, and other parameters.
S5!"*: =

J -+!+#(' ; list-of-generics-and-their-types < B K
(2
I" '*! ?+ %+'0*#+% *!5 $!+ $4 "6+ 4$00$3(!- =
Cntity )eclaration
#omponent )eclaration
#omponent Instantiation
#onfiguration .pecification
#onfiguration )eclaration
The generic si"e can be used inside the entity and in the architecture that matches the
entity. In this example, the generic si"e is defined as an integer with an initial value ?.
The si"es of the input and output ports of the entity increment are set to be ? bits unless
the value of the generic is overwritten by a generic map statement in the component
instantiation of the entity.
E:*/70+ =
entity increment is
generic + si"e D integer DE ? / 6
port + ivec D in bitOvector +0 to si"e-1/ 6
ovec D out bitOvector +0 to si"e-1// 6
end increment 6
The other ways of specifying the value of a generic are in a component instantiation.
A1 D and2 generic map +10/ port map + ), .1 / 6
A2 D or2 generic map +,EZ?/ port map + #, .2/ 6
CONFIGURATIONS
Ased to bind component instances to design entities and collect architectures to ma!e,
typically, a simulatable test bench. -ne configuration could create a functional simulation
(1
while another configuration could create the complete detailed logic design. *ith an
appropriate test bench the results of the two configurations can be compared.
& configuration does not have any simulation semantics associated with it6 it only
specifies how a top-level entity is organi"ed in terms of lower-level entities. The
component names and the entity names, as well as the port names and their order, are
different. The binding information can be specified using a configuration.
T3$ "57+, $4 ?(!%(!-
#onfiguration .pecification
#onfiguration )eclaration
C$!4(-&#*"($! ,7+'(4('*"($!
To bind component instantiations to specific entities stored in design libraries.
It appears in the declarations part of the architecture or bloc! in which the components
are instantiated
S5!"*: =
4$# list-of-comp-labels = component-name binding-indication B
The binding-indication specifies the entity represented by the entity-architecture
pair, and the generic and port bindings, and one of its forms is
&,+ +!"("5 entity-name J ; architecture-name < K
J -+!+#(' /*7 ; generic-association-list < K
J 7$#" /*7 ; port-association-list < K - - - - - - ;orm 1

The list of component labels may be replaced with the !eyword all to denote all
instance of a component6 it may also be the !eyword others to specify all as yet unbound
instances of a component.
(>
The generic map is used to specify the values for the generics or provide the mapping
between the generic parameters of the component and the entity to which it is bound. The
port map is used to specify the port bindings between the component and the bound
entity.
E:*/70+ =
=ibrary ieee6
use ieee.stdOlogicO11'>.all 6
entity 0&
port + &, 5 D in stdOlogic 6
.um,#a D out stdOlogic / 6
end 0& 6
architecture 0&Ostr of 0& is
component xor2
port + &, 5 D in stdOlogic 6
# D out stdOlogic / 6
end component 6
component and2
port + &, 5 D in stdOlogic 6
# D out stdOlogic / 6
end component 6
for T1 D xor2 use entity wor!.xor2 + xorOarch /6
for &1 D and2 use entity wor!.and2 + andOarch /6

begin

T1 D xor2 port map + &, 5, .um / 6
&1 D and2 port map + &, 5, #a/ 6

end 0&Ostr 6
((
C$!4(-&#*"($! %+'0*#*"($!,
The binding of component instances to design entities is performed by
configuration specifications6 such specifications appear in the declarative part of the
bloc! in which the corresponding component instances are created. In certain cases,
however, it may be appropriate to leave unspecified the binding of component instances
in a given bloc! and to defer such specification until later. & configuration declaration
provides the mechanism for specifying such deferred bindings.
S5!"*: =
'$!4(-&#*"($! identifier $4 entityOname (,
configurationOdeclarativeOpart
useOclause
b attributeOspecification
bloc!Oconfiguration
+!% J '$!4(-&#*"($! K J configurationOsimpleOname K B
The entity name identifies the name of the entity declaration that defines the
design entity at the apex of the design hierarchy. ;or a configuration of a given design
entity, both the configuration declaration and the corresponding entity declaration must
reside in the same library. If a simple name appears at the end of a configuration
declaration, it must repeat the identifier of the configuration declaration.
G-TC.
f& configuration declaration achieves its effect entirely through elaboration. There are
no behavioral semantics associated with a configuration declaration.
f& given configuration may be used in the definition of another, more complex
configuration.
('
E:*/70+ =
f &n architecture of a microprocessorD
architecture .tructureO@iew of $rocessor is
component &=A port + ggg /6 end component6
component ,AT port + ggg /6 end component6
component =atch port + ggg /6 end component6
begin
&1D &=A port map + ggg / 6
,1D ,AT port map + ggg / 6
,2D ,AT port map + ggg / 6
,1D ,AT port map + ggg / 6
=1D =atch port map + ggg / 6
=2D =atch port map + ggg / 6
end .tructureO@iew 6
f & configuration of the microprocessorD
library TT=, *or! 6
configuration @Oconfig of $rocessor is
use *or!.all 6
for .tructureO@iew
for &1D &=A use configuration TT=..G<>=.1?1 6
end for 6
for ,1,,2,,1D ,AT use entity ,ultiplex> +5ehavior/ 6
end for 6
for allD =atch
end for 6 f use defaults
end for 6
end configuration @Oconfig 6
(<
& bloc! configuration defines the binding of components in a bloc!, where a bloc! may
be an architecture body, a bloc! statement, or a generate statement.

S5!"*: $4 B0$'@ '$!4(-&#*"($! =
4$# bloc!-name
component-configurations
bloc!-configurations
+!% 4$# B
& bloc!-name is the name of an architecture body, a bloc! statement label, or a generate
statement label.
S5!"*: $4 C$/7$!+!"1'$!4(-&#*"($! =

4$# list-of-comp-labels = component-name
J binding-indication B K
J bloc!-configurations K
+!% 4$# B
There are two other forms of binding indication
&,+ '$!4(-&#*"($! configuration-name - - - - - - ;orm 2
&,+ $7+! - - - - - - ;orm 1

In ;orm 2, the binding indication specifies that the component instance are to be bound to
a configuration of a lower-level entity as specified by the configuration name. In ;orm
1,the binding indication specifies that the binding is not yet specified and is to be
deferred. 5oth these forms of binding indication may also be used in a configuration
specification.
E:*/70+ =
=ibrary TT= 6
(?
configuration 0&Oconfig of 0& is
for 0&OT&

for T1 D xor2
use entity wor!.Tor2 + xorO2 / 6
end for 6
for &1 D and2
use entity wor!.and2 + andO2 / 6
end for 6
end for 6
end 0&Oconfig 6

D(#+'" I!,"*!"(*"($!
It is possible to directly instantiate the entity-architecture pair or a configuration
in a component instantiation statement. This saves the additional binding step necessary
when using components.
Two additional forms of the component instantiation statement that can be used to
directly instantiate an entity or a configuration.
S5!"*: =

#omponent-label = +!"("5 entity-name
J ; architecture-name < K

J -+!+#(' /*7 ; generic-association-list < K
J 7$#" /*7 ; port-association-list < K B

#omponent-label = '$!4(-&#*"($! config-name

(7
J -+!+#(' /*7 ; generic-association-list < K
J 7$#" /*7 ; port-association-list < K B
G-TC
Go configuration declaration is necessary or possible in this case, since the component
instantiations directly instantiate the appropriate entity-architecture pairs or
configurations.
Go components declarations are necessary or possible.
E:*/70+ =
architecture 0&Ostr of 0& is
begin
T1 D entity wor!.xor2 + xor2 / port map + &, 5, . / 6
&1 D configuration TT=.and2 port map + &, 5,# / 6
end 0&Ostr 6
CHAPTER 6
SUBPROGRAMS AND PACKAGES
SUBPROGRAMS
There are two !inds of subprogramsD procedures and functions. 5oth procedures
and functions written in @0)= must have a body and may have declarations.
$rocedures perform se%uential computations and return values in global ob4ects
or by storing values into formal parameters.
;unctions perform se%uential computations and return a value as the value of
the function. ;unctions do not change their formal parameters.
.ubprograms may exist as 4ust a procedure body or a function body.
.ubprograms may also have a procedure declarations or a function declaration. *hen
'0
subprograms are provided in a pac!age, the subprogram declaration is placed in the
pac!age declaration and the subprogram body is placed in the pac!age body.
P#$'+%&#+ D+'0*#*"($!
S5!"*: =
7#$'+%&#+ identifier J + formal parameter list / K 6
;ormal parameters are separated by semicolons in the formal parameter list.
Cach formal parameter is essentially a declaration of an ob4ect that is local to the
procedure. The type definitions used in formal parameters must be visible at the place
where the procedure is being declared. Go semicolon follows the last formal parameter
inside the parenthesis. ;ormal parameters may be constants, variables, signals or files.
The default is variable. ;ormal parameters may have modes (!, (!$&" and $&" ;iles do
not have a mode. The default is (!.If no type is given and a mode of (! is used, constant is
the default.
E:*/70+ =
7#$'+%&#+ build + & D (! integer6
5 D (!$&" ,(-!*0 bitOvector6
# D $&" real6
) D 4(0+ / 6
P#$'+%&#+ B$%5
S5!"*: =
7#$'+%&#+ identifier J + formal parameter list / K (,
subprogram declaration
b subprogram body
b type declaration
b subtype declaration
b constant, ob4ect declaration
'1
b variable, ob4ect declaration
b alias declaration
b use clause
?+-(!
se%uential statement+s/
+!% 7#$'+%&#+ identifier 6

The procedure body formal parameter list is defined above in $rocedure
)eclaration. *hen a procedure declaration is used then the corresponding procedure
body should have exactly the same formal parameter list.
E:*/70+ =
type opOcode is + add, sub, mul, div / 6
procedure &=A + &, 5 D in integer 6
p D in opOcode 6
^ D out integer 6 / is
begin
case op is
when add EZ ^ YE & R 5 6
when sub EZ ^ YE & - 5 6
when mul EZ ^ YE & S 5 6
when others EZ ^ YE & 9 5 6

end case 6
P#$'+%&#+ C*00
$rocedures are invo!ed by using procedure calls.
S5!"*: =
J =abel K procedure-name + list-of-actuals / 6
'2
The actuals specify the expressions, signals, variables, or files, that are to be
passed into the procedure and the names of ob4ects that are to receive the computed
values from the procedure.
E:*/70+ =
#hec!Timing +t$=0, t$0=, #l!, ), U/6
F&!'"($! D+'0*#*"($!
S5!"*: =
4&!'"($! identifier J + formal parameter list / K #+"&#! aOtype 6
;ormal parameters are separated by semicolons in the formal parameter list.
Cach formal parameter is essentially a declaration of an ob4ect that is local to the
function. The type definitions used in formal parameters must be visible at the place
where the function is being declared. Go semicolon follows the last formal parameter
inside the parenthesis.
;ormal parameters may be constants, signals or files. The default is constant.
;ormal parameters have the mode (!. ;iles do not have a mode.
The reserved word 4&!'"($! may be preceded by nothing, implying 7&#+, 7&#+
or (/7&#+ . & 7&#+ 4&!'"($! must not contain a reference to a file ob4ect, slice,
subelement, shared variable or signal with attributes such as delayed, stable, %uiet,
transaction and must not be a parent of an impure function.
Gote -- The inout and $&" are not allowed for functions. The default is (!.
E:*/70+ =
4&!'"($! random #+"&#! float 6
4&!'"($! isOeven + & D integer/ #+"&#! boolean 6
'1
F&!'"($! B$%5
S5!"*: =
4&!'"($! identifier J + formal parameter list / K #+"&#! aOtype (,
subprogram declaration
b subprogram body
b type declaration
b subtype declaration
b constant, ob4ect declaration
b variable, ob4ect declaration
b alias declaration
b use clause
?+-(!
se%uential statement+s/
return someOvalue6 -- of type aOtype
+!% 4&!'"($! identifier 6
The function body formal parameter list is defined above in ;unction
)eclaration. *hen a function declaration is used then the corresponding function body
should have exactly the same formal parameter list.
E:*/70+ =
4&!'"($! random #+"&#! float (,
variable T D float6
?+-(!
#+"&#! T6 -- compute T
+!% 4&!'"($! random 6
F&!'"($! C*00
& function call is an expression and can also be used in large expressions.
S5!"*: =
f unction-name + list-of-actuals /
'>
The actuals may be associated by position or using named association.
sum D E sum R largest + maxOcoins, collection / 6
PACKAGES
& pac!age is used as a collection of often used data types, components, functions,
and so on. -nce these ob4ect are declared and defined in a pac!age, they can be used by
different @0)= design units. In particular, the definition of global information and
important shared parameters in complex designs or within a pro4ect team is recommended
to be done in pac!ages. It is possible to split a pac!age into a declaration part and the so-
called body. The advantage of this splitting is that after changing definitions in the
pac!age body only this part has to be recompiled and the rest of the design can be left
untouched. Therefore, a lot of time consumed by compiling can be saved.
P*'@*-+ %+'0*#*"($!,
& pac!age declaration defines the interface to a pac!age. The scope of a
declaration within a pac!age can be extended to other design units.
S5!"*: =
7*'@*-+ packageOname (,
pac!ageOdeclarativeOpart D
subprogramOdeclaration
b typeOdeclaration
b subtypeOdeclaration
b constantOdeclaration
b signalOdeclaration
b aliasOdeclaration
b componentOdeclaration
b attributeOdeclaration H specification
b useOclause
'(
+!% J 7*'@*-+ K J packageOname K 6
If a name appears at the end of the pac!age declaration, it must repeat the name of the
pac!age declaration. If a pac!age declarative item is a type declaration, then that
protected type definition must not be a protected type body. Items declared immediately
within a pac!age declaration become visible by selection within a given design unit
wherever the name of that pac!age is visible in the given unit. .uch items may also be
made directly visible by an appropriate use clause.
G-TCfGot all pac!ages will have a pac!age body. In particular, a pac!age body is
unnecessary if no subprograms, deferred constants, or protected type definitions are
declared in the pac!age declaration.
E:*/70+ =
f & pac!age declaration that needs no pac!age bodyD
pac!age Time#onstants is
constant t$=0 D Time DE 10 ns6
constant t$0= D Time DE 12 ns6
constant t$=^ D Time DE < ns6
end Time#onstants 6
f & pac!age declaration that needs a pac!age bodyD
pac!age ,I $&#V is
type .$CC) is +.T-$, .=-*, ,C)IA,, ;&.T/6
component 0&
port +I1, I2 D in bit6 ., # D out bit/6
end component6
constant )C=&I TI,C D time6
function IGT25IT @C# +IGT @&=AC D integer/ return bit vector6
end ,I $&#V6
''
P*'@*-+ ?$%(+,
& pac!age body defines the bodies of subprograms and the values of deferred
constants declared in the interface to the pac!age.
S5!"*: =
7*'@*-+ ?$%5 pac!ageOname (,
pac!ageObodyOdeclarativeOpart
subprogramOdeclaration
b subprogramObody
b typeOdeclaration
b subtypeOdeclaration
b constantOdeclaration
b aliasOdeclaration
b useOclause
+!% J 7*'@*-+ ?$%5 K J pac!ageOname K B
The name at the start of a pac!age body must repeat the same name. In addition to
subprogram body and constant declarative items, a pac!age body may contain certain
other declarative items to facilitate the definition of the bodies of subprograms declared
in the interface.
Items declared in the body of a pac!age cannot be made visible outside of the
pac!age body. If a given pac!age declaration contains a deferred constant declaration,
then a constant declaration with the same identifier must appear as a declarative item in
the corresponding pac!age body. This ob4ect declaration is called the full declaration of
the deferred constant. The subtype indication given in the full declaration must conform
to that given in the deferred constant declaration. *ithin a pac!age declaration that
contains the declaration of a deferred constant, and within the body of that pac!age, the
use of a name that denotes the deferred constant is only allowed in the default expression
for a local generic, local port, or formal parameter. The result of evaluating an expression
that references a deferred constant before the elaboration of the corresponding full
declaration is not defined by the language.
'<
E:*/70+ =
pac!age body ,I $&#V is
constant )C=&I TI,C D time DE 1.2( ns6
function IGT25IT @C# +IGT @&=AC D integer/return bit vector is
begin
-- se%uential behavioral description
end IGT25IT @C#6
end ,I $&#V6
The binding between the pac!age declaration and the body is established by using the
same name. In the above example it is the pac!age name ,I $&#V.
$ac!ages must be made visible before their contents can be used. The A.C clause ma!es
pac!ages visible to entities, architectures, and other pac!ages.
S5!"*: =
U,+ libraryOname . $ac!ageOname . *00 B
E:*/70+ =
-- use only the binary and addObits1 declarations
A.C wor! .myOstuff.binary, myOstuff.addObits16

... CGTITI declaration...
... &2#0ITC#TA2C declaration ...
-- use all of the declarations in pac!age myOstuff
A.C wor! .myOstuff.&==6

... CGTITI declaration...
'?
... &2#0ITC#TA2C declaration...
CHAPTER
ADVANCED FEATURES
Benerate .tatements
&liases
&ttributes
'7
GENERATE STATEMENTS
#oncurrent statements can be conditionally selected or replicated during the
elaboration phase. The generate .tatement provides for a compact description of regular
structures such as memories, registers, and counters.
T3$ 4$#/, $4 "6+ G+!+#*"+ S"*"+/+!"
;or-generation .cheme
If-generation .cheme
F$#1G+!+#*"($!
#oncurrent statements can be replicated a predetermined number of times.
S5!"*: =
generate-label = 4$# generate-identifier (! discrete-range -+!+#*"+
J bloc!-declarations
?+-(! K
concurrent statements
+!% -+!+#*"+ J generate-label K B
The values in the discrete range must be globally static, that is, they must be computable
at elaboration time.
These statements can also use the generate identifier in their expressions, and its value
would be substituted during elaboration for each replication.
The type of identifier is defined by the discrete range. )eclarations, if present, declare
items
that are visible only within the generate statement.
E:*/70+ =
A1 D for ; in 1 downto 0 generate
sum + ; / YE & + ; / xor 5 + ; / xor # + ; /
ca + ; R 1 / YE & + ; / and 5 + ; / and # + ; /
<0

end generate A1 6
I41G+!+#*"($!

#oncurrent statements can be conditionally elaborated.
S5!"*: =
generate-label = (4 expression -+!+#*"+
J bloc!-declarations
?+-(! K
concurrent statements
+!% -+!+#*"+ J generate-label K B
This statement allows for conditional selection of concurrent statements based on the
value of an expression.
This expression must be a globally static expression, that is, the value must be
computable at elaboration time.
&ny declarations present are again local to the generate statement.
E:*/70+ =
@1 D if Aser E lowO)ly generate

^ YE & after 2 ns 6

end generate @1 6

@2 D if Aser E highO)ly generate
^ YE & after 2( ns 6

<1
end generate @2 6
ALIASES
&n alias is an alternate name for an existing ob4ect. 5y using an alias of an ob4ect,
you actually use the ob4ect to which it refers. 5y assigning to an alias, you actually assign
to the ob4ect to which the alias refers.
S5!"*: =
*0(*, identifier = subtypeOindication (, name B
& reference to an alias is interpreted as a reference to the ob4ect or part corresponding to
the alias.
E:*/70+ =
variable instr D bitOvector+11 downto 0/6
alias opOcode D bitOvector+< downto 0/ is instr+11 downto 2>/6
declares the name op_code to be an alias for the left-most eight bits of instr.

signal vec D stdOlogicOvector +> downto 0/ 6
alias midObit D stdOlogic is vec+2/ 6
-- &ssignment D
midObit YE L0L 6
-- is the same as
vec+2/ YE L0L 6
&liases are often useful in unbound function calls. ;or instance, if you want to
ma!e a function that ta!es the &G) operation of the two left most bits of an arbitrary
<2
array parameter. If you want to ma!e the function general enough to handle arbitrary
si"ed arrays, this function could loo! li!e thisD
function leftOand +arrD stdOlogicOvector/ return stdOlogic is
begin
return arr+arrLleft/ and arr+arrLleft-1/ 6
end leftOand 6
---- ;unction does not wor! for ascending index ranges of arr.
This function will only wor! correctly if the index range of arr is descending
+downto/. -therwise, arrLleft-1 is not a valid index number. @0)= does not have a
simple attribute that will give the one-but-leftmost bit out of an arbitrary vector, so it will
be difficult to ma!e a function that wor!s correctly both for ascending and descending
index ranges. Instead, you could ma!e an alias of arr, with a !nown index range, and
operate on the aliasD
function leftOand +arr D stdOlogicOvector/ return stdOlogic is
alias aliasedOarr D stdOlogicOvector +0 to arrLlength-1/ is arr 6
begin
return aliasedOarr+0/ and aliasedOarr+1/ 6
end leftOand 6
---- ;unction wor!s for both ascending and descending index ranges of arr.
ATTRIBUTES
<1
It is a value, function, type, range, signal, or constant that can associated with
certain names. .uch as an entity name, an architecture name, a label, or a signal
U,+#1%+4(!+% A""#(?&"+,
Aser-defined attributes are constants of any type, except access or file type. They
are declared using attribute declarations
Aser-defined attributes are useful for annotating language models with tool-specific
information.
A""#(?&"+ D+'0*#*"($!,
It declares the name of the attribute and its type.
S5!"*: A E:*/70+ =
*""#(?&"+ attribute-name = value-type B
type ;arads is range 0 to (000 6
units
pf 6
end units 6
attribute capacitance D ;arads 6
These user-defined attribute with a name and to assign a value to the attribute.
A""#(?&"+ S7+'(4('*"($!
It is used to associate a user-defined attribute with a name and to assign a value to the
attribute.
S5!"*: =
*""#(?&"+ attribute-name $4 item-names = name-class (, expression B
<>
The item-names is a list of one or more names of an entity, architecture,
configuration, component, label, signal, variable, constant, type, subtype, pac!age,
procedure, or function. The name-class indicates the class type, that is, whether it is an
entity, architecture, label, or others.
The expression, whose value must belong to the type of attribute, specifies the value of
the attribute.
E:*/70+ =
attribute length of 2TO2dy D signal is 1 micron 6
attribute capacitance of cl!, rst D signal is 20 pf 6
The item-name in the attribute specification can also be replaced with the !eyword all to
indicate all names belonging to that name-class.
E:*/70+ =
attribute capacitance of all D variable is 10 pf 6
&fter having created an attribute and then associated it with a name, the value of the
attribute can then be used in an expression. &n attribute indicates a specific property of
the signal, and is of a defined type. Asing attributes at the right places creates a very
flexible style of writing @0)= code.
S5!"*: =
item-name M attribute-name
E:*/70+ =
signal vectorOup D bitOvector +> to 7/ 6
signal vectorOdwn D bitOvector +2( downto 0/ 6
vectorOdwnL=C;T -- returns integer 2(
vectorOdwnL2&GBC -- returns range 2( to 0
<(
TC@CGT -- T2AC when there is an event on signal T
I0IB0 -- returns the highest value in the range of I
vectorOupL2IB0T -- returns integer 7
vectorOupL2&GBC -- returns range > to 7
<'