Computer Architecture and the Fetch-Execute Cycle

John Von Neumann introduced the idea of the stored program. Previously data and programs were stored in separate memories. Von Neumann realised that data and programs are indistinguishable and can, therefore, use the same memory. This led to the introduction of compilers which accepted text as input and produced binary code as output. The Von Neumann architecture uses a single processor which follows a linear sequence of fetch-decode-execute. In order to do this, the processor has to use some special registers. These are: Register Meaning PC Program Counter CIR Current Instruction Register MAR Memory Address Register MDR Memory Data Register Accumulator Holds results The program counter keeps track of where to find the next instruction so that a copy of the instruction can be placed in the current instruction register. Sometimes the program counter is called the Sequence Control Register (SCR) as it controls the sequence in which instructions are executed. The current instruction register holds the instruction that is to be executed. The memory address register is used to hold the memory address that contains either the next piece of data or an instruction that is to be used. The memory data register acts like a buffer and holds anything that is copied from the memory ready for the processor to use it. The central processor contains the arithmetic-logic unit (also known as the arithmetic unit) and the control unit. The arithmetic-logic unit (ALU) is where data is processed. This involves arithmetic and logical operations. Arithmetic operations are those that add and subtract numbers, and so on. Logical operations involve comparing binary patterns and making decisions. The control unit fetches instructions from memory, decodes them and synchronises the operations before sending signals to other parts of the computer. The accumulator is in the arithmetic unit, the program counter and the instruction registers are in the control unit and the memory data register and memory address register are in the processor. A typical layout is shown in Fig. 4.3.1.1 which also shows the data paths. Main Memory 4.3.2 The Fetch-Decode-Execute-Reset Cycle The following is an algorithm that shows the steps in the cycle. At the end the cycle is reset and the algorithm repeated. Load the address that is in the program counter (PC) into the memory address register (MAR). Increment the PC by 1. Load the instruction that is in the memory address given by the MAR into the memory data register (MDR). Load the instruction that is now in the MDR into the current instruction register (CIR). Decode the instruction that is in the CIR. If the instruction is a jump instruction then a. Load the address part of the instruction into the PC b. Reset by going to step 1. Execute the instruction. Reset by going to step 1.

Steps 1 to 4 are the fetch part of the cycle. Steps 5, 6a and 7 are the execute part of the cycle and steps 6b and 8 are the reset part. Step 1 simply places the address of the next instruction into the memory address register so that the control unit can fetch the instruction from the right part of the memory. The program counter is then incremented by 1 so that it contains the address of the next instruction, assuming that the instructions are in consecutive locations. The memory data register is used whenever anything is to go from the central processing unit to main memory, or vice versa. Thus the next instruction is copied from memory into the MDR and is then copied into the current instruction register. Now that the instruction has been fetched the control unit can decode it and decide what has to be done. This is the execute part of the cycle. If it is an arithmetic instruction, this can be executed and the cycle restarted as the PC contains the address of the next instruction in order. However, if the instruction involves jumping to an instruction that is not the next one in order, the PC has to be loaded with the address of the instruction that is to be executed next. This address is in the address part of the current instruction, hence the address part is loaded into the PC before the cycle is reset and starts all over again. 4.3.3 Other Architectures Using the above architecture for a microprocessor illustrates that basically an instruction can be in one of three phases. It could be being fetched (from memory), decode (by the control unit) or being executed (by the control unit). An alternative is to split the processor up into three parts, each of which handles one of the three stages. This would result in the situation shown in Fig. 4.3.3.1, which shows how this process, known as pipelining, works. Instruction 1 Instruction 2 Instruction 1 Instruction 3 Instruction 2 Instruction 1 Instruction 4 Instruction 3 Instruction 2 Instruction 5 Instruction 4 Instruction 3 Fig. 4.3.3.1 This helps with the speed of throughput unless the next instruction in the pipe is not the next one that is needed. Suppose Instruction 2 is a jump to Instruction 10. Then Instructions 3, 4 and 5 need to be removed from the pipe and Instruction 10 needs to be loaded into the fetch part of the pipe. Thus, the pipe will have to be cleared and the cycle restarted in this case. The result is shown in Fig. 4.3.3.2

Instruction 1 Instruction 2 Instruction 1 Instruction 3 Instruction 2 Instruction 1 Instruction 4 Instruction 3 Instruction 2 Instruction 10

Instruction 11 Instruction 10 Instruction 12 Instruction 11 Instruction 10 Fig. 4.3.3.2 Another method that is used is to have array processors. This involves more than one arithmetic-logic unit but still only one processor. This is particularly useful when processing data held in a one-dimensional array when the same operation is to be applied to every element of the array. An example is where all the values represent the costs of different items in stock and it is required to find the selling prices which are calculated by adding the same percentage to each value. An extension of array processors is to use parallel processors. This system uses many independent processors working in parallel on the same program. One of the difficulties with this is that the programs running on these systems need to have been written specially for them. If the programs have been written for standard architectures, then some instructions cannot be completed until others have been completed. Thus, checks have to be made to ensure that all prerequisites have been completed. However, these systems are in use particularly when systems are receiving many inputs from sensors and the data need to be processed in parallel. A simple example that shows how the use of parallel processors can speed up a solution is the summing of a series of numbers. Consider finding the sum of n numbers such as 2 + 4 + 23 + 21 + …. + 75 + 54 + 3 Using a single processor would involve (n – 1) additions one after the other. Using n/2 processors we could simultaneously add n/2 pairs of numbers in the same time it would take a single processor to add one pair of numbers. This would leave only n/2 numbers to be added and this could be done using n/4 processors. Continuing in this way the time to add the series would be considerably reduced. 4.3.4 Example Questions The questions in this section are meant to mirror the type and form of questions that a candidate would expect to see in an exam paper. As before, the individual questions are each followed up with comments from an examiner. 1. The Program Counter (Sequence Control Register) is a special register in the processor of a computer. a) Describe the function of the program counter. (2) b) Describe two ways in which the program counter can change during the normal execution of a program, explaining, in each case, how this change is initiated. (4) c) Describe the initial state of the program counter before the running of the program. (2) A. a) -The program counter stores the address… -of the next instruction to be carried out in the sequence of the program. (2) b) -P.C. is incremented… -as part of the fetch execute cycle. -P.C. is altered to the value being held in the address part of the instruction… -When the instruction is one that alters the normal sequence of instructions in the program. -This second type of command involves the P.C. being reset twice in the same cycle. (4) c) -The P.C. will contain the address of the first instruction in the sequence to be run… -this must have been placed in the register by some external agent, the program loader. (2) Notes: Part (a) is often poorly understood by students. The majority believing that the program counter is used to keep track of the number of programs running, or the order in which programs have been called. There is obviously a confusion with the idea of a stack storing return addresses of modules when they have been called. Part (b) illustrates a characteristic of true examination questions. Most genuine questions

will have more mark points available than there are marks for the question. This is not true of these sample questions. It should also be remembered that these sample questions have not been through the rigorous testing process that a genuine paper would have undergone, so any problems with the content should not be repeated in the examination. Candidates find difficulty in making the distinction between different types of instruction, it may be of value to spend some time talking about arithmetic/logic/jump/ command type instructions as they all affect the cycle in different ways. Part (c) refers back to the AS work in the need to understand that the loader will initially set the value of the P.C. so that the program can begin. 2. Explain what is meant by the term Von Neumann Architecture. (2) A. -A way of looking at the relationships between the various pieces of hardware in a computer processor. -A single memory used to store program instructions and the data for use with those instructions. -A single processor is used which follows a linear sequence of instructions. (2) Notes: Many students will be content with the correct answer that VN architecture is the ability to store the instructions and data in the same memory. However, a look at the mark allocation shows that something else is required or only one mark would have been available. Always look at the mark allocation and think of the examiner, is there enough in the answer given to be able to award the full number of marks? 3. Describe the fetch/decode part of the fetch/decode/execute/reset cycle, explaining the purpose of any special registers that you have mentioned. (7) A. -Contents of PC loaded into MAR -PC is incremented -Contents of address stored in MAR loaded into MDR -Contents of MDR loaded into CIR -Instruction in CIR is decoded. -PC (program counter) stores the address of the next instruction to be executed. -MAR (memory address register) holds the address in memory that is currently being used -MDR (memory data register) holds the data (or instruction) that is being stored in the address accessed by the MAR. -CIR (current instruction register) holds the instruction which is currently being executed. (7) Notes: The whole cycle may be asked for in some questions but it is more likely that it would be split up in some way in order to make the question shorter and more accessible. This is a difficult question because there is no splitting up of the points asked for, the student must rely on their own interpretation of the requirements of the question. There is a hint in the question because it asks for two parts of the cycle specifically, but students should be aware that that becomes a part of the question, in other words the answer must not contain any further information because it has been specifically ruled out in the question. A candidate who describes the execution of particular types of instruction has demonstrated that they cannot differentiate between the parts of the cycle and would probably be penalised. 4. a) Describe how pipelining normally speeds up the processing done by a computer. (2) b) State one type of instruction that would cause the pipeline system to be reset, explaining why such a reset is necessary. (3) A. a) -All instructions have three phases… -which are treated separately, by different parts of the processor… -so that more than one instruction can be being dealt with simultaneously. (2) b) -Jump instruction -The instructions in the pipeline are no longer the ones to be dealt with next… -so the pipeline has to be reset. (3)

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