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Design and Evaluation of a Low-Cost

High-Performance ADC for Embedded Control

Systems in Induction Heating Appliances

Oscar Jimenez, Student Member, IEEE, Oscar Lucia, Member, IEEE, Isidro Urriza,

Luis A. Barragan, and Denis Navarro

AbstractThe advantages of resonant power converters, such

as high efciency and high power density, make them a suitable

solution for domestic applications such as induction heating (IH)

cookers. The control systems of these appliances require perform-

ing accurate and smooth power control while assuring the safety

of the power devices. In order to accomplish these tasks, it is nec-

essary to have information about the target output power, which

is selected by the user, and the specic parameters of the out-

put current. In this paper, a single-bit second-order sigmadelta

() analog-to-digital converter (ADC) is proposed to measure

the magnitude of interest in resonant power converters. An opti-

mized digital low-pass lter architecture is proposed to extract the

output current from the digitized bit stream. This lter improves

the accuracy while having low logic-resource consumption. The

proposed ADC has been veried using a resonant inverter applied

to the IH cooktop application. The inverter switching frequency

is in the range of 4080 kHz. A statistical analysis of the nal

measurement system has been performed to assess the system

accuracy. The proposed system achieves good accuracy in the

inverter operating range.

Index TermsAnalog-to-digital converter (ADC), digital con-

trol, induction heating (IH), resonant power conversion.

I. INTRODUCTION

T

HE DOMESTIC induction heating (IH) market has ex-

perienced in recent years a signicant growth due to its

advantages such as safety, cleanliness, and higher efciency [1],

in comparison with its other classical counterparts. Fig. 1(a)

shows the block diagram of an IH system. The IH system is

composed of four main subsystems: a user interface, a power

converter, a digital control system, and a sigmadelta ()

analog-to-digital converter (ADC).

The user interface allows users to select the power delivered

to the vessel. The power converter transfers mains power to the

Manuscript received December 27, 2012; revised April 4, 2013 and

June 19, 2013; accepted August 4, 2013. Date of publication August 15, 2013;

date of current version October 18, 2013. This work was supported in part

by the Spanish Ministry of Science and Innovation under Project TEC2010-

19207, Project CSD2009-00046, Project IPT-2011-1158-920000, and FPU

Grant AP2010-5267, in part by the Diputacin General de Aragn-Fondo

Social Europeo (DGA-FSE), and in part by the Bosch and Siemens Home

Appliances Group.

The authors are with the Department of Electronic Engineering and

Communications, University of Zaragoza, 50018 Zaragoza, Spain (e-mail:

ojimenez@unizar.es).

Color versions of one or more of the gures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identier 10.1109/TIE.2013.2278524

load. Manufacturers usually choose resonant power converters

due to their high efciency and high power density implemen-

tation. The most used topologies in domestic IH are half-bridge

[2], [3], full-bridge [4], single-switch [5], and multiinverter

topologies [6], [7]. In this paper, the power converter features

a half-bridge resonant converter operating with switching fre-

quency f

sw

between 40 and 80 kHz. In order to reduce the

commutation losses, the half-bridge converter operates under

zero-voltage-switching conditions. The resonant load of the

power converter consists of a planar inductor situated below a

vessel and a series resonant capacitor C

r

. Usually, the coupling

between the inductor coil and the pan is modeled as a equivalent

series resistor R

eq

and inductor L

eq

[8]. Fig. 1(b) shows the

main waveforms of the power inverter.

The digital control system controls the power transferred to

the pan by adjusting the modulation parameters of the rst

power stage [7], [9], [10]; then, it performs the other required

tasks, such as verifying the proper switching conditions [11].

In order to assure that the power devices of the inverter are

kept inside the safe operational area, the control system re-

quires the values of the following parameters of output current

i

o

[see Fig. 1(b)]: peak value i

o, peak

, mean of the absolute

value i

o, mean

, and rms value i

o, rms

. These measurements are

computed at each half period of the mains T

B

. Then, the

control system can be divided into two blocks: the control unit

and the measurement block. The control unit block generates

the gating signals of the power devices (S1 and S2), taking

into account user input and output current measurements. The

measurement block measures the required current parameters

from the reconstructed output current i

r

provided by the

ADC. Despite that the nal system will be implemented in

an application-specic integrated circuit, in this paper, eld-

programmable gate array (FPGA) technology is used to verify

the digital system [12], [13].

The ADC subsystem digitizes the output current.

modulators are widely used in power electronics either

as ADCs [14][18] or pulsewidth modulators [19][21].

ADCs combine oversampling and shaping of the quantization

noise to achieve high accuracy, which makes them a cost-

effective and efcient solution [18], [22], [23]. Due to do-

mestic IH being a cost-oriented application and the trend to

implement multiload hobs [24], this paper proposes a second-

order ADC as a cost-effective solution. Despite that some

integrated ADCs are available [16], [18], the modulator

0278-0046 2013 IEEE

2602 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 5, MAY 2014

Fig. 1. Domestic IH system. (a) General block diagram. (b) Power converter waveforms.

is implemented with discrete elements to optimize the converter

according to the target application.

The output current digitization is carried out in three steps.

First, the output current is sensed and conditioned to the

modulator dynamic range (DR). The conditioning circuit con-

sists of a current transformer with a turns ratio of CTR, and

a burden resistor R

T

. Second, a modulator digitizes the

conditioned output current x(t) into a single-bit data stream

i

bs

. Finally, the digital low-pass lter (LPF) block reconstructs

output current i

r

by ltering i

bs

.

The aim of this paper is to propose a measurement system for

measuring the current parameters of the power stage required

by the IH control system. This paper presents the analysis and

design of the ADC, the experimental verication of the

proposed system and, nally, a calibration process in order to

assess the quality of the measurements.

Several works have proposed rst-order single-bit

ADCs to digitize the output current of IH systems [1], [14].

Although this converter architecture has very low cost im-

plementation and achieves good accuracy in power measure-

ment, the measurements of current parameters, particularly

the peak current, do not achieve the desired accuracy. Hence,

this paper proposes a second-order single-bit ADCs in

order to improve the accuracy of the measurement system

while maintaining low-cost solution. The improvement of the

measurement quality would allow a control system to perform

a better control algorithm and to ensure the safety of the

converter. In [25], a second-order single-loop single-bit

ADC is presented for measuring the magnitude of interest in

power converters connected to a dc power supply. Based on

this study, we propose to use a ADC to measure the

output current in half-bridge power converters used in domestic

IH appliances [1]. The analysis presented in [25] has been

extended to cover rectied ac power supply, as shown in Fig. 1.

Several oversampling ratios (OSRs) have been considered, and

a statistical analysis of the nal measurement system has been

carried out in order to evaluate the system accuracy.

This paper is organized as follows. Section II explains the

modulator design. Section III describes the ADC

digital lter design. The main experimental results are shown

in Section IV. The calibration process is detailed in Section V.

Finally, the conclusions of this paper are drawn in Section VI.

Fig. 2. Second-order modulator block diagrams. (a) Continuous-time

diagram. (b) Discretized and linearized block diagram.

II. SIGMADELTA MODULATOR DESIGN

A. SigmaDelta Modulator Analysis

ADCs [26] use the modulation noise-shaping

property and oversampling techniques to allow high-resolution

conversion. Assuming white quantization noise, the oversam-

pling technique reduces the in-band quantization noise spread-

ing its power along the frequency range dened by sampling

frequency f

s

. Thus, the sampling frequency is usually selected

to be signicantly higher than the Nyquist rate. The sampling

frequency sets the OSR, which is dened as the quotient be-

tween sampling frequency f

s

and the Nyquist rate of the signal.

In addition, the noise-shaping property place most of the quan-

tization noise in the high frequency range to minimize in-band

noise. The noise shape depends on the modulator order.

Higher modulator orders allow higher in-band noise reduction.

Nevertheless, single-loop single-bit modulators with an

order higher than two have instability issues [26]. Thus, in

this paper, a continuous-time second-order single-loop single-

bit ADC has been chosen.

Fig. 2(a) shows the continuous-time block diagram of a

second-order single-loop single-bit modulator. It consists

of two integrator stages, a single-bit quantizer, and a sample-

and-hold circuit. This ADC digitizes input signal x(t) into

JIMENEZ et al.: DESIGN AND EVALUATION OF ADC FOR EMBEDDED CONTROL SYSTEMS 2603

single-bit signal i

bs

(k) at sampling rate f

s

. Fig. 2(b) shows the

linearized and discretized second-order modulator block

diagram. The transformation from the continuous-time domain

to the discrete-time domain has been done using the forward

Euler method. Thus, the integrators transfer functions are

I

1

(z) =

1

(1 z

1

)

(1)

I

2

(z) =

z

1

(1 z

1

)

. (2)

The rst integrator I

1

does not consider the delay term in the

numerator in order to obtain delay unity in the signal-to-output

transfer function (STF). In addition, sampling period T

s

has

been included in coefcients and to simplify the equations.

The relationships between the continuous-time and discrete-

time coefcients are

x

= a

x

T

s

and

x

= b

x

T

s

, respectively.

The nonlinear quantizer has been modeled as white noise

source n plus gain factor k

q

[26]. The STF and the noise-to-

output transfer function (NTF) for the proposed ADC are

STF =

y(z)

x(z)

=

k

q

2

z

1

1 +z

1

(k

q

2

+k

q

2

2) +z

2

(1 k

q

2

)

(3)

NTF =

y(z)

n(z)

=

(1 z

1

)

2

1 +z

1

(k

q

2

+k

q

2

2) +z

2

(1 k

q

2

)

. (4)

Thus, the low-frequency gain of the modulator is

G

= STF(z = 1)

1

. (5)

The modulator coefcients (

1

,

2

,

1

, and

2

) de-

ne the ADC performance, which can be specied with the

converter attributes shown in Fig. 3, i.e., SNR, the signal-

to-noise-plus-distortion ratio (SNDR), the overload amplitude

level (OL), and the DR [26]. Fig. 3 shows how SNR and

SNDR curves fall for higher amplitudes. The OL point is the

maximum amplitude of the input sinusoidal signal, for which

the modulator still works correctly. In this paper, the OL point is

set at the amplitude where the SNDR falls 6 dB below the peak

SNDR value. Finally, the DR value is the rms amplitude range

between the smallest detectable amplitude and the overload

level.

The converter attributes also depend on the OSR. Due

to the fact that, in this paper, the clock frequency of the digital

systemis f

clk

= 40 MHz, three sampling frequencies have been

analyzed: 10, 20, and 40 MHz. Considering an input signal

bandwidth of B

i

= 250 kHz, the selected sampling frequencies

entail the following OSRs, respectively, i.e., 20, 40, and 80.

The converter coefcients and the OSR have been chosen

through Matlab simulations [27]. The simulation test bench

consists of two simulation levels. The rst level obtains the

SNR or SNDR value for a specic set of converter parameters

at a given input signal amplitude A

in

. In this level, an input

Fig. 3. Second-order ADC performance characteristics for f

s

=

20 MHz,

1

= 0.134,

1

= 0.15,

2

= 0.7, and

2

= 0.448.

signal composed by a sine wave (175 kHz for SNR and 75 kHz

for SNDR) of amplitude A

in

and white noise (

2

N

= 130 dB)

is used. The output bit stream is ltered by an eighth-

order Butterworth LPF with a cutoff frequency of f

c

= B

i

to remove all out-of-band noise. Finally, the IEEE sine-wave

tting method [28] is applied to the ltered signal to extract

the SNR or SNDR value at this amplitude. The second level

of simulation, making use of the rst level, performs amplitude

sweeps of the input signal to obtain the SNR and SNDR curves.

Prior to the converter coefcient selection, two design con-

straints are introduced.

1) Stability criteria: The modulator has to be stable,

which means that

2

1

/

2

< 3/4, as in [27].

2) Full-scale (FS) input support: The modulator op-

erates in a high-noise environment due to the presence of

a switched-mode inverter. To maximize the input signal

x(t) SNR parameter, it is advisable to make the most

of the ADC input range. Thus, the modulator is

designed to operate with an FS input, i.e., OL = FS.

The FS value takes the value of the supply voltage V

CC

when implementing a dual supply or half of it when

implementing a single supply. The overload level can be

tuned using coefcient

1

. For specic

2

,

1

, and

2

co-

efcients, the SNR and SNDR curves can be horizontally

shifted by tuning

1

, and consequently, OL is also shifted.

If coefcient

1

is increased, the curves are shifted to

the left.

B. Selection Procedure

The selection procedure can be divided into two steps. In

the rst step, different converters with an ADC gain of 1, i.e.,

1

=

1

, have been tested for the three OSRs. This analysis

allows extracting the attributes of the converter for specic

1

,

2

, and

2

coefcients. However, FS input support is not

assured. The second step modies the gain of the converter by

selecting coefcient

1

for conguring the converter with FS

input support.

The converters analyzed in the rst step of the selection

process are the combination of coefcients

1

and

2

in the

range of [0.05, 1] with a step of 0.05, and the coefcient

2

in the range of [S

lim

, 5S

lim

] with a step of 0.2 S

lim

, where

S

lim

is the stability limit with respect to

2

and

2

, i.e.,

2

> S

lim

=

2

1

4/3. For each converter, the SNR and SNDR

curves have been obtained in order to extract the attributes

2604 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 5, MAY 2014

Fig. 4. SNR curves of the best analyzed second-order converter for

each OSR.

of the converter. The chosen converter parameters are those

that yield the maximum values of SNR and SNDR. Fig. 4

shows the SNR curves of the converters selected for each OSR

value. The coefcients of the converter with OSR = 20 are

1

=

1

= 0.25,

2

= 0.6, and

2

= 0.44; the coefcients of

the converter with OSR = 40 are

1

=

1

= 0.15,

2

= 0.7,

and

2

= 0.448; and the coefcients of the converter with

OSR = 80 are

1

=

1

= 0.15,

2

= 0.5, and

2

= 0.28. As

expected, the attributes of the converter with OSR = 40 signif-

icantly improve the attributes of the converter with OSR = 20.

However, due to system noise, the attributes of the converter

with OSR = 80 slightly improve the attributes of the converter

with OSR = 40. In view of these results, a second-order

ADC with OSR = 40 has been chosen to be implemented.

The second step of the selection process tunes the

1

coef-

cient to obtain FS input support, leading to

1

= 0.134. The

integrator coefcients result in the ADC performance shown

in Fig. 3, where SNR

max

= 56.7 dB, SNDR

max

= 54.2 dB,

OL = FS, DR = 58.1 dB, and gain G = 0.89.

C. Circuit Implementation

The schematic circuit of the designed ADC is shown

in Fig. 5. The supply voltage of the converter is V

CC

= 3.3 V.

The relationship between the passive components and the

modulator coefcients are given by

R

n

C

n

=

1

f

s

n

(6)

where

n

=

1

,

2

,

1

, or

2

. The selected values for the

passive components are R

= 2.5 k1%, R

= 2.21 k1%,

C

1

= 150 pF 10%, R

= 475 1%, R

C

2

= 150 pF 10%. Thus, the resulting coefcients are

1

= 0.133,

1

= 0.151,

2

= 0.702, and

2

= 0.444.

The ADC stability has been veried in the component

tolerance ranges. The converter attributes for the nominal com-

ponent values are SNR

max

= 56.3 dB, SNDR

max

= 54.9 dB,

OL = FS, DR = 60 dB, and G = 0.884.

III. DIGITAL FILTER DESIGN

In order to measure the required current parameters, i.e.,

i

o,peak

, i

o, mean

, and i

o, rms

, output current i

o

has to be ex-

tracted from the ADC output i

bs

. A digital LPF archi-

tecture reconstructs the output current by removing most of the

Fig. 5. Second-order sigmadelta ADC schematic circuit.

Fig. 6. Implementation block diagram for the CIC lter.

quantization noise. In this paper, a cascaded integratorcomb

(CIC) lter has been chosen as a hardware-effective solution

[29], [30]. The difference equation for the rst-order CIC

lter is

m(k) =

1

d

d1

i=0

y(k i). (7)

CIC lters perform a moving average over the last d sam-

ples. To minimize the logic-resource consumption, this lter

has been implemented as shown in Fig. 6. Moreover, the d

parameter has been selected to be a power of two to avoid

the hardware division implementation. According to [31], the

CIC lter order has been selected to be one order more than the

modulator order, i.e., a third-order lter has been chosen.

The LPF removes most of the quantization noise while allow-

ing the desired bandwidth to pass through with low attenuation.

The CIC lter frequency response is a sinc whose rst zero

is placed at f

z

= f

s

/d. Thus, the d parameter sets both, i.e.,

the rst zero position and cutoff frequency f

c

. In this paper,

three lters have been evaluated: a second-order CIC lter with

d = 8, a third-order CIC lter with d = 8, and a cascade of a

second-order CIC lter with d = 8 and a rst-order CIC lter

with d = 16. Fig. 7 shows the frequency response magnitude

for the evaluated lters. The frequency responses show that

the CIC

2

8

+ CIC

16

lter has the higher attenuation at high

frequencies, which entails better quantization noise ltering,

but it also has higher attenuation at the highest frequencies of

the signal bandwidth.

The performance of the proposed lters has been evaluated

through simulation. Fig. 8 shows the current measurement

relative errors

r

for the three lters and the proposed second-

order ADC. The relative error has been dened as

r

= 100

I

meas

I

I

(8)

JIMENEZ et al.: DESIGN AND EVALUATION OF ADC FOR EMBEDDED CONTROL SYSTEMS 2605

Fig. 7. Magnitude of the frequency responses of the evaluated lters.

Fig. 8. Current measurement relative errors for different lters. (a) Error in

positive peak. (b) Error in mean of the absolute value. (c) Error in rms value.

where I is the reference magnitude obtained through a circuital

simulation during T

B

= 10 ms, and I

meas

is the same magni-

tude measured with the proposed system.

Fig. 8(a) shows the error in the current positive peak for

the whole power-converter frequency range of operation. The

peak error for the CIC

3

8

lter reaches 20%, which is insufcient

for the IH application. Thus, the CIC

2

8

+ CIC

16

lter has been

selected to perform this measurement. Fig. 8(b) and (c) shows

the error in mean and rms current values, respectively. In these

measurements, the CIC

2

8

+ CIC

16

lter shows higher error

than the CIC

3

8

lter due to the lter attenuation on the signal

bandwidth. As expected, these errors get worse as the current

Fig. 9. Selected lter architecture.

frequency increases. Thus, the CIC

3

8

lter has been chosen for

the mean of the absolute and rms calculation.

Fig. 9 shows the nal lter architecture and the measure-

ments obtained from each lter. This lter topology has been

optimized to achieve the required accuracy while keeping the

lter to a reasonable size. The measurement block measures

the current parameters during the mains half-cycle from the

reconstructed currents i

r

. The peak value is obtained as the

maximum of the reconstructed signal i

r,CIC

2

8

+CIC

16

. The mean

of the absolute is computed as

i

o, mean

=

1

N

N1

n=0

i

r,CIC

3

8

(n)

(9)

where N is the number of samples taken into account in the

measurement, i.e., the number of samples of a mains half-cycle.

Finally, the current rms value is computed as

i

o, rms

=

1

N

N1

n=0

i

2

r,CIC

3

8

(n). (10)

IV. EXPERIMENTAL VERIFICATION

The experimental verication of the designed second-order

ADC has been carried out in two steps. The rst step

veries the modulator by means of frequency analysis

and the extraction of the modulator parameters. The second

one veries the ADC behavior while working under real

conditions.

Fig. 10 shows the test bench used for the experimental

verication [32]. It is made up of four subsystems: the power

converter, the modulator, the FPGA board, and the user

interface. The power converter features a half-bridge series-

resonant inverter designed for the IH application. The power

converter operates with switching frequencies between 40 and

80 kHz. In addition, this stage implements the output-current

conditioning circuit. The modulator board implements the

proposed second-order modulator. The ADC sampling

frequency is 20 MHz. The digital system has been embedded in

a Xilinx Spartan-6 FPGA included in an ATLYS development

board fromDigilent. Finally, a Matlab-based graphical interface

is using for controlling the modulation parameters of the power

converter and retrieving the system results.

2606 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 5, MAY 2014

Fig. 10. Experimental test bench.

TABLE I

PARAMETERS OF PSD ESTIMATION

A. ADC Analysis

In this analysis, the designed modulator is tested. First,

the noise-shaping capability of the modulator is veried by

means of a frequency analysis. Second, the attributes of the

ADC are obtained by using the IEEE standard sine-wave tting

method. In both analysis, analog input signal x(t) is generated

by a Tektronix AFG3022 sine-wave generator.

The verication of the modulator noise-shaping prop-

erty has been carried out by computing the power spectral

density (PSD) estimation of the modulator output i

bs

. The

PSD has been calculated by using Welchs method P

w

(e

jw

)

[33] with the parameters shown in Table I. Both frequency

and amplitude sweeps of the input sine-wave signal have been

performed to verify the modulator behavior in the whole

operating range.

Fig. 11 shows the simulated and experimental PSD estima-

tions of the second-order modulator output i

bs

for an input

sine-wave signal of amplitude A

sin

= 0.5 V and frequency

f

sin

= 75 kHz.

Following the frequency analysis, the attributes of the ADC

are measured from the SNR and SNDR curves. To obtain these

curves, amplitude sweeps of the input sine-wave signal x(t)

have been performed for the whole ADC DR. In Fig. 12,

simulation and experimental results of the ADC performance

are merged together. Because SNR and SNDR curves are

affected by the noise in the system, Fig. 12 represents the mean

value of 50 measurements per amplitude. The SNR and SNDR

curves show good agreement between simulation and experi-

mental results. The attributes of the implemented second-order

ADC are SNR

max

= 56.5 dB, SNDR

max

= 53.4 dB, and

Fig. 11. PSD estimation of the ADC output i

bs

. Simulation versus experi-

mental results.

Fig. 12. ADC performance characteristics. Simulation versus experi-

mental results.

OL = 0.971. The DR attribute cannot be measured due to sine-

wave generator limitations.

The DR of the ADC allow measuring output current

amplitudes up to 90 A, which covers the normal inverter op-

erating conditions. However, the output current amplitude may

be higher than this value due to abnormal operating conditions

such as short circuit or vessel removal. An output current

amplitude higher than 90 A deteriorates the modulator

behavior or may even cause modulator instability. In spite

of the fact that the modulator does not work properly, the

peak current measurement is able to detect that the maximum

current value has been reached. This overcurrent detection is

enough for the high-level control algorithm to execute the

corresponding security measures.

B. Complete System Verication

The complete system verication has been performed while

under real operating conditions. Fig. 13 shows the power deliv-

ered to the vessel versus switching frequency for the induction

load detailed in Table II. The values of the equivalent resis-

tance R

eq

and inductance L

eq

depend on the resonant inverter

operating point. Hence, these values have been specied at

the resonant frequency f

o

. The efciency of the half-bridge

resonant inverter depends on its operating point. Typically, the

inverter efciency is in the range of 89%97% [34]. IH load

characteristics in conjunction with the power levels available in

domestic induction appliances entail output current values of

up to 90 A. To adapt these current levels to the ADC

DR (03.3 V), a current transformer with CTR = 200, and a

burden resistor of R

T

= 3.65 have been selected.

JIMENEZ et al.: DESIGN AND EVALUATION OF ADC FOR EMBEDDED CONTROL SYSTEMS 2607

Fig. 13. Output power versus switching frequency in the whole operating

range.

TABLE II

INDUCTION LOAD PARAMETERS

In Fig. 14, the error in current measurements for the lters

included in the digital control system in the whole range of

operation is shown. Fig. 14(a) shows the error in the positive

inductor current peak, Fig. 14(b) shows the error in the cur-

rent mean of absolute, and Fig. 14(c) shows the error in the

rms measurement. The experimental values used for the error

calculations at each frequency are the mean of 50 independent

measurements. The experimental values have been compared

with the measurements of a Tektronix TCP0030 current probe

and a Tektronix DPO7354 oscilloscope congured to work with

high resolution (> 11 bits), a sampling rate of 20 megasamples

per second (MSPS), and calculation time of 10 ms. As expected,

the best results are obtained when using the (CIC

8

)

2

+ CIC

16

lter for the peak measurement, and the (CIC

8

)

3

lter for the

mean of the absolute and the rms measurements. Then, the lter

architecture presented in Fig. 9 is selected to be implemented in

the nal measurement system.

The experimental output voltage and current at the limits of

the switching frequency range for the load detailed in Table II

are shown in Fig. 15. Fig. 15(a) shows the output voltage and

output current at the peak of the mains cycle when the inverter

works with a switching frequency of f

sw

= 40 kHz, i.e., close

to resonance. Fig. 15(b) shows the same waveforms when the

inverter works with a switching frequency of f

sw

= 40 kHz.

Close to resonance, the output current waveform has a sinusoid-

like shape and high amplitude. However, as the switching

frequency increases, the waveform shape gets a triangular form

and the amplitude decreases.

Finally, Fig. 16 shows the experimental time-domain wave-

forms of the output current when the inverter works with a

switching frequency of f

sw

= 40 kHz. The results show good

accuracy in the reconstruction of the output power.

V. SYSTEM CALIBRATION

The inductor current measurements are affected by several

error sources in addition to the error caused by the algo-

Fig. 14. Error in current measurements for different lters. (a) Error in

positive peak value. (b) Error in the mean of the absolute value. (c) Error in

rms value.

rithms. Among these error sources are the accuracy of the

current sensor, the tolerance of the passive components, and the

nonidealities of the analog parts. For these reasons, the nal

measurement system has to be calibrated [35]. This calibration

process assesses the quality of the proposed system measure-

ments by using the measurements performed with a working

measurement standard, which is a measurement standard used

to calibrate instruments. In this paper, the working measure-

ment standard is a Tektronix TCP0030 current probe and a

Tektronix DPO7354 oscilloscope congured to work with high-

resolution, a sampling rate of 20 MSPS, and calculation time of

10 ms.

The measurement systems denote the accuracy of the system

by means of the uncertainty u. In metrology, the uncertainty of

a measurement is the margin of error that limits the range of

values that likely encloses the true value i. For that reason, the

measurement result is given as

i =L u

L =i

m

i (11)

where i

m

is the value calculated by the measurement system,

and i is the bias of the measurement system. The uncertainty

2608 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 5, MAY 2014

Fig. 15. Experimental output voltage v

o

(50 V/div) and output current i

o

(15 A/div) waveforms. (a) Experimental results at switching frequency f

sw

=

40 kHz. (b) Experimental results at switching frequency f

sw

= 80 kHz. The

time is 5 s/div.

Fig. 16. Experimental time-domain waveforms of the output current. From

top to bottom: output current, 1-bit data stream ADC output, recon-

structed current with lter CIC

2

8

, reconstructed current with lter CIC

3

8

, and

reconstructed current with lter CIC

2

8

+ CIC

16

.

can be specied by multiplying the standard deviation of the

measurement system s

y

by a factor k, i.e.,

u = ks

y

. (12)

A. Calibration at Each Calibration Point

The rst step in the calibration process is to obtain the

bias and the uncertainty of the measurement system in each

Fig. 17. Bias in current measurements. (a) Values of the measurements

performed with the working measurement standard. (b) Bias in the positive

peak. (c) Bias in the mean of the absolute and rms values.

operation point. In order to perform this task, in this paper,

n

c

= 50 measurements have been captured at each calibration

point j. Then, the bias at each calibration point j, i.e., i

cj

, is

calculated as

i

cj

= i

cj

i

oj

(13)

where

i

cj

is the mean value of the measurements at the cali-

bration point j, and i

oj

is the working standard measurement.

Fig. 17(a) shows the value of the measurements obtained

with the working measurement standard at the calibration

points considered in the calibration process. Fig. 17(b) and (c)

shows the bias values at each calibration point for the three

measurements.

The uncertainty of each calibration point is obtained through

the variance calculation. In order to obtain the variance of

the measurements at each calibration point, the propagation of

uncertainty rule is applied to the error effects in the calibration

chain as follows:

s

2

j

= s

2

oj

+s

2

cj

+s

2

mj

(14)

where s

2

j

is the variance of the measurement at the calibration

point j, s

2

oj

is the variance of the working standard measurement,

JIMENEZ et al.: DESIGN AND EVALUATION OF ADC FOR EMBEDDED CONTROL SYSTEMS 2609

Fig. 18. Uncertainty in current measurements for the selected lter

architecture.

s

2

cj

is the estimated value of the variance of the measures used

in the calibration process, and s

2

mj

is the estimated value of

the variance of the measurement sample working under real

conditions. The variance at each calibration point leads to

s

2

j

= s

2

oj

+

s

2

icj

n

c

+

s

2

icj

n

(15)

where s

icj

is the standard deviation of the measurements used

in the calibration process at the calibration point j, and n is

the number of samples used for each current measurement at

real working conditions, which is in the implemented system

n = 1. Fig. 18 shows the uncertainties of the measurements at

each calibration point u

cj

setting k = 2 in order to obtain an

interval of condence of 95%, considering the uncertainty of

the working standard 1% with an interval of condence of 99%.

B. Calibration in the Whole Measurement Range

In the second step in the calibration process, a unique value of

uncertainty is given for the whole operating range that considers

the variance and the bias. For calculating the global uncertainty,

rst, the uncertainty of each point of calibration is obtained with

an interval of condence of 95% (k = 2). Considering (10) and

(13), and including the bias in the error chain, the uncertainty

can be calculated using

u

j

=

0.44u

2

oj

+k

2

s

2

icj

1

n

c

+

1

n

+ i

2

cj

(16)

where u

i

is the uncertainty of the calibration point j, and u

oj

is the working standard uncertainty in the calibration point

j. Finally, the uncertainty of the measurement system is the

maximum of the obtained uncertainties; thus, u = max(u

j

).

The global uncertainties of the measurements performed

with the proposed measurement system (second-order

ADC) are presented in Table III, together with the uncertainties

obtained with a measurement system that performs a rst-order

ADC. These results show that the proposed measurement

system offers better accuracy in the measurements while keep-

ing low-cost implementation. The uncertainty is a conservative

value that indicates the maximum absolute error in the whole

operating range with an interval of condence of 95%. In

addition to this, the experimental results show that the proposed

system achieves accuracy better than 9% for the peak current

and better than 1% for the mean and rms values.

TABLE III

GLOBAL UNCERTAINTY

VI. CONCLUSION

In this paper, a low-cost solution for measuring the main

required current parameters of a resonant power converter

applied to IH has been presented. The proposed system consists

of a second-order single-bit ADC and a digital lter

architecture. Ageneral design procedure for designing the ADC

has been explained, and an optimized lter architecture has

been proposed to improve the accuracy and hardware resources.

The proposed architecture has been experimentally tested

with an induction-heating resonant converter. A calibration

process has been performed in order to assess the quality of the

measurement system. This calibration process shows that the

measurement system achieves accuracy better than 9% in peak

current measurement and 1% in mean of the absolute and rms

measurements. The achieved accuracy is good enough to both

perform proper output power control and to ensure the safety of

the converter.

In addition, the proposed architecture can be easily extended

to any other power converter. This paper considers the output

current DR from 90 to 90 A when operating under nor-

mal conditions. However, the measurement system DR can

be adapted to the specic application by selecting the current

transformer turns ratio CTR value and/or the burden resistor

R

T

value.

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Oscar Jimenez (S10) received the M.Sc. degree

in telecommunication engineering from the Univer-

sity of Zaragoza, Zaragoza, Spain, in 2009. He is

currently working toward the Ph.D. degree in the

Department of Electronic Engineering and Commu-

nications, University of Zaragoza.

His current research interests include domestic

induction heating, resonant inverters, and digital con-

trol applied to power converters.

Mr. Jimenez is a member of the Aragon Institute

for Engineering Research.

Oscar Lucia (SM04M11) received the M.Sc. and

Ph.D. degrees in electrical engineering from the Uni-

versity of Zaragoza, Zaragoza, Spain, in 2006 and

2010, respectively.

He has been with the Department of Electronic

Engineering and Communications, University of

Zaragoza, where he is currently an Assistant Profes-

sor. His main research interests include multiple out-

put converters, digital control, and resonant power

conversion for induction heating applications.

Dr. Lucia is a member of the Aragon Institute for

Engineering Research.

Isidro Urriza received the M.Sc. and Ph.D. de-

grees in electrical engineering from the University

of Zaragoza, Zaragoza, Spain, in 1991 and 1998,

respectively.

He is currently an Associate Professor with the

Department of Electronic Engineering and Commu-

nications, University of Zaragoza. He has been in-

volved in various research and development projects.

His main research interests include digital im-

plementation of modulation techniques for power

converters.

Dr. Urriza is a member of the Aragon Institute for Engineering Research.

JIMENEZ et al.: DESIGN AND EVALUATION OF ADC FOR EMBEDDED CONTROL SYSTEMS 2611

Luis A. Barragan received the M.Sc. and Ph.D.

degrees in physics from the University of Zaragoza,

Zaragoza, Spain, in 1988 and 1993, respectively.

He is currently an Associate Professor with the

Department of Electronic Engineering and Commu-

nications, University of Zaragoza. He has been in-

volved in various research and development projects

on induction heating systems for home appliances.

His research interests include digital circuit design

and digital control of inverters for induction heating

applications.

Dr. Barragan is a member of the Aragon Institute for Engineering Research.

Denis Navarro received the M.Sc. degree in mi-

croelectronics from the University of Montpellier,

Montpellier, France, in 1987 and the Ph.D. degree

from the University of Zaragoza, Zaragoza, Spain,

in 1992.

Since September 1988, he has been with the

Department of Electronic Engineering and Commu-

nications, University of Zaragoza, where he is cur-

rently an Associate Professor. In 1993, he designed

the rst SPARC microprocessor in Europe. He is

involved in the implementation of new applications

of integrated circuits. His current research interests include computer-aided de-

sign for very large scale integration, low-power application-specic integrated

circuit design, and modulation techniques for power converters.

Dr. Navarro is a member of the Aragon Institute for Engineering Research.

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