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A Phase Locked Loop (PLL) is a system that locks the phase or frequency to an input
reference signal. Phase Locked Loops are used in almost every communication
system. Some of its uses include recovering clock from digital data signals,
performing frequency, phase modulation and demodulation, recovering the carrier
from satellite transmission signals and as a frequency synthesizer.
Wireless communications has undergone an incredible amount of development over
the past several years. It has revolutionized the way we live today. Traditional cable
communication is becoming obsolete in various applications. A mobile phone or a
cellular telephone is the most popular among the wireless gadgets. But the wireless
revolution is not confined to this single device. Wireless connectivity is exploring
new horizons every day- for instance, nowadays a car can be considered as a large
mobile communication device. Surveys predict the number wireless gadgets could
exceed the global population within a couple of years. This large demand is
motivating manufactures to provide increasingly competitive devices in terms of
functionality, price, size and battery life. The battery life of a device is of particular
importance since a consumer wishes to have a device that can operate for extended
periods of time without the need of recharging the battery.
From the circuit designers point of view, the price could be decreased by using low-
cost technologies, such as an advanced CMOS process, size could be reduced by
minimizing the number of off-chip components, thus high levels of integration, and
battery life could be extended by decreasing the overall power consumption of the
A frequency synthesizer being an important building block in a wireless transceiver,
is responsible for translating the desired radio-frequency (RF) band signal down to
baseband in the receive path, and from baseband to RF in the transmit path. In most

wireless transceivers, the frequency synthesizer is also responsible for selecting the
desired channel of interest. Given the fact that the desired channel lies at a high
frequency and is usually surrounded by much stronger and very close adjacent
channels (200 kHz for GSM), it is no surprise that the frequency synthesizer has to
meet very stringent requirements.
Not only is the frequency synthesizer a critical part of the wireless radio, but almost
all the performance criteria of the PLL affects the radio. Phase-noise, which is most
often determined by the voltage-controlled oscillator (VCO) of the PLL, is a
significant contributor to noise in transceivers. It also contributes to the spurious
emission of the transmitter and is thus subject to governmental regulations. Finally, it
is also one of the main power hungry circuits of the radio. Thus improving the
performance of the frequency synthesizer can have a large impact on the overall
performance of any transmitter, receiver, or transceiver design.
The design of a PLL synthesizer demands a solid understanding of various sub-
disciplines of electronics engineering such as control systems, signals, analog design,
digital circuits etc. Therefore the design of a PLL synthesizer is a challenging research
1.3.1 Wireless Transceiver Basics
The objective of an RF transceiver is to transmit and receive data. The transmitter
processes the base band data signals and feed it to the antenna in a frequency suitable
for transmission. Similarly the receiver senses the signal picked up by the antenna and
processes it so as to reconstruct the original information. Figure 1.1 shows a generic
RF transceiver. Each block has its own function. The prime requirements of the
transceiver are; the signal fed to the antenna must be powerful enough to reach far
distances and the receiver must sense a small signal and amplify it with low noise for
further processing.


Fig. 1.1 Generic RF Transceiver [5]

The base band signal to be transmitted is first processed digitally using digital
baseband processors and then is converted into an analog mode which is suitable for
wireless transmission. This analog signal is up-converted to a much higher frequency
with the help of mixer stages. The number of these mixer stages can vary from only
one stage to many of them based on the architecture of the transceiver. A homodyne
or direct conversion transceiver uses only one stage of up/down converter. In
heterodyne transceivers, two such stages are used. In super heterodyne transceivers,
more than two up/down conversion mixer stages are used. This has an inherent
advantage of better system performance at the cost of higher system complexity.
Homodyne transceivers suffer from problems such as creation of unwanted image
frequencies[5]. A duplexer precedes the antenna which is used to isolate transmit and
receive signal paths to avoid the possible interference of transmitted and received
signals. The signal up-converted to radio frequency levels are amplified in power
level with power amplifiers which provides sufficient signal power for transmission.
The signal picked up by the antenna from air is given to a LNA (Low Noise
Amplifier) whose function is to amplify the signal with minimum addition of extra
noise. This amplified signal is down converted using one or more mixer stages
depending on the receiver architecture. Baseband signal is converted to digital format
for the processing in digital processors.


1.3.2 Role of Synthesizer in Wireless Transceiver
Frequency synthesizers are an essential part of nearly all multi-frequency wireless
transceivers. Phase-Locked Loop (PLL) based frequency synthesizers are most
frequently used as local oscillators (LOs) in wireless receivers to down-convert the
carrier frequency to a lower, intermediate frequency. Sometimes, PLLs are also used
to perform frequency or phase modulation and demodulation, clock recovery, jitter
suppression in communication, frequency synthesis, skew suppression, edge
detection, etc.
The role of a frequency synthesizer is to provide the reference frequency for
frequency translation. Fig. 1.1 shows the typical block diagram of a cellular phone RF
section. An RF synthesizer and an IF synthesizer in heterodyne transceiver are used
for the frequency translation. RF synthesizer alone is used in homodyne.
As shown in Fig. 2.2, an ideal frequency synthesizer generates a single frequency
tone. In the receiver case, it mixes with the received RF signal spectrum and shifts it
down to baseband. In the transmitter case, it mixes with the modulated baseband
signal and shifts it up to RF. In both cases, the output spectrum is the convolution
result of the synthesizer tone with the received signal spectrum or the modulated
baseband signal spectrum

Fig.1.2 Role of Frequency Synthesizer

Any noise in the circuit or environment will create phase disturbance. In Fig. 1.3, a
non-ideal frequency synthesizer spectrum is shown. It is no longer a single frequency
tone but rather a smeared version. The energy under the skirt is phase noise.
Sometimes the energy is concentrated at frequencies other than the desired frequency,
appearing as a spike above the skirt. This energy is due to a spurious tone. Phase noise
and spurious tones are the two key performance parameters of a frequency

Fig.1.3 Effect of Phase Noise on Local Oscillator Signal [8]
In a receiver, the spurious tones and phase noise of the frequency synthesizer can mix
with the undesired signal and produce noise in the desired channel. This reduces the
sensitivity and selectivity of a receiver.[8]
Similarly, in a transmitter, the spurious tones and the phase noise of the frequency
synthesizer can mix with the modulated baseband signal and produce undesired
spectral emissions, increase adjacent channel interference, and reduce the modulation

Fig.1.4 Effect of Spurious Frequencies on Local Oscillator Signal [8]
1.3.3 Synthesizer Alternatives
There are different alternatives available for the implementation of Synthesizer. The
most popular among them are Phase Locked Loop (PLL), Delay Locked Loop (DLL)
and Direct Digital Frequency Synthesis (DDFS).
DLL is same as a PLL except the fact that VCO is replaced by a voltage controlled
delay line. The advantage of the DLL based frequency synthesizer is that the jitter
does not accumulate from cycle to cycle as in the ring oscillator and thus lower phase
noise at close-in frequencies can be achieved.
The major disadvantage of the DLL approach is that the output frequency is fixed by
the number of delay stages in the delay line. Hence it is not suitable in applications
where frequency tuning is required. The design which is discussed in this thesis is
based on Phase Locked Loop (PLL).
This thesis is organized in 5 chapters. Followed by introduction, Chapter 2 presents
the various blocks in a PLL synthesizer. The implementation details of various blocks
are discussed in Chapter 3. Chapter 4 presents a novel low phase noise ring VCO.
Simulation results are included in Chapter 5 followed by conclusions.

The basic phase-locked loop circuit synchronizes an output signal with an input
reference signal. The output signal has the same frequency as the input reference
signal and also a constant phase difference. A block diagram of a simple phase-locked
loop is given in Figure 2.1

Fig. 2.1 Basic PLL block diagram
The phase-locked loop works by comparing the reference signal,

with the voltage

controlled oscillators (VCO) output,

An error signal,

is produced that is
proportional to the phase difference of the reference signal and the output signal. This
error signal is filtered to generate the voltage controlled oscillator control voltage,

The loop is setup in a negative feedback fashion so the voltage controlled oscillator
control voltage will force the output of the voltage controlled oscillator to lock with
the input reference signal within certain frequency limits.
Advances in integrated circuit technology allowed phase-locked loop circuits to be
used commonly in many areas such as communications, wireless systems, consumer
electronics, and motor control.


The PLL can be used as a frequency synthesizer by placing a loop divider in the
feedback path as shown in Figure 2.2. By adding a frequency divider in the feedback
path, output frequency is made N times that of the reference frequency.

FIG.2.2 Frequency Synthesizer using PLL
Here the output frequency

is related to the input reference frequency

by the
following equation:


is the center frequency and

is the VCO conversion gain. Adjusting the

division factor or modulus can change the frequency that the PLL synthesizes.
Although a PLL is normally a non-linear device because of phase and frequency
detector (PFD), divider, and prescaler, it can be accurately analyzed using a linear
device model when the loop is in a locked status.

Fig 2.3 A Single Loop Feedback Control System

A basic linear feedback control system is shown in Figure 2.3. This control system
model will be used to derive and analyze the transfer functions of a PLL. In this
system model, the closed-loop transfer function is given as a function of feed-forward
gain, G(s), and feedback gain, H(s), like G(s) / (1 + G(s) H(s)), where s is a complex
frequency. Another important feature of the system model is the steady-state error
transfer function 1 / (1 + G(s) H(s)), which indicates the remaining error after all
transients have died out.
If the system loop bandwidth is less than 20 times the reference input frequency and
the system is in a locked status, then the digital PLL which consists of a divider with
modulus N, a PFD with gain K
(V/rad), a LPF with transfer function F(s), and a
VCO with gain K
(rad/Vs) can also be analyzed using a continuous single-loop
feedback control system model.

Fig 2.4 Small signal block diagram of the PLL
The small-signal block diagram of the simple digital PLL where input signal with a
frequency of f
and a phase
is applied is shown in Figure 8. In this figure, the
closed-loop transfer function can be given by



The steady-state error transfer function can also be given by

2.3.1 Phase Frequency Detector
The phase detector is a digital phase/frequency detector (PFD) with a charge pump
output stage. The digital phase/frequency detector consists of two D Flip-Flops and an
AND gate. A schematic of the phase/frequency detector is shown in Figure 2.5. The
phase/frequency detector produces two output signals, UP and DOWN, that are
dependent on the phase and frequency relationship of the two inputs,


The UP and DOWN outputs control the charge pump which acts as the phase
frequency detectors output stage. The charge pump outputs a current into the loop
filter to generate the control signal of the VCO.

Fig 2.5 PFD Schematic
The UP output signal of the PFD goes high on the rising edge of

. The DOWN
output signal goes high on the rising edge of

. The UP and DOWN signals remain

high until they are reset by the AND combination of UP and DOWN. In other words,
the reset signal is produced when both


clock inputs are high. Both Q

outputs will be essentially low when both signals are in phase and of the same
frequency. An example is shown in Figure 2.6.


Fig 2.6 PFD Sample Waveforms

2.3.2 Charge Pump
Figure 2.7 shows the charge pump output stage of the phase/frequency detector. It
supplies current to the loop filter to produce the VCO control voltage.

Fig.2.7 Charge Pump Schematic
The UP signal is high when the reference signal is operating at a higher frequency
than the feedback signal. The charge pump forces current into the loop filter when the
UP signal is high. This causes the VCO control voltage to rise. This increases the
VCO frequency and brings the feedback signal to the same frequency as the reference
signal. The DOWN signal is high when the reference signal is operating at a lower
frequency then the feedback signal. The charge pump forces current out of the loop
filter when the DOWN signal is high. This causes the VCO control voltage to fall.
This decreases the VCO frequency and brings the feedback signal to the same
frequency as the reference signal.


The signals from the PFD, UP and DOWN, are used to control the charge-pump
circuit. The purpose of the charge-pump circuit is to change the VCO control voltage
by applying positive or negative charges to the low-pass filter. The electric current
magnitude of the charge-pump PLL is an important factor in the overall loop behavior
because it determines the transfer function of the charge-pump circuit that is given by

where I
(s) = the Laplace transform of the average current over a cycle
= the pump current

(s) is the Laplace transform of the phase difference at the PFD input
2.3.3 Loop Filter
The advantage of an active filter over its passive counterpart like a lag RC filter or a
passive lag-lead low pass filter comes from the presence of a very high DC gain
amplifier, which allows a nearly ideal integration in the loop filter. A filter with a pole
at its origin helps to reduce the static phase error to a very small, residual value. Using
an active filter, the static phase error of a PLL can be reduced. However, an
operational amplifier in the loop filter produces a significant amount of noise power
within the PLL bandwidth. Therefore, the noise power contributes to the offset, which
in turn causes unwanted sidebands in the output signal[4].
A simple way to achieve the same performance result as the active filter with a pole at
its origin without using the noisy, offset-susceptible active operational amplifier is to
use a charge-pump circuit. When compared with the PLLs without a charge-pump, the
charge-pump PLL offers two important advantages in addition to reducing static
phase error. First, the capture range of a charge-pump PLL is only limited by the
VCO output frequency range. Second, the static phase error is zero if mismatches and
offsets of charge-pump are negligible

Fig.2.8 Passive Loop Filter
As shown in Figure 2.8, a simple, second-order passive low-pass filter is composed of
a resistor, R and two capacitors, C and C
The transfer function of this filter is given by


Then, the closed-loop transfer function is found to be

And the open-loop transfer function is

According to the definition of type and order, this is a type two, third-order PLL
system. In this system, the pole created by capacitor C
that is needed to suppress the
control voltage ripple coming from the resistor connected in a series must be lower

than the reference input frequency in order to attenuate the spurs. But the pole must
also be higher than the loop bandwidth; otherwise, the loop will become unstable.
The equation (2.8) can be approximated by a second-order expression to derive
outcomes that give an intuitive feel of the transient response. The higher order terms
are assumed to be small relative to the lower order terms. The simplified second order
expression is given by

The loop filter is the critical building block that determines the loop dynamics. In a
charge pump PLL, the natural frequency and the damping factor is set independently
by the values of the components used in the loop filter. The capacitor

sets the
natural frequency. The resistor sets the damping factor[7].

2.3.4 Voltage Controlled Oscillator
The voltage-controlled oscillator generates an output signal with a frequency that is
dependent on the input control voltage by the following equation

It has a center frequency of

. The slope of the transfer characteristic in the linear

region is equal to the VCO conversion gain

There are several different types of VCOs. Some VCO architectures include RC, LC,
crystal, relaxation, and ring oscillators. The oscillators most commonly used in
integrated PLL design are the LC tuned and the ring oscillators.
The LC oscillator is shown in Figure 2.9. This circuit is generally preferred in high
performance frequency synthesizers because of its superior phase noise performance.

Fig.2.9 LC Voltage-controlled Oscillator
A ring oscillator is shown in Figure 2.10. This circuit consists of an odd number of
inverting amplifiers placed in a feedback loop.

Fig.2.10 A Single Ended Ring VCO
The frequency of oscillation is determined by the equation


is the delay of individual delay stage.

The integrated ring voltage-controlled oscillators typically have the advantages of
simple design, wider tuning range and lower power consumption than the LC

oscillators. However, these advantages come at the price of poorer phase noise
performance when compared to LC oscillators. In this work a low phase noise ring
VCO using a novel delay cell structure is introduced.
2.3.5 Loop Divider
The loop divider divides the VCO output frequency to produce the VCO feedback
signal. The loop division factor determines the output frequency relation with the
input reference frequency. The loop divider can be realized in many different ways
depending on the type of synthesizer architecture used. The most common circuits
used in the loop divider are prescaler circuits, dual-modulus prescalers, and counters.
These are implemented using flip-flops where each D flip-flop's inverted output is
connected back to its input, making it a divide by two circuit. If the input is fed into
the clock signal of this circuit the output frequency will be half of the input frequency.
A circuit configuration of such a circuit and its input output behavior is shown in
Figure 2.11.

Fig.2.11 Divide by 2 Circuit using D Flip-Flop[5]
Further, by adding logic gates and D flip-flops, dividers with different moduli can be
implemented including multi-modulus dividers.
2.3.6 Programmable Dividers
Other than dividers which have a fixed divide ratio, programmable dividers are there
in which the divide ratio can be programmed according to the programing bits.


The PLL is a complex system to design. Performance and stability considerations
must be accounted for in the design procedure. The entire design procedure for a fully
integrated PLL is generally an iterative process. Typically design parameters are
adjusted from the mathematical model to the system level model to the transistor level
design. The following design procedure describes how to define the system level
parameters for a fully integrated charge pump PLL.
The following system level parameters need to be defined.
1. Charge Pump Current

2. Loop Filter Components

3. VCO Tuning Range
4. VCO Gain

5. Loop Division Factor N
Step 1: Determine VCO Tuning Range
The maximum and minimum output frequencies determine the PLL frequency of
operation. This is the frequency at which the PLL is operating. The frequency at
which PLL operates is 1.8 GHz. This requires that the VCO have a tuning range at
least 1.2 GHz to 2.2 GHz.
Step 2: Determine Loop Division Ratio Range.
The loop division ratio is the modulus, N at which the divider is operating. This is
largely determined by the synthesizers input and output frequencies. Here the input
frequency is decided as 225 MHz. If it is assumed that a 225 MHz reference is used to
produce a 1.8GHz signal at the output, N will have the following value.

The value of N has an effect on other loop parameters. Therefore, in defining the other
parameters the value of N will be used.

Step 3: Determine Damping Factor,

The damping factor

has an effect on the speed and stability of the system. As a

compromise between speed and stability,

is optimally set to the following


Step 4 Determine Natural Frequency,

The natural frequency has a significant effect on the loop bandwidth. For a charge
PLL with a passive loop filter, the loop bandwidth,

, is related to the natural

frequency by the following

If 0.707 is assumed, this results in the following

It is desirable to make the loop bandwidth less than 1/10 of the input reference
frequency (225 kHz) in order to avoid the continuous time approximations of the
charge pump PLL breaking down. However, it is desirable to make the loop
bandwidth as wide as possible in order to suppress the VCO phase noise that is the
dominant source of phase noise for the integrated PLLs. As a compromise between
stability and noise performance, the loop bandwidth is set to the following

This results in the natural frequency equal to

Step 5: Determine VCO Gain

The tuning range of the VCO and the VCO control voltage range set the VCO gain.
From step 1 it was shown that the VCO needs to tune a minimum frequency range of
1.3 to 2.3 GHz. The VCO control voltage range is limited by the power supply and
the voltage levels necessary to keep the charge pump in saturation. The charge pump
will no longer behave ideally if the VCO control voltage rises too high or falls too
Therefore, the VCO control voltage is limited to a minimum of a

from the
supply rails. With a power supply of 1.8V, a VCO control range of 1V can be
assumed with sufficient margin to handle process variations. This results in the
following VCO gain.

Step 6: Determine Charge Pump and Loop Filter Capacitor
The charge pump current is set so that a decent loop gain is obtained without
producing too large of a capacitor as shown in the following.


Now all of the system level loop design parameters have been computed. Table 3.1
summarizes the system level parameters.


Table 3.1 PLL Specifications
Loop Bandwidth 58.8 Mrad/s
Damping Factor 0.707
Natural Frequency 28.56 Mrad/sec
VCO Tuning Range 1.3 2.3 GHz
VCO Conversion Gain 5.8Grad/s
Loop Division Ratio 8
Charge Pump Current 25A
Primary Loop Filter Capacitance 2.66pF
Loop Filter Resistance 4k
Primary Loop Filter Capacitance 0.2pF

This design procedure has defined all the key system level parameters required to start
the design. The next step in the circuit design is to construct a system level
macromodel which allows simulation of the loop dynamics. Then transistor level
design is started. The design process is generally an iterative process. For example,
non-idealities introduced by the transistors can be compensated by adjusting
parameters in the system level macromodel and then translating those adjustments
back to the transistor level. There are usually many design iterations involved in such
a complex system level design as a PLL.
3.2.1 Phase Frequency Detector
Phase frequency detector produces UP and DOWN pulses corresponding to the phase
lagging/leading of the output frequency with respect to the reference frequency. A
gate level implementation of phase frequency detector is shown in figure 3.1. Each
gate is designed using static CMOS logic. The gate transistors are sized according to
provide adequate drive strength for the gates. The drive strength of each gate is
determined using the method of logical effort.


Fig.3.1 Gate Level Schematic of Phase Frequency Detector [9]
To eliminate dead zone, a reset path delay is added to the PFD. UP and DOWN have
the coincident pulses while the PFD has zero phase difference. Furthermore, a
complementary pass gate is interposed between UP/DOWN and the CP to match the
delay between UP, DOWN and their complementary signals.
3.2.2 Charge Pump
The charge pump designed in this system is shown in Figure 3.2. The circuit consists
of a PMOS current mirror (M5 and M6) to mirror

into the charge pump. This

current either goes into the loop filter or into the ground node depending on the
position of the two PMOS switches (M1 and M2). An NMOS current mirror (M7 and
M8) is used to mirror

into the charge pump. This

current either
discharges the loop filter or pulls current from the ground node depending on the
position of the two NMOS switches (M3 and M4).


are both set equal to insure a constant phase detector gain. These
currents are set to the following value.

= 25mA
The transistors in charge pump are sized in order to match


and also to
drop minimum voltage across each transistor switch when in is on.

Fig 3.2 Charge Pump Transistor Level Schematic [7]

3.2.3 Loop Filter
The loop filter is fully integrated on chip. The key issue here is the silicon area
associated with the filter components. Better performance requires loop filters to be
active ones with op-amps. This comes with a trade-off of higher complexity and area.
Therefore a passive loop filter is preferred in this design whose schematic is as shown
below. Input to the loop filter is the charge pump current and its output is the VCO
control voltage

. Values of loop filter components are found as shown in section 3.1

They are
R1 = 2.66pF
C1 = 4k
C = 0.2pF

Fig 3.3 Loop Filter
3.2.4 Voltage Controlled Oscillator
Voltage Controlled Oscillator is implemented as nine-stage differential ring VCO.
This delay imparted by each delay cell stage is a function of

, the control voltage of

the VCO. [3]
Delay cell transistors are sized so as to provide a delay ranging from 27ps to 55ps. So
that the frequency of oscillation is approximately

The schematic of a generic dual delay path N-stage differential ring oscillator is
shown below in figure 3.4.

Fig. 3.4 Schematic of N-stage ring VCO [18]

Buffers are provided to drive larger loads.
The details of low phase-noise ring VCO implementation are discussed in next
3.2.5 Loop Divider
The schematic of loop divider used in PLL synthesizer is shown in fig.3.5.
It provides a division ratio of 8

Fig 3.5 Divide by 8 Circuit
All the flip-flops are designed using dynamic TSPC logic. The transistor level
schematic of a dynamic TSPC flip-flop is given in figure 3.8. [11][7]

Fig.3.6 Dynamic TSPC Flip-Flop


Figure 3.7 Dynamic Divide by 2 D Flip-Flop
The dynamic flip-flop used as a divide-by-2 can be looked at as the circuit shown in
Figure 3.9. It is basically three clocked inverters cascaded with an output inverter. The
first inverter operates when the clock is low, while the second and third inverters
operate when the clock is high. The staggering of clock control signals thus produced
causes the output frequency to be half of the clock frequency. The first flip-flop to
which the VCO output is directly given has to be designed more carefully. It has to
work faster than the other two.


Phase noise is the random variation in phase of the output of an oscillator. It is
measured as the ratio of output signal power to noise power at an offset ranging from
a few kilohertz to megahertz offset from the signal frequency and is expressed in
dBc/Hz. It is a significant source of noise in an oscillator.
Due to high common mode rejection, differential VCO performs better in terms of
substrate and supply noise [19]. Apart from this there are several factors which can be
used to improve the noise performance of an oscillator. Since phase noise is a
measure of signal to noise ratio (SNR) large signal swing can be used to ensure low
phase noise. Devices which are turned completely off do not contribute to phase
noise. This is another factor which favors large signal swing. Timing jitters introduced
by phase noise can be minimized by having sharp transition edges. Also the periodic
on-off switching of the devices ensures a reduced flicker noise [19].
Analog gain stages are not preferred for applications in which low phase noise is
critical. Analog gain stages consist of transistors biased into continuous conduction
which contribute to the overall noise. Periodic switching on and off of gain transistors
can be done to overcome this problem [16] [19].
In single-ended ring oscillators, most of the devices experience complete switching
between on and off states; hence the simplified linear model for phase noise does not
apply. The large signal swing and the sharp transition improve the noise performance
for the following reasons:
Large signal swing implies large signal power and results in a large signal-to-
noise ratio (SNR).
The devices do not contribute additional noise when they are turned off.
The short transition time results in a short period when the oscillator is
sensitive to noise.

The sharp transition edge results in less timing jitter caused by noise.
Device flicker noise is reduced by the periodic on-off switching of the devices

Despite the above benefits, it is a commonly held belief that single ended circuits
suffer from power supply and substrate noise injection when the oscillator is
implemented on the same silicon substrate with digital circuits. As a result, fully
differential oscillators have been widely used where low phase noise performance is
critical. However, even with a fully differential implementation, the circuit is still
subject to power supply and substrate noise.
The most important parameters of a VCO are its phase noise and power consumption.
One can be enhanced by compromising the other. Therefore to compare these results
with other works, a widely used figure of merit (FoM) for evaluating the VCO
performance is used. It is defined as

Where is the phase noise at an offset of from the center frequency

is the power consumed by the circuit while operating at the frequency


The frequency of oscillation in a ring VCO is determined by the propagation delay of
the delay cell as well as the number of delay stages as shown in equation (4.2)

Where N is the total number of stages and

is the propagation delay of each stage.

According to equation (4.2) the frequency of oscillation can be increased by
decreasing the number of stages and decreasing the delay through single stage.

Singe loop oscillators have limitations in frequency range and noise performance.
Multiple-pass loop architecture for an N-stage ring oscillator is shown in Fig. 3.4.
This is the architecture chosen for this work. In this type of architecture there are
auxiliary feed forward loops apart from the main loop. These loops are connected to
the secondary inputs S+ and S- of each delay-cell stage. This effectively reduces the
delay that can be achieved using a single delay cell stage. In multi pass loop technique
a set of secondary inputs are added to each stage of delay cell. The switching of these
secondary inputs takes place earlier than the primary inputs. Thus the delay is
reduced. Switching time of PMOS is shortened. Transition is made sharper.
According to the discussion in the previous section, this reduces the overall phase
Secondary inputs S+, S- receive skewed delay signals earlier than the primary inputs.
This helps to reduce the PMOS switching time. The differential output of every stage
is connected to the primary input of the next stage as well as the secondary input of
the next second stage. Thus the delay time through a stage can be shortened by
switching the secondary input earlier then the primary input. The secondary delay
path also known as the skewed delay path reduces the phase noise apart from
enhancing the frequency.
Fig.2 shows the reference delay cells presented in [18] and [16] respectively.
Transistors MN1 and MN2 are the input transistors to which the primary inputs are
connected. MP1 and MP2 form regenerative cross-coupled PMOS transistor pair in
both the designs. The strength of the latch is varied by changing the coupling between
MP1 and MP2 using control voltage v_ctrl that is connected to the gates of NMOS
switches MN3 and MN4. The coupling between MP1 and MP2 is enhanced by a
higher control voltage, which makes it more difficult to switch the output logic, hence
reducing the frequency. To MP3 and MP4, the secondary inputs of the multiple pass
architecture are connected. This effectively improves the switching frequency and
noise performance.

As the control voltage v_ctrl becomes lower the latching between MP1 and MP2
becomes weaker. When v_ctrl is sufficiently low such that the gate to source voltage
of MN3 and MN4 are lower than their threshold voltages, these transistors are turned
off. Tuning becomes difficult in such low values of v_ctrl. Therefore, transistors MP5
and MP6 are used by [16] to enhance the tuning range even when MN3 and MN4 are
turned off as in figure 4.1(b). These transistors are absent in the design presented in
figure 4.1(a) [18].

Fig.4.1 Reference Delay Cells
In low values of control voltage, if MP5 and MP6 are let to remain in ON condition
forever, it will add to the total noise of the circuit [16] [19]. Therefore, these
transistors are removed as in figure 4.2 to minimize the overall phase noise. Thus
better noise performance is achieved at the expense of lower tuning range. Apart from
this, a pair of cross coupled NMOS transistors MN5 and MN6 is included in the
design as in figure 4.2.
A delay cell is a combination of RC networks. A signal passing through a RC network
will get delayed. Cell delay is a function of output loading and input slew rate.
When an additional cross coupled NMOS pair is introduced it will add more
capacitance to the output load, therefore the overall cell delay is increased. The
increment in cell delay depends largely on the size of transistors in the cross coupled
pair. The effective resistance as seen at the output node of a cross coupled pair is

(a) (b)


negative and its value is -2/

, where

is the small signal trans-conductance of the

NMOS transistors when biased in saturation. This cross coupled pair helps establish
the logic levels in sharp transitions.

Fig.4.2 Proposed Low Phase Noise Delay Cell

Fig.4.3 Linear Model of Proposed Delay Cell

The design of the ring oscillator is a trade-off process that involves power, frequency,
area, and noise performance. While the ring oscillator is actually experiencing large
signal operation, it becomes extremely difficult to analyze its frequency and noise
characteristics due to the nonlinearity and complexity.
The differential input NMOS transistors (MN1/MN2 in this work) contribute a
significant portion of thermal noise as compared to the rest of the circuit. However, a
larger dimension is necessary if higher frequency is desired. Hence, there is a tradeoff
involving phase noise performance and operating frequency. If cross-coupled latches
are introduced, the slowdown impact on the entire circuit operation can be reduced by
decreasing the trans-conductance, i.e., by reducing the W/L or the drain current.
Once the sizes of the input differential NMOS transistors and cross-coupled latch are
determined, the

of PMOS load transistors (P1/P3 in this work) has to be larger

than a specific value in order to meet the minimum required dc gain, so as to ensure
the kick-start of the oscillation.
The layout of the proposed nine stage VCO is shown below. The core area is
measured as 236 x 87

Fig.4.4 Layout of Proposed Nine-stage VCO


The results of simulating the PLL synthesizer in Cadence Virtuoso design
environment are discussed in this chapter.
Figures 5.1 and 5.2 show the waveforms which ensure the functionality of phase
frequency detector, charge pump and loop filter. Figure 5.1(a) and 5.1(b) show the
reference and output waveforms respectively. It can be seen from the figure that the
output waveform is lagging in terms of phase/frequency from the reference waveform.
In order to compensate for this lag the UP signals are generated with a high pulse
width by the PFD (Fig.5.1 (c)), whereas DOWN pulses are only narrow spikes
(Fig.5.1 (d)). Hence the charge pump charges the loop filter capacitor so as to increase
the VCO control voltage (Fig.5.1 (e)) and thereby the output frequency. A steady
increase in capacitor voltage is visible in the figure.

Fig. 5.1 PFD, CP, LPF Waveforms for Phase Lagging Output






Similar to the above case figure 5.2 (a) and 5.2 (b) show the reference and output
waveforms respectively. It can be observed that the output waveform is leading in
terms of phase/frequency from the reference waveform. To minimize this phase lead
the DOWN signals are generated with a high pulse width by the PFD (Fig.5.2 (c)),
whereas UP pulses are only narrow spikes (Fig.5.2 (d)). Hence the charge pump
discharges the loop filter capacitor so as to decrease the VCO control voltage (Fig.5.2
(e)) and thereby the output frequency. A steady decrease in capacitor voltage is visible
in the figure.

Fig 5.2 PFD, CP, LPF Waveforms for Phase Leading Output
The standalone voltage controlled oscillator (VCO) exhibited a frequency range of
1.1GHz to 2.3GHz in which a good linearity in tuning is observed from 1.3GHz to 2.3
GHz. Figure 5.3 shows the tuning curve of VCO. It shows a negative conversion gain
of 1GHz/V. Sample oscillation of the VCO corresponding to a control voltage of
1.125 V is depicted in figure 5.4. Figure 5.5 shows a group of phase noise curves
when the control-voltage is varied from 0.6V to 1.8V. The VCO exhibits a phase
noise of -108.15dBc/Hz @ 1MHz offset at an operating frequency of 1.8GHz






(Fig.5.5). The variation of phase noise at an offset of 1 MHz with variation of control
voltage from 0.6V to 1.8V is shown in figure 5.6

Fig. 5.3 VCO Tuning Curve

Fig 5.4 VCO Output Waveform at 1.8 GHz

Figure 5.7 depicts the input and output waveforms of static frequency divider. Output
frequency is 8 times less than input frequency. Here, the PLL operating frequency of
1.8 GHz is selected as the input frequency.

Fig 5.5 VCO Phase Noise for different values of Control voltage

Fig 5.6 VCO Phase Noise at 1MHz offset for different values of Control voltage

0 0.5 1 1.5 2





Control Voltage (V)

Fig 5.7 Divider Waveforms

Fig. 5.8 PLL in Unlocked State






Fig 5.9 PLL in Locked State showing offset

Figure 5.8 depicts a PLL in unlocked state. The red color waveform on top is not
aligned with the black color one which is super imposed on it (Fig.5.8 (a)). Since the
output frequency divided by 8 (red) is less than the reference frequency (black) a
series of wide UP pulses are produced and VCO control voltage is increasing.
Figure 5.9 depicts a PLL in locked state. The red and green waveforms superimposed
on each other are phase locked with a static phase offset of 437ps (Fig.5.9 (a)). Both
UP and DOWN are narrow spikes once the phase lock is achieved. The duration of
UP pulse is more than DOWN due to the lagging static phase offset of 437ps. The
VCO control voltage is no more fluctuating and is a constant once phase lock is
achieved. It is separately depicted in figure 5.11 below. It takes around 4s for the
VCO control voltage to stabilize its value. Therefore the lock time of this PLL is 4s.
The various transient signals in PLL once it is switched on are shown in figure 5.12.
The figure clearly shows how the oscillation picks up slowly and then increase in






Fig 5.10 Starting of PLL Oscillations

Fig. 5.11 Initial Variation of VCO Control Voltage






Figure 4.11 shows the oscillations produced by PLL synthesizer. Its frequency is 1.8
GHz. The phase noise plot is as sown in figure 5.13.

Fig. 5.12 Oscillations Produced by PLL Synthesizer

Fig.5.13 PLL Phase Noise

The spectrum of PLL output is shown in figure 5.14. The spectrum has a sharp peak at
1.8 GHz.

Fig.5.14 PLL Output Spectrum

Table 5.1 Comparison of VCO Performance

Phase Noise
FoM (dBc/
Core Area

(at 1 MHz)
65mW -155.26 236 x 87 0.18m
[1] 0.479-4.09
(at 1 MHz)
13mW -154.4 - 0.18m
[3] 1.1-1.86
(at 1 MHz)
- - 106 x 76.2 0.18m
[7] 7.3-7.86
(at 1 MHz)
60mW -160.3 180 x 50 0.13m
[8] 0.075 to 6.9
(at 10 MHz)
9.32mW -153.7 70 x 105 0.18m

Table 5.1 compares the performance of the proposed low phase noise ring VCO with
a number of reference designs.


Table 5.2 Summary of Results
Parameter Value
Reference Frequency 225 MHz
Operating Frequency 1.8 GHz
Phase Noise -125dBc/Hz @ 1 MHz
Power Consumption 72.7mW
Settling Time 4s

Table 5.3 compares the performance of the PLL synthesizer presented in
this paper with a number of reference designs.

Table 5.1 Comparison of PLL Performance
Reference Frequency
[1] 1.92GHz 1.8 -100.9dBc/Hz 18 0.18m
[2] 1.6GHz 1.8 -120.6dBc/Hz 51.7 0.18m
[3] 2.4GHz 1.8 -105.8dBc/Hz 14.10 0.18m
This work 1.8GHz 1.8 -125.0dBc/Hz 72.0 0.18m


Integer-N radio frequency synthesizer using phase locked loop has been designed in
UMC 0.18m technology using Cadence Virtuoso design environment. It operates at
an input frequency of 225MHz and produces an output frequency of 1.8GHz. It is
observed that the PLL synthesizer gives a phase noise of -125dBc/Hz at an offset of
1MHz from the operating center frequency of 1.8GHz. The power consumption is
measured as 72.7mW. The proposed nine stage low phase noise differential ring VCO
operates between 1.1 and 2.3 GHz gives a phase noise of -108.15dBc/Hz at an offset
of 1MHz from a center frequency of 1.8 GHz. The VCO alone consumes 65mW of
power. The VCO occupies a core area of 236 m x 87m. The overall figure of merit
(FoM) of the VCO is estimated as -155.26dBc/Hz which is a competitive figure
compared to contemporary designs.
Future work involves the use of programmable divider so as to automatically switch
from one frequency band to the other according to a set of programming bits.


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