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A S V Aditya Email:

#CG11, Parimala Trinity, Contact no.: +91-9663733433
Sy No-69, Panathur Main road,
Kadubesanahalli, 560103
Seeking a challenging career as a Memory, IO, Analog and Mixed Signal Layout & Design Engineer in the
reputed Organization that offers sustained professional growth, while being resourceful, innovative and flexible.

Work Experience
A total of 5 yrs of technical work experience, off which, 2 yrs in SRAM/eDRAM and 2 yrs of
experience in Analog and Mixed Signal layouts.
o Hands-on exposure on the latest 10nm,14nm(SOI-FINFET) and 20nm (BULK-PLANAR)
CMOS technologies.
o In-depth and hands-on expertise in layout design of
TSV based layouts for 3D ICs.
NVROM/RAM Bit Cell Array and Periphery Logic.
eDRAM ( Core Array and Periphery, full chip exposure to 16MB & 256MB )
SRAM Leaf cells & SRAM Memory Compilers.
Various analog, full custom digital and mixed-signal circuits that include high current
LDOs and bidirectional I/Os.
o Designed robust layouts based on specific necessities of the design (both Memory and Mixed
Analog) at hand. Bit-Line, Word-Lines matching and Sense-Amplifier interference (due to
the signals in its proximity) in SRAM & eDRAM design. Electromigration, ESD, Latch-up
(Guard Rings), etc., in case of IOs (in BULK CMOS).
o Good exposure to CAD tools and flows pertaining to layout design, its automation and layout
reliability verification. [Virtuoso layout editor, Calibre DRC/LVS physical verification tool ,
Unix and shell scripting and custom SKILL scripting]
o Have exposure to various layout tools including Intels In-house Genesys, IBMs GYM
and Cadences Virtuoso - Suite of IC Mask Design Tools.
o Exposure on multiple VLSI process technologies [180nm, 90nm, 32, 28, 20, 14 & 10 nm]
o Good problem-solving and teamwork skills along with strong verbal and written
communication skills.

Project Details

IBM Semiconductor Research & Development Center, FEB 2013* [1 Year, 6 Months]
o Job title: Circuit Layout Design Specialist.
o Job Description: (Early Process development)
Work closely with Process & Enablement team for DTCO of eDRAM design.
Apply for design waivers and track their progress with Waiver Review Board.

Design various Device level & Functional Macros for measurement and study of
electrical parameters.
14nm: Completed layout of 144K NVROM macro using traditional CMOS.
14nm: Completed layout of inline testable 16M eDRAM.
14nm: Worked at Full Chip layout of 256M eDRAM design.
10nm: Completed layout of inline testable 16K eDRAM Macro [Using Gate
Array approach].
Multiple Device & Functional Macros for 14 & 10nm related to eDRAM.

Texas Instruments , August 2011 JAN 2014 [1 Year, 5 Months ]
o Job title: Design Engineer
o Layout Job description: Floor-planning and designing of simple Bi-Directional I/Os,
Optimized Leaf cell design of SRAM components like SENSE-AMP, PRECHARGE, ROW-
o Scripting and Design Automation: Developed SKILL scripts for Memory Compilers [Layout
and Schematic Generators]. Developed SKILL scripts for Layout and Schematic Quality
checks [Area usage, Diffusion Contacts analysis, Poly Routing detection in layouts and
checks for Antenna Diodes and Gates Connected to power in schematics]
o Achievements: Successfully developed layouts for I/Os and SRAM. Wrote SKILL scripts for
Memory Compilers. And scripts to check Quality & Reliability of layout and schematics.

Wipro Technologies , December 2009 August 2011 [1Year, 8 Months]
o Job title: Project Engineer.
o Job description: Layout/Mask Designer for Analog Mixed Signal designs.
o Job responsibilities: Floor-plan, design and optimize layout designs based on variety of
design constraints [space, power/current, signal integrity and Noise]
o Achievements: Successfully completed floor plan and layout of multiple critical blocks such
as voltage regulators, LDOs, LCVRs, error amplifiers, high current driver blocks with all the
layout requirements and constraints.

DigiLogic Systems, November 2008 December 2009 [1 Year]
o Job title: Lab View Developer
o Job description: To design and develop LabView code for Data Acquisition systems,
Automated Test Equipment, Test Benches and Control Units using NI-DAQ hardware.
o Job responsibilities: Visiting customer location, gathering technical requirements and
developing the solution for the customer.
o Achievements: Solely handled and successfully completed an Automated Test Jig project
involving multiple Power, Control and DAQ equipment. The project met all the customer
requirements and quality expectations.

OS Platform, Software proficiency and EDA Tools
Computer Languages : C, C++, Perl, Shell & SKILL Scripting ;

Operating Systems : MS DOS, Windows 98, NT, XP, Vista, LINUX.

CAD & EDA Tools:
o Custom Layout Design Tools

Cadence Virtuoso - Layout design tool.
Cadence SKILL Cadence script for Design & Automation.
Genesys (Intel In-House Tool)
GYM (IBMs In-House Tool)
o Logic Design & Simulation Tools:
MultiSim, Active HDL, Verilog, Xilinx.
o Layout verification tools:
Calibre DRC,LVS.
o Other scientific computation & Automation tools:
Matlab & LabView.
Activities, Interests & Achievements
Academic Activities and Achievements

o Designed and conceived RoBionic Eye: An Intelligent Electronic Eye for Laser Tracking,
Laser Telemetry using a webcam mounted on a self-built tilt-n-pan platform. The control
system was coded in MatLab, so that it could function autonomously without any user
supervision. [Submitted as my Final Year Project in 2008].

o Won 1
prize in SRUJ ANA 2006 for Working Model METACARPALS (a Microcontroller
based Robotic arm). The Robotic Arm can be programmed to pick-n-place objects repetitively
reflecting a typical production belt scenario.

o Successfully executed the assigned tasks at IIT (Shaastra06) in Stair Climbing Event.

o Participated in ROBOTIC WORKSHOP (TECSTACY06) conducted by CBIT.

Technical Interests:
o 3D ICs & FinFET approach for Low-Power, Low-Leakage VLSI Design, Layout and
fabrication technologies.
o Lithography and OPC/RET techniques for reliable mask design.
o MEMS and its applications.
o Robotics/Mechatronics & Internet-of-Things(IoT).

Personal Skills:
Good verbal and written skills, willingness to learn and apply, team facilitator, aggressive problem solver,
hard-working, innovative and patient.

B.Tech in Electronics & Communication Engineering (2008).

Qualification Educational Board Institute Marks Year
B.Tech (ECE) JNTU JBIET 72.18% (agg.) 2008
Board of
Education, A.P
Sri Chaitanya
Jr. Kalasala
78.50% (agg.) 2003
(All India Sec. School
CBSE Kendriya
73.40% 2001

Personal Profile
Name : A S V Aditya
Fathers Name : A. Veeranjaneyulu
Mothers Name : A. Uma Devi
Nationality : INDIAN
Date of Birth : 31 December 1985
Languages Known : Telugu, Hindi & English.

Place: Bangalore (A S V ADITYA)