# Exercises for

Differential Amplifiers
ECE 102, Fall 2012, F. Najmabadi
F. Najmabadi, ECE102, Fall 2012 (2/37)
Exercise 1: Compute V
D
, V
S
, V
DS
and V
GS
if I
D3
= 2 mA, R
D
= 500 Ω,
V
OV3
= 0.5 V, and identical Q1 &Q2 with µ
n
C
ox
(W/L ) = 8 mA/V
2
,
V
t
= 0.5 V, λ = 0.
A) For V
G
= 0 and B) For V
G
= 1 V. Repeat the exercise for λ = 0.1 V
-1
.
 This exercise shows that precise biasing of Q1 and Q2 is not necessary as V
S
 Inclusion of channel-length modulation does not impact the bias points of Q1
and Q2 (which is set by the current source).
F. Najmabadi, ECE102, Fall 2012 (3/37)
Assume Saturation
V 1
1 1
= + =
t OV GS
V V V
Saturation &
V 1 2 1 ) 2 (
V 5 . 2 ) 1 ( 5 . 1
V 1 1 0
0 A)
3 3 1 1
3
1 1
1 1
1
⇒ > >
= + − = − − =
= − − = − =
− = − = − =
=
OV DS OV DS
S DS
S D DS
GS G S
G
V V V V
V V
V V V
V V V
V
V 5 . 0
1
=
OV
V
Ignoring channel-length modulation (λ = 0)
2
1
3 2
1 1
3
10 4 ) / ( 5 . 0 10 1
OV OV ox n D
V V L W C I
− −
× = = = × µ
V 5 . 1 5 . 0 2 2
1 1
= − = − =
D D D
I R V KVL:
Note that as the bias voltage of Q1, V
G1
, changes, V
S
is
adjusted automatically to get the necessary V
OV1
and I
D1

mA 1 5 . 0
3 2 1
= = =
D D D
I I I
Saturation &
V 2 2 0 ) 2 (
V 5 . 1 0 5 . 1
0 1 1
1 A)
3 3 1 1
3
1 1
1 1
1
⇒ > >
= + = − − =
= − = − =
= − = − =
=
OV DS OV DS
S DS
S D DS
GS G S
G
V V V V
V V
V V V
V V V
V
F. Najmabadi, ECE102, Fall 2012 (4/37)
Assume Saturation
) (
) (
) (
1 1 1
1 1 1
1 1 1
1 1
G t D OV
G t OV D
G GS D
S D DS
V V V V
V V V V
V V V
V V V
− + + =
− + + =
− + =
− =
Including channel-length modulation (λ = 0.1)
25 . 0 ) 1 . 0 1 (
) 1 ( ) / ( 5 . 0 10 1
1
2
1
1
2
1 1
3
= +
+ = = ×

DS OV
DS n OV ox n D
V V
V V L W C I λ µ
Need to write V
DS1
in terms of V
OV1
:

For a given V
G1
, we then substitute for V
DS1
in I
D

equation which leads to a cubic equation for V
OV1

V 5 . 1 5 . 0 2 2
1 1
= − = − =
D D D
I R V KVL:
mA 1 5 . 0
3 2 1
= = =
D D D
I I I
F. Najmabadi, ECE102, Fall 2012 (5/37)
V 948 . 0
1 1
= + =
t OV GS
V V V
1 1 1 1
) (
G t OV D DS
V V V V V − + + =
V 448 . 0
1
=
OV
V
Including channel- length modulation (λ = 0.1)
25 . 0 ) 1 . 0 1 (
1
2
1
= +
DS OV
V V
V 5 . 1
1
=
D
V
V 948 . 0 948 . 0 0
1 1
− = − = − =
GS G S
V V V
C) V
G1
= 0
0 . 2 ) 0 5 . 0 5 . 1 (
1 1 1
+ = − + + =
OV OV DS
V V V
0 25 . 0 2 . 1 1 . 0
25 . 0 )] 0 . 2 ( 1 . 0 1 [
2
1
3
1
1
2
1
= − +
= + +
OV OV
OV OV
V V
V V
V 448 . 2 0 . 2
1 1
= + =
OV DS
V V
V 967 . 0
1 1
= + =
t OV GS
V V V
V 467 . 0
1
=
OV
V
V 033 . 0 967 . 0 1
1 1
+ = − = − =
GS G S
V V V
0 . 1 ) 1 5 . 0 5 . 1 (
1 1 1
+ = − + + =
OV OV DS
V V V
0 25 . 0 1 . 1 1 . 0
25 . 0 )] 0 . 1 ( 1 . 0 1 [
2
1
3
1
1
2
1
= − +
= + +
OV OV
OV OV
V V
V V
V 467 . 1 0 . 1
1 1
= + =
OV DS
V V
D) V
G1
= 1 V
V 052 . 1 2 948 . 0 ) 2 (
3
= + − = − − =
S DS
V V V 033 . 2 2 033 . 0 ) 2 (
3
= + = − − =
S DS
V V
F. Najmabadi, ECE102, Fall 2012 (6/37)
V 00 . 1
V 50 . 2
V 00 . 1
V 0
V 500 . 0
mA 0 . 1
3
1
2 1
2 1
2 1
=
=
− =
= =
= =
= =
DS
DS
S
G G
OV OV
D D
V
V
V
V V
V V
I I
Include channel-length modulation
Specified
parameters
 Inclusion of channel-length modulation does
not impact the bias points of Q1 and Q2
(which is set by the Q3 current source).
V 2.0
V 50 . 1
0
V 0 . 1
V 500 . 0
mA 0 . 1
V 1.052
V 448 . 2
V 948 . 0
0
V 448 . 0
mA 0 . 1

V 2.033
V 467 . 1
V 033 . 0
V 0 . 1
V 467 . 0
mA 0 . 1
Ignore channel-length modulation
 Bias voltage of Q1 and Q2 (V
G
) does not affect I
D1
as V
S
G
affects only V
DS1
and
V
DS3
and precise biasing is NOT necessary.
F. Najmabadi, ECE102, Fall 2012 (7/37)
Exercise 2: Find the differential gain and (W/L) of all transistors in the
circuit below, Q3 & Q4 are matched, Q1 & Q2 are matched, all transistors
have V
OV
= 0.2 V, µ
n
C
ox
= 400 µA/V
2
, µ
p
C
ox
= 100 µA/V
2
, and V
An
=
|V
Ap
|= 3.6 V. Ignore channel-length modulation in biasing calculations.
For symmetric circuits:
d
d o
d
d o
d
d o
d
d o d o d o d o o o
v
v
v
v
v
v
A
v v v v v v
5 . 0
2
2
1 , 1 , ,
, 1 , 1 , 2 , 1 2

= × − = =
− = − = → − =
F. Najmabadi, ECE102, Fall 2012 (8/37)
Since transistors are matched and have the same V
OV
:
2 1
2
1 1 1
6
) / ( 5 . 12 ) / (
) / ( 5 . 0 10 100
L W L W
V L W C I
OV ox n D
= =
= = ×

µ
A 100
4 3 2 1
µ = = = =
D D D D
I I I I
4 3
2
3 3 3
6
) / ( 50 ) / (
) / ( 5 . 0 10 100
L W L W
V L W C I
OV ox p D
= =
= = ×

µ
A/V 10
2
3
1
1
1

= =
OV
D
m
V
I
g k 36
1
1
1
= =
D
A
o
I
V
r
Differential Mode
Half Circuit
k 36
3
3
3
= =
D
A
o
I
V
r
18 10 18 10 k) 36 || k 36 ( 10 ) || (
3 3 3
o3 o1 1
− = × × − = − = − =
- -
m d
r r g A
) || (
5 . 0
3 1 1
1 , ,
o o m
d
d o
d
d o
d
r r g
v
v
v
v
A
− =

= =
F. Najmabadi, ECE102, Fall 2012 (9/37)
Exercise 3: The differential amplifier below should achieve a differential
gain of 40 with a power consumption of 2 mW. All transistors operate with
the same V
OV
. Find (W/L) of all transistors, V
G3
, V
G4
, and V
G5
.

n
C
ox
= 400 µA/V
2
, µ
p
C
ox
= 100 µA/V
2
, λ
n
= 0.1 /V, λ
p
= 0.2 /V, and
V
tn
= |V
tp
|= 0.4 V. Ignore channel-length modulation in biasing.
Power Consumption:
mA 556 . 0 5 . 0
mA 11 . 1 10 2 8 . 1
5 4 3 2 1
5
3
5
= = = = =
= → × = =

D D D D D
D D
I I I I I
I I P
F. Najmabadi, ECE102, Fall 2012 (10/37)
Differential Mode
Half Circuit
3 5 . 0
) 5 . 0 (
||
5 . 0
1 1

1

1
1
1 1
1 1
3 1
1 1
1 1 3
3
1
1
o
o o
o o
o o
o o
p
n
D n p
n
D p D p
o
D n
o
r
r r
r r
r r
r r
I I I
r
I
r
=
+
×
=
= × = × = = =
=
λ
λ
λ λ
λ
λ λ
λ
V 167 . 0
40
3 . 0
2 1 2
3
1

3
1
) || ( | |
1
1 1 1
1
1 1 3 1 1
=
= = × × =
= + =
OV
OV D n OV
D
o m o o m d
V
V I V
I
r g r r g A
λ
) || (
5 . 0
3 1 1
1 , ,
o o m
d
d o
d
d o
d
r r g
v
v
v
v
A
− =

= =
F. Najmabadi, ECE102, Fall 2012 (11/37)
V 167 . 0
mA 556 . 0 5 . 0
5 4 3 2 1
5 4 3 2 1
= = = = =
= = = = =
OV OV OV OV OV
D D D D D
V V V V V
I I I I I
100 ) / ( ) / (
) 167 . 0 ( ) / ( 10 400 5 . 0 10 556 . 0
) / ( 5 . 0
1 2
2
1
6 3
2
1 1 1
= =
× × × = ×
=
− −
L W L W
L W
V L W C I
OV ox n D
µ
400 ) / ( ) / (
) 167 . 0 ( ) / ( 10 100 5 . 0 10 556 . 0
) / ( 5 . 0
3 4
2
3
6 3
2
3 3 3
= =
× × × = ×
=
− −
L W L W
L W
V L W C I
OV ox p D
µ
200 ) / (
) 167 . 0 ( ) / ( 10 400 5 . 0 10 11 . 1
) / ( 5 . 0
5
2
5
6 3
2
5 5 5
=
× × × = ×
=
− −
L W
L W
V L W C I
OV ox n D
µ
V 567 . 0 0 567 . 0
V 567 . 0 4 . 0 167 . 0
5 5 5
5 5
= + = + =
= + = + =
S GS G
tn OV GS
V V V
V V V
V 233 . 1 567 . 0 8 . 1
V 567 . 0 4 . 0 167 . 0 | |
3 3 3
3 3
= − = − =
= + = + =
SG S G
tp OV SG
V V V
V V V
F. Najmabadi, ECE102, Fall 2012 (12/37)
Exercise 4: The circuit below is fabricated with V
An
= |V
Ap
| = 3.6 V,
µ
n
C
ox
= 100 µA/V
2
& µ
p
C
ox
= 25 µA/V
2
. All transistors operate with
V
OV
= 0.5 V. Find (W/L) of all transistors and the differential gain of the
circuit.
F. Najmabadi, ECE102, Fall 2012 (13/37)
k 36
10 100 278 . 0
1 1
...
mA/V 4 . 0
5 . 0
10 100 2 2
...
V 5 . 0 ...
A 100 5 . 0 ...
6
1
8 2 1
6
1
1
8 2 1
9 8 2 1
9 8 2 1
=
× ×
= = = = =
=
× ×
= = = = =
= = = = =
= = = = =

D
o o o
OV
D
m m m
OV OV OV OV
D D D D
I
r r r
V
I
g g g
V V V V
I I I I
λ
µ
/V 0.278
6 . 3
1 1
= = = =
A
p n
V
λ λ
NMOS: Q1, Q2, Q3, & Q4:
8 ) / ( ) / ( ) / ( ) / (
) 5 . 0 ( ) / ( 10 100 5 . 0 10 100
) / ( 5 . 0
1 2 3 4
2
1
6 6
2
1 1 1
= = = =
× × × = ×
=
− −
L W L W L W L W
L W
V L W C I
OV ox n D
µ
PMOS: Q5, Q6, Q7, & Q8:
32 ) / ( ) / ( ) / ( ) / (
) 5 . 0 ( ) / ( 10 25 5 . 0 10 100
) / ( 5 . 0
5 6 7 8
2
1
6 6
2
5 5 5
= = = =
× × × = ×
=
− −
L W L W L W L W
L W
V L W C I
OV ox p D
µ
F. Najmabadi, ECE102, Fall 2012 (14/37)
Differential Mode
Half Circuit
7.63 40.6k) || k 36 ( 10 0.4
) || ( ) 5 . 0 /(
3
3 1 1 1 1
− = × × − =
− = − =

i o m d vQ
R r g v v A
k 6 . 40
1

3 3
3
3
=
+
′ +
=
o m
L o
i
r g
R r
R
8 . 103
1 3
− = =
vQ vQ d
A A A
k 36 ...
mA/V 4 . 0 ...
8 2 1
8 2 1
= = = =
= = = =
o o o
m m m
r r r
g g g
k 590 10 36 ) 36 4 . 0 1 ( 10 36
) 1 (
3 3
7 7 5 5
= × + × + × × =
+ + = ′
o o m o L
r r g r R
Method 1: Use formula for Cascode Amplifier on
Lecture Set 6, slide 14 (which assumes g
m
r
o
>> 1):
104 ) 10 36 10 0.4 ( 5 . 0
) ( 5 . 0
5 . 0

2 3 3
2 1 ,
− = × × × − =
− =

=

d
o m
d
d o
d
A
r g
v
v
A
d
d o
d
d o
d
d o
d
v
v
v
v
v
v
A
5 . 0
2
1 , 1 , ,

= × − = =
Method 2: Use multistage amplifier calculations (similar to
Lecture Set 6, slide 14 but not assuming g
m
r
o
>> 1):
13.6 590k) || k 36 ( 10 0.4
) || ( /
3
3 3 1 , 1 3
= × × =
′ ≈ =

L o m d o vQ
R r g v v A
g
m
r
o
>> 1 is a good
approximations
F. Najmabadi, ECE102, Fall 2012 (15/37)
Exercise 5: Assume Q3 and Q4 as well Q1 and Q2 are identical. Compute the
differential gain.
 This is a practice problem in
constructing half-circuit.
F. Najmabadi, ECE102, Fall 2012 (16/37)
Half-circuit for differential Gain
Zero voltage at symmetry line
Replace Q3 by
Elementary R forms
) || || (

5 . 0
3 1 1
1 , ,
P o o m
d
d o
d
d o
d
R r r g
v
v
v
v
A
− =

= =
F. Najmabadi, ECE102, Fall 2012 (17/37)
Exercise 6: Compute the differential gain.
 This problem has it all, half circuit, constructing
resistances from elementary R form, and
Cascode amplifier.
F. Najmabadi, ECE102, Fall 2012 (18/37)
Differential-Mode half-circuit
2 / || )] 2 / || ( 1 [
7 7 5 p o p o m o L
R r R r g r R + + = ′
) || ( ) 5 . 0 /(
3 1 1 1 1 i o m d vQ
R r g v v A = − =
3 3
3
3
1

o m
L o
i
r g
R r
R
+
′ +
=
) || )( || (
3 3 1 3 1 1 3 L o i o m m vQ vQ d
R r R r g g A A A ′ − = =
) || ( /
3 3 1 , 1 3 L o m d o vQ
R r g v v A ′ ≈ =
Since R
p
value is not given, we cannot simplify R’
L
expression using g
m
r
o
>> 1 .
v
1
F. Najmabadi, ECE102, Fall 2012 (19/37)
Exercise 7: What is the input common-mode range in the circuit below. Q1
and Q2 are Identical and R
D
= 500.
Use µ
n
C
ox
(W/L ) = 8 mA/V
2
, V
t
= 0.5 V and V
G3
= −1 V.
 The input common-mode level is the range of DC
values that can be applied to the gate of Q1 and
Q2 (bias + signal) for which transistors remain in
saturation.
o Basically we are looking for range of DC
voltages (i.e., bias) that can be applied to Q1
and Q2 while keeping them in saturation.
o Then, for any given bias voltage, we can
calculate the range of common-mode signals
that can be applied to the circuit.
 There are two limits: 1) for Q1 and Q2 remain in
saturation, 2) for Q3 to remain in saturation.
 It is straight forward to extend this to active loads.
F. Najmabadi, ECE102, Fall 2012 (20/37)
Assume Q1 and Q2 in Saturation
2
1
3 2
1 1
3
10 4 ) / ( 5 . 0 10 1
OV OV ox n D
V V L W C I
− −
× = = = × µ
V 1
1 1
= + =
t OV GS
V V V
V 5 . 1 5 . 0 2 2
1 1
= − = − =
D D D
I R V
V 5 . 0
1
=
OV
V
1 1 5 . 1
1
1
≤ − ≤ −
− =
− =
CM
CM S
S CM GS
V
V V
V V V
V 1 5 . 1 ≤ ≤ −
S
V
V 5 . 1 5 . 0 2
5 . 0 ) 2 (
3 3
3 3
− = + − ≥
≥ − − = −

S
S S D
OV DS
V
V V V
V V
For Q3 in saturation:
V 5 . 0 5 . 0 ) 2 ( 1
3 3 3 3
= − − − − = − − = − =
t S G t GS OV
V V V V V V
For Q1/Q2 in saturation:
V 1 5 . 0 5 . 1
5 . 0 5 . 1
1 1
1 1
= − ≤
≥ − = −

S
S S D
OV DS
V
V V V
V V
V 2 5 . 0 ≤ ≤ −
CM
V
F. Najmabadi, ECE102, Fall 2012 (21/37)
Exercise 8: Circuit below is designed to operate at zero bias voltage at the
gate of Q1 and Q2 (Q1 & Q2 are matched and λ = 0). The practical circuit,
however includes a slight mis-match of R
D1
= R
D
− 0.5 ∆R
D
and R
D2
= R
D
+
0.5 ∆R
D
(∆R
D
/R
D
is small).
A) If v
1
= v
2
= 0, find V
o
= v
o2
− v
o1
(Differential DC voltage at the output).
B) For what values of V
OS
= v
2
− v
1
, the DC output voltage will be zero.
Ignore channel-length modulation.
 No amplifier chip can be manufactured with perfect
symmetry. Mis-matches not only affect CMRR but DC
voltages.
 Differential DC voltage at the output and the input
offset voltage, V
OS
, are important specs. Chips
typically include pins for feedback to zero out these
voltages.
 Note: v
1
and v
2
are DC values in this problem, they
can be viewed either as mis-matched bias (and no
signal) and/or signal (but with a matched “zero” bias).
F. Najmabadi, ECE102, Fall 2012 (22/37)
Since transistors are matched and V
GS1
= V
GS2

(because v
1
= v
2
):
) 5 . 0 ( 5 . 0
) 5 . 0 ( 5 . 0
2 2 2 2
1 1 1 1
D D o DD D D DD D o
D D o DD D D DD D o
R R I V I R V V v
R R I V I R V V v
∆ + − = − = =
∆ − − = − = =
o D D
I I I 5 . 0
2 1
= =
D o o o o
R I v v V ∆ − = − = 5 . 0
1 2
Output Offset Voltage
A) If v
1
= v
2
= 0, find V
o
= v
o2
− v
o1
(Differential DC voltage at the output):
D D D D D D
R R R R R R ∆ + = ∆ − = 5 . 0 & 5 . 0
2 1
F. Najmabadi, ECE102, Fall 2012 (23/37)
o D D
I I I 5 . 0
2 1
= =
Method 1: Viewing V
OS
as the signal.
The bias voltages remain at zero and V
o
has the
above value. A differential signal v
d
= V
OS
is applied
to the circuit leading to a differential output , v
o,d
.
We want to find V
OS
such that v
o,d
+ V
o
= 0
D o o o o
R I v v V ∆ − = − = 5 . 0
1 2 Output Offset Voltage
o D OS m d o
D D D D OS m d o
D D OS m d o d o d o
V R V g v
R R R R V g v
R R V g v v v
− = − =
∆ − + ∆ + − =
+ − = − =
,
,
1 2 , 1 , 2 ,
] [ 5 . 0
) ( 5 . 0
D D OS D
OV
D
D o OS D m
R I V R
V
I
R I V R g ∆ − = → ∆ − =
1
2
5 . 0 5 . 0
1
D
D
OV OS
R
R
V V

× − =
OS OS
V v V v 5 . 0 and 5 . 0
2 1
+ = − =
Input Offset Voltage
B) For what values of V
OS
= v
2
− v
1
, the DC output voltage will be zero.
Ignore channel-length modulation.
OS D m OS D m d o
OS D m OS D m d o
V R g V R g v
V R g V R g v
2 2 , 2
1 1 , 1
5 . 0 ) 5 . 0 (
5 . 0 ) 5 . 0 (
− = + − =
+ = − − =
F. Najmabadi, ECE102, Fall 2012 (24/37)
2 2 1 1 2 1

D D DD D D DD o o
I R V I R V v v − = − → =
Method 2: Viewing V
OS
as the bias voltage:
0 such that 5 . 0 and 5 . 0
1 2 1 2
= − = − = + =
o o o os G os G
v v V V V V V
) / ( 5 . 0 5 . 0 0
2
2 1 2 1 OV ox n o D D G G
V L W C I I I V V µ = = = ⇒ = =
) / 1 ( 5 . 0
) / 1 ( ) / ( 5 . 0
) ( ) / ( 5 . 0
) 5 0 ( ) / ( 5 . 0
2
2
2
1
OV OS o
OV OS OV ox n
OV OS OV ox n
OS OV ox n D
V V I
V V V L W C
V V V L W C
V . V L W C I
− =
− =
− ≈
− =
µ
µ
µ
) / 1 ( 5 . 0 ) 5 0 ( ) / ( 5 . 0
2
2 OV OS o OS OV ox n D
V V I V . V L W C I + ≈ + = µ
0 / ) / ( 2 = ∆ +
D D OV OS
R R V V
) / 5 . 0 1 )( / 1 ( 5 . 0 ) / 5 . 0 1 )( / 1 ( 5 . 0
D D OV OS D o D D OV OS D o
R R V V R I R R V V R I ∆ + + = ∆ − −
For:
Find:
5 . 0
1
D
D
OV OS
R
R
V V

× − =
2 2 1 1 D D D D
R I R I =
Dropping V
2
OS
terms by
assuming V
OS
<< V
OV

F. Najmabadi, ECE102, Fall 2012 (25/37)
Exercise 9: Consider the circuit below with µ
n
C
ox
= 90 µA/V
2
, µ
p
C
ox
=
30 µA/V
2
, V
tn
= − V
pn
= 0.7 V and V
An
= − V
Ap
= 20 V. The circuit is
to operate such that all transistors operate at V
OV
= 0.5 V, I
D1
= I
D2
=
I
D3
= I
D4
= I
ref
= 0.2 mA, and (W/L )
5
= (W/L )
6
.
a) Design the circuit (i.e., find (W/L) of all transistors).
b) Find the differential gain.
c) Find the common mode response at v
o1
(i.e., v
o1
/v
CM
).
d) Find the input common-mode range
e) Find the allowable range of the output voltage.
Ignore channel-length modulation in biasing calculations.
F. Najmabadi, ECE102, Fall 2012 (26/37)
1) Q1 & Q2: PMOS
Differential
amplifier
2) Q5: Biasing current mirror
5) Q6: Providing
reference voltage
(or current) for Q5
3) Q3& Q4: current-
6) Q7: Providing
“I
ref
” for Q6
4) Qref: The
reference leg of
current mirror for
the circuit
F. Najmabadi, ECE102, Fall 2012 (27/37)
8 . 17 ) / (
) 5 . 0 ( ) / ( 10 90 0.5 ) / ( 5 . 0 10 2 . 0
2 -6 2 3
=
× × = = = ×

ref
ref OV ref ox n ref
L W
L W V L W C I µ
mA 4 . 0
2 1 5
= + = =
D D D
I I I I
a) Find (W/L of all transistors)
I
D1
= I
D2
= I
D3
= I
D4
= I
ref
= 0.2 mA,
and (W/L )
5
= (W/L )
6
.
Step 1: Compute all currents.
NMOS: Qref, Q3, Q4, and Q7
( )
( )
mA 4 . 0
/
/

5
5
6
6
= × =
D D
I
L W
L W
I
mA 4 . 0
6 7
= =
D D
I I
Step 2: Compute (W/L)s (V
ov
= 0.5 V)
6 . 35 ) / ( 2 ) / ( mA 4 . 0 2
7 7
= = ⇒ = =
ref ref D
L W L W I I
8 . 17 ) / ( ) / ( ) / ( mA 2 . 0
4 3 4 3
= = = ⇒ = = =
ref ref D D
L W L W L W I I I
F. Najmabadi, ECE102, Fall 2012 (28/37)
3 . 53 ) / (
) 5 . 0 ( ) / ( 10 30 0.5 ) / ( 5 . 0 10 2 . 0
1
2
1
-6 2
1 1
3
=
× × = = = ×

L W
L W V L W C I
OV ox p D
µ
PMOS: Q1, Q2, Q5, and Q6
107 ) / ( 2 ) / ( ) / ( mA 4 . 0 2
1 6 5 1 6 5
= = = ⇒ = = = L W L W L W I I I
D D D
3 . 53 ) / ( ) / ( mA 2 . 0
1 2 1 2
= = ⇒ = = L W L W I I
D D
A/V 10 8
5 . 0
10 2 . 0 2 2
4
3
1
1
1 2

× =
× ×
= = =
OV
D
m m
V
I
g g
k 00 1
10 2 . 0
20
3
1
1
1 2
=
×
= = =

D
A
o o
I
V
r r
Small signal parameters:
k 00 1
10 2 . 0
20
3
3
3
3 4
=
×
= = =

D
A
o o
I
V
r r
k 50
10 4 . 0
20
3
5
5
5
=
×
= =

D
A
o
I
V
r
F. Najmabadi, ECE102, Fall 2012 (29/37)
40 k) 100 || k 100 ( 10 8
) || (
5 . 0
4
3 1 1
1 ,
− = × − =
− =

=

d
o o m
d
d o
d
A
r r g
v
v
A
98 . 0
1 80 1
80
1 10 50 10 8 2 1
10 100 10 8
/ 2 1
, 1 , 2
3 4
3 4
, 1
1 3 5 1
3 1
, 1
− =
+ +
− = =
+ × × × × +
× × ×
− =
+ +
− =

c
c o
c
c o
c
c o
o o o m
o m
c
c o
v
v
v
v
v
v
r r r g
r g
v
v
b) Find the differential gain:
c) Find common mode response, v
o1
:
F. Najmabadi, ECE102, Fall 2012 (30/37)
d) Find input common mode range:
1) Q5 in saturation:
2 . 1 V 1.2 | |
1 1
+ = ⇒ = + = −
CM S tp OV CM S
V V V V V V
V 2 5 . 0 5 . 2 5 . 2
5 1 5 5
= − ≤ = ⇒ ≥ − =
D S OV D SD
V V V V V
2) Q1/Q3 in saturation:
3 3
1 1

OV DS
OV SD
V V
V V

5 . 1 1 ) 5 . 2 (
V 1
1 1
3 1
− ≥ ⇒ ≥ − −
= + ≥ +
S S
OV OV DS SD
V V
V V V V
V 2.0 .5 1
1
≤ ≤ −
S
V
The above equation indicates V
S1
changes
and tracks V
CM
as V
CM
changes. V
S1
is
limited by two criteria below:
V 2.0 1.2 .5 1 ≤ + ≤ −
CM
V
V 0.8 .7 2 ≤ ≤ −
CM
V
Note that the requirement on Q1/Q3 in saturation is usually more restrictive than above as Q1/Q3 do
not usually reach saturation together (calculation above represents “the best case”). However, correct
solution requires that we include channel-length modulation and calculate the relationship between
V
SD1
& V
DS3
(same arguments apply to part e).
F. Najmabadi, ECE102, Fall 2012 (31/37)
e) Find allowable range of output voltage:
1) Q3 in saturation:
V 2 5 . 0 5 . 2
) 5 . 2 (
1
1 3
− = + − ≥
≥ − − =
o
OV o DS
v
V v V
2) Q1/Q5 in saturation:
OV SD
OV SD
V V
V V

5
1

V 5 . 1
1 5 . 2
V 1 2
1
1 1 5
1 5

≥ − = +
= ≥ +
o
o SD SD
OV SD SD
v
v V V
V V V
V 1.5 .0 2
1
≤ ≤ −
o
v
F. Najmabadi, ECE102, Fall 2012 (32/37)
Exercise 10: Consider the circuit below with µ
n
C
ox
= 400 µA/V
2
,
µ
p
C
ox
= 100 µA/V
2
, and V
tn
= − V
pn
= 0.4 V. All transistors operate at
V
OV
= 0.2 V and I
D1
= I
D2
= I
D3
= I
D4
= I
D6
= I
ref
= 0.2 mA
a) Design the circuit (i.e., find (W/L) of all transistors)
b) Find the input common-mode range
c) Find the differential gain (λ = 0.2 V
-1
)
F. Najmabadi, ECE102, Fall 2012 (33/37)
1) Q1 & Q2: NMOS Differential
amplifier with single-ended
output (1
st
stage)
3) Q5: Current-
mirror bias for
differential
2) Q6: PMOS CS
amplifier (2
nd
stage)
5) Q3/Q4: asymmetric
differential amplifier
6) Q7: current-
Q6 CS amplifier
4) Qref: The
reference leg of
current mirror for
the circuit
F. Najmabadi, ECE102, Fall 2012 (34/37)
25 ) / ( ) / ( 5 . 0 10 2 . 0
2 3
= ⇒ = = ×

ref OV ref ox n ref
L W V L W C I µ
mA 4 . 0
2 1 5
= + =
D D D
I I I
a) Find (W/L of all transistors).
Step 1: Compute all currents.
NMOS: Qref, Q1, Q2, and Q7 (all have same I
D
and V
OV
)
mA 2 . 0
6 7
= =
D D
I I
Step 2: Compute (W/L)s (V
ov
= 0.2 V)
50 ) / ( 2 ) / ( mA 4 . 0 2
5 5
= = ⇒ = =
ref ref D
L W L W I I
25 ) / ( ) / ( ) / ( ) / ( mA 2 . 0
7 2 1 7 2 1
= = = = ⇒ = = = =
ref ref D D D
L W L W L W L W I I I I
mA 2 . 0
6 4 3 2 1
= = = = = =
ref D D D D D
I I I I I I
100 ) / ( ) / ( 5 . 0 10 2 . 0
3
2
3 3
3
= ⇒ = = ×

L W V L W C I
OV ox p
µ
PMOS: Q3, Q4, and Q6 (all have same I
D
and V
OV
)
100 ) / ( ) / ( ) / ( mA 2 . 0
6 4 3 6 4 3
= = = ⇒ = = = L W L W L W I I I
D D D
F. Najmabadi, ECE102, Fall 2012 (35/37)
b) Find input common mode range:
1) Q5 in saturation:
V 6 . 0
1 1 1
− = ⇒ + = = −
CM S tn OV GS S CM
V V V V V V V
V 8 . 0 1 2 . 0 ) 1 (
5 1 5 5
− = − ≥ = ⇒ ≥ − − =
D S OV D DS
V V V V V
2) Q1/Q3 and Q2/Q4 in saturation (because the circuit is NOT symmetric,
we need to consider both cases and choose the most restrictive one).
1 3 3 3
3 3 3
V 0.4 1
V 0.6 | |
D D D SD
tp OV SG SD
V V V V
V V V V
= = ⇒ − =
= + = =
V 0.2
V 2 . 0 4 . 0
1
1 1 1 1

= ≥ − = − =
S
OV S S D DS
V
V V V V V
V 2 . 0 8 . 0
1
≤ ≤ −
S
V
Similar to problem 9, we look at V
S1
limits:
2A) Q1/Q3
2 6 6 6
6 6
V 0.4 1
V 0.6 | |
D G G SG
tp OV SG
V V V V
V V V
= = ⇒ − =
= + =
V 0.2
V 2 . 0 4 . 0
1
1 2 2 2

= ≥ − = − =
S
OV S S D DS
V
V V V V V
2B) Q2/Q4
V 6 . 0 2 . 0 ≤ ≤ −
CM
V ⇒ ≤ − ≤ − ⇒ V 0.2 0.6 .8 0
CM
V
F. Najmabadi, ECE102, Fall 2012 (36/37)
c) Find the differential gain (λ = 0.2 V
-1
):
A/V 10 2
2 . 0
10 2 . 0 2 2
3
3
1
1
1 2

× =
× ×
= = =
OV
D
m m
V
I
g g
k 25
10 2 . 0 2 . 0
1 1
3
1
1 2
=
× ×
= = =

D
o o
I
r r
λ
A/V 10 2
2 . 0
10 2 . 0 2 2
3
3
6
6
6

× =
× ×
= =
OV
D
m
V
I
g
k 25
10 2 . 0 2 . 0
1 1
3
6
6
=
× ×
= =

D
o
I
r
λ
k 25
10 2 . 0 2 . 0
1 1
3
3
3 4
=
× ×
= = =

D
o o
I
r r
λ
k 5 . 12
10 4 . 0 2 . 0
1 1
3
5
5
=
× ×
= =

D
o
I
r
λ
mA 2 . 0
6 4 3 2 1
= = = = =
D D D D D
I I I I I
mA 4 . 0
2 1 5
= + =
D D D
I I I
mA 2 . 0
7 6
= =
D D
I I
k 25
10 2 . 0 2 . 0
1 1
3
7
7
=
× ×
= =

D
o
I
r
λ
F. Najmabadi, ECE102, Fall 2012 (37/37)
Q6: PMOS CS amplifier
(2
nd
stage)
∞ =
= × − =
− =

i2
3
7 6 6
R
25 5k) 2 || k 25 ( 10 2
) || (
x
o
o o m
x
o
v
v
r r g
v
v
Q1 & Q2: NMOS Differential
amplifier with single-ended
output (1
st
stage)
25 5k) 2 || k 25 ( 10 2
) || || (
3
3 1 1
= × − =
− =

d
x
L o o m
d
x
v
v
R r r g
v
v
625 25 25 = × = × = =
d
x
x
o
d
o
d
v
v
v
v
v
v
A
v
x