Design of a Space Image Processing System
Robert A. Hillman email@example.com Department of Electrical and Computer Engineering University of Alabama in Huntsville Huntsville, AL 35899
Mark W. Maier firstname.lastname@example.org Department of Electrical and Computer Engineering University of Alabama In Huntsville Huntsville, AL 35899
As part of the SEDSAT-1 project we have designed SEASIS (SEDS Earth Atmospheric and Space Imaging System), an image processing computer system for small satellites . Our design is based on the Transputer chip and features 128 Megabytes of EDAC (Error Detection and Correction) DRAM, redundant video digitizers, and an option for an advanced signal processor. These features are contained on a 13 inch by 12 inch board designed for the thermal and radiation environment of a small satellite. This paper reviews the history and features of the design, including choice of processors, design of an error-correcting mass memory system, signal processor options, power control features, CCD Camera Control Circuitry, and physical structuring for thermal and radiation characteristics. The design has been manufactured in a flight printed circuit board configuration and is undergoing environmental qualification before launch on SEDSAT-1 in July of 1998.
SEDSAT-1, signifying Students for the Exploration and Development of Space Satellite number one, is being developed at the University of Alabama in Huntsville. The SEDSAT-1 project has grown from two students and their mentors to an international project funded by NASA, DARPA, and major corporations. SEDSAT-1 will have significant impact on space education, amateur radio communications, and space utilization. SEDSAT-1 is scheduled for launch on a Delta II in mid-1998, as a secondary payload on the JPL DS-1 mission. On-orbit, SEDSAT-1 will be a unique resource for education and research.
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Figure 1. External view of SEDSAT-1
Drawing by John Bollich, UAH
The structural frame of the satellite is approximately 13.5 inch cube, with solar cells on 5 of the six sides, and a marman clamp on the 6th side for interfacing to the deltaII (see figure 1). Also shown are the transponder antenna’s and the PAL (Panoramic Annular Lens) - one of the two lens systems used on SEDSAT. In its orbital configuration, the main objectives of the satellite are: 1. To provide multi-spectral remote sensing to the broadest possible community by use of SEASIS (SEDS Earth Atmospheric Imaging System) - the optics system of SEDSAT-1. The two cameras will collect in narrow wave bands (using selected filters) to coordinate with ground based observations across the U.S. Unlike other remote sensing systems, the data will be broadly accessible because will be
entirely public domain, and because its communication system will be integrated into the World-Wide-Web. 2. Serve as a development platform for advanced microsatellite position determination and control algorithms. The satellite will demonstrate a unique attitude determination system and new technology in active microsatellite control. Provide the amateur radio community with digital packet store-and-forward and analog repeater systems by use of the Mode-L Transponder, which has an uplink of 9600 baud, and downlink of 9600 or 57,600. Generate new data on the space performance of NiMh batteries, solar cells, and advanced electronic components.
Many design constraints were considered before finalizing on the SEASIS design. Table 1 Shows general information on processor performance and features. The main objective of SEASIS is to digitize from two CCD cameras, one which is fully calibrated. Also, select one of 12 filters from each, and control camera configurations to maximize dynamic range. Real-time video data compression is possible with the addition of the three Analog Devices SHARC ADSP-21062 chips later discussed. Mass RAM is included to store large amounts of images - since the downlink on the SEDSAT is only at 9600 and 57,600 bps. Processor computing capabilities are shown in Table 1.
Processors T805-20 3 Analog Devices SHARC DSP Clock 20 Mhz 40 Mhz MFLOPS 3.3 Peak 120 Peak/each 360 Total MIPS 20 SRAM 2 Mbyte SMI 512Kbyte onchip SRAM (1.5Mbyte Total) DRAM 128 Mbyte N/A Total System Power (Watts) 0.7 to 5 Watts 3 Watts Each
Table 1. SEASIS Processor Specifications
Originally, DARPA donated an MCM (the SCC-100) with 3 ZORAN DSP’s, a T805 Transputer, and 2 Mbytes of internal SRAM. Unfortunately, the bus design for the ZORAN’s would be a great bandwidth constraint (lowering the MFLOP rating of the MCM to a fraction of it’s 100Mflops peak), and the system was not designed for our purpose. Also, the SCC-100 consumed over 5 watts of power, and was the only MCM of it’s kind - making it almost impossible to have a ground system functionally identical. For this reason, we chose to re-design a lower power, more effective solution. The heart of the SEASIS board is the 32 bit T805 processor by INMOS running at 20 Mhz. The processor operates under ½ watt under normal operations, has multitasking capabilities built-in, and has a long history of use in space applications. For
memory, code and data both reside inside the 128MByte EDAC protected DRAM’s linearly addressed memory space without the need for bank switching. Internal to the T805 are 4 high speed serial links - one running to the CDS board (Command Data System board on the SEDSAT-1 which communicates to the ground station) and the other three to the DSP’s (see Figure 2). These links make the communications hardware easier to implement in the system since different sections can be powered off. The three SHARC chips can be powered on separately under the T805 software control, on an external expansion board. Each SHARC has access to one of the T805’s 20MBit links for communications and bootup code. Once a SHARC chip is powered on, it immediately accepts code over the link from the T805, and runs the code once the end is reached. The SEASIS board can be reset from the CDS board under software control. Upon power-up of the SEASIS board, a power-on reset circuit gives maximum reset timings for all circuitry. After reset, the T805 polls the transputer links for bootup code. One of the links is connected to the CDS - allowing the CDS board to send bootup code to SEASIS over the link, placing it in EDAC protected memory and then run once complete.
Video In Video In
Digitizer and I/O Power
NTSC Digitizer 1
NTSC Digitizer 2
I/O Devices and Camera Control Logic
20Mbit Data Links To DSP’s and to CDS
Shared Memory Interface
Figure 2. SEASIS Processor Board Block Diagram
32 MB EDAC SIMM 32 MB EDAC SIMM 32 MB EDAC SIMM 32 MB EDAC SIMM
EDAC Mass Memory Design
Mass memory consists of 128 Mbytes of EDAC (Error Detection and Correction) DRAM (Dynamic RAM) comprising of 4 32 Mbyte SIMM’s. DRAM requires
refreshing (accesses to every row at intervals no greater than 32 ms) - and this is incorporated into the design external to the Transputer for robustness, even though the T805 does have some limited refreshing capabilities. The refresh design has no memory mapped registers, when the power is applied, the DRAM’s are guaranteed refreshed until powered down. Also, by using a CBR refresh (CAS before RAS) cycle, power consumption is minimized and the address bus can remain tri-stated. When refreshing 128 Mbytes, interleaving was chosen to minimize effects on the power bus. Instead of refreshing all 4 SIMM’s (both sides) at once, they are refreshed separately and distributed evenly (8 CBR cycles during each refresh interval) throughout the 32 ms. Each SIMM is 36 Bits wide (4 for parity) and 32 for data bits - along with 4 check bits for each byte. Each byte has a separate EDAC chip - correcting single bit errors in EACH byte (and some double bit errors) - while detecting single and double bit errors. A memory mapped register can be read by the Transputer to determine when single and double bit errors occur - to map error locations and generate SEU statistics. Using a flow-thru EDAC chip such as the IDT 39C465, the SMI SRAM can be EDAC protected during digitizing, as well as running code. Also, instead of using the IBM EDAC DRAM’s for the mass RAM, the 32 Bit IDT EDAC chip has been designed to do read-modify-write cycle on SRAM’s and could be modified for standard COTS JEDEC 72 Pin DRAM’s. The T805 can vary it’s bus cycle write size, making it more difficult to design a 32 bit EDAC memory system that generates code words for the full 32 bits. Because of this, wait states would need to be added, or faster memory would need to be selected. For this reason, SEDSAT chose to use the IBM EDAC byte-wide DRAM’s which generate check bits for each byte, rather than for each word - eliminating the need for a read-modify-write cycle during a partial CPU write.
Video Digitizer Design
Incorporated in the SEASIS board are two NTSC video digitizers which can sample at speeds up to 20 Mhz. In our case, at 768x484 resolution, we need to sample at the pixel clock rate of the CCD’s (14.31818 Mhz) which is far within the specifications. Reference digitizing voltages can be set from software control, as well as the analog multiplexer choosing between one of the four input video channels, allowing for a total of 8 video inputs together, or redundant digitizers. To digitize, the transputer flips a bit in a memory mapped register, causing the Digitizer to find the beginning of the image. Then, the digitizer starts digitizing into the SMI (Shared Memory Interface) SRAM. Once complete, the digitizer generates an exception (interrupt) for the T805, signaling that the digitizing is complete. Up to four clocks can be software selected (CCD clock, fixed oscillator, software clock, No clock). Selecting no clock will lower power consumption when the digitizers are powered on but not digitizing.
Digital Signal Processing Capabilities
Three SHARC DSP’s were chosen for the ability of having redundant computations on each, storing their result in the internal SRAM on-chip (512kbytes each). High speed links connect each DSP together, with speeds up to 240MByte/second using the internal DMA capabilities. Once each DSP has computed the result, each one will transfer their result to the T805, and the T805 will compare their results to see if any SEU (Single Event Upsets) occurred, and in which DSP. Another option is to have all three DSP’s operating on different sections of the image, and to have it computed twice for comparison on the T805. If the results are not the same, the T805 will compute what isn’t consistent again on the 3 DSP’s until it finds a match. Since all software is uploaded to the SHARC chip upon power-on, any scenario can be programmed to ensure data integrity.
Power Control Features
SEASIS can be powered on in a base configuration with all mass memory refreshed in under 1 watt. The CDS board on SEDSAT can power off SEASIS, or send a command to power different sections of SEASIS down when it detects a low power state of the batteries on the satellite. Configuration possibilities and power consumption are shown in Table 2. Configuration Minimum Running Digitizing Cameras Stepper Motor Systems Active Power (W) Mass RAM, CPU Idle 0.7 Mass RAM, CPU active 100% 3.5 Mass RAM, CPU, all I/O and 5.0 Digitizers Stand-alone, each 3.0 Single Stepper, single Phase energized 5.6 Table 2. Power Control Configurations
SEASIS always starts up in the base configuration with only the critical memory and logic system enabled. All camera control logic, stepper motor control, and the digitizers can be powered up and down under software control. The cameras, auto-iris lenses, and stepper motors power can also be controlled independently to minimize total power consumption.
Image Control Logic
SEASIS has two cameras mounted perpendicular on the experimental mounting plate (see Figure 3). One lens is a PAL (Panoramic Annular Lens), and the other is a telephoto with a field of view of approximately 10 degrees. The unique capability of the PAL allows us to see 360 degrees around the lens, which will overlap the image from the telephoto.
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Figure 3. SEDSAT Experimental Mounting Plate
Drawing by John Bollich, UAH
The PAL CCD camera is flown in fully automatic mode - allowing the camera to select shutter speed, iris setting, and gain automatically. Only the telephoto camera is required to be calibratable. For this reason, and because we aren’t able to read the settings made in automatic mode from the lens and iris, we generate a calibratable system by setting the options on the iris and lens under software control. A list of options and settings is in Table 3.
System Lens Camera Stepper Motor Filter Wheel
Options Iris Control Shutter Speed Gain Control Phase A,B,C,D 12 Filters
Possible Settings 14 Bit D/A for 16,384 settings 200 PWM Electronic Speeds AGC/Fixed/Manual Pulsed to select one of 12 filters
Optical encoders on wheel which can be read to determine filter number Table 3. Image Control Settings on SEASIS
Iris control can be controlled by means of outputting an analog voltage into the auto-iris lens from the D/A converter. This will allow variation in intensity under software control, however, makes the system unable to be calibrated. Because of this, the iris will be flown on SEDSAT fixed completely open on the lens which requires calibration, and only the gain and shutter speed will be configurable (as well as a selection of neutral density filters), which will give us enough dynamic range. Our second CCD camera will be flown completely automatically - CCD camera and auto-iris lens since we have no need to calibrate.
SEASIS is powered by Interpoint DC/DC converters, with maximum output power of 15 to 30 Watts, and efficiencies of around 75%. The DC/DC converters are mounted on the SEDSAT experiment mounting plate, located near the center of the satellite. Our simulations and tests have shown this to be the coldest location in the satellite, and an ideal location for our DC/DC converters. Three DC/DC converters are used, one for cameras (12VDC), one for SEASIS main power (5VDC), and one for stepper motor power (28VDC). All derive their power directly from the main satellite power bus. PCB’s have ground planes located on the top and bottom of all boards in the satellite, secured to the frame with wedge-locks. Our simulations and tests have demonstrated that this is very effective at distributing heat evenly especially when making good thermal contact to the body of the components (using a thermally conductive, electrically non-conductive strip). Soldering was very tedious when soldering pins to ground, so better heat relief was added on the solder side.
Almost all of the hardware on SEASIS are commercial parts with radiation information available (see Table 4). One of the main exceptions are the A/D video chips chosen, which have no radiation information (Brooktree BT252). Because of the internal 4 channel mux, and programmable voltage references, we chose to keep the BT252 in the SEASIS design since our orbit will give us a minimal radiation exposure level.
However, we have redundant electronics for the video digitizers, and can have components RAD-COAT’ed (© Space Electronics, Inc.) to increase their life expectency to over 100krad. Also, the HS9008-RH could be used in a future design where longduration exposure at high doses exist in place of the BT252. Part Number T805-20 HM628512 74 and 54 Series MTR2805S MTR2812S 10.00Mhz BT252 HS9008-RH* Description Latch up Threshold MeV/
Inmos 20Mhz Transputer 36 512Kx8 SMI SRAM > 90 Discrete Logic >100 Interpoint 28-5V DC/DC >50 Interpoint 28-12V DC/DC >50 Q-Tech Rad-Hard Oscillator >100 Brooktree A/D No Information Available Harris Rad-Hard A/D >300 Table 4. Radiation Specifications *Feasible replacement part for BT252 on new design. **Radiation information from http://www.dasiac.com, and Interpoint for DC/DC converters.
The SEASIS design incorporates low cost, low power, and high performance. In our planned low earth orbit, the life expectancy is 3 years. Alternative chips and packaging methods can increase total dose survival rate on SEASIS to well over 100krad, but was not feasible (due to funding), nor required for our mission. Future designs will include a more modern microprocessor - the T805 is being phased out. Possible replacements include the 486 or Pentium microprocessors with low power modes, and a VME bus interface. Also, new digital camera technologies could allow for direct digital output instead of NTSC, simplifying the image capture hardware. These options will be more feasible once the technology is more mature, and a longer flight history is developed.