Circuits for Ultralow Supply
Voltages
Peter Kinget
COLUMBIA UNIVERSITY
IN THE CITY OF NEW YORK
© Peter Kinget
12
Thick oxide V
DD
Thin oxide V
DD
Thin oxide V
T
Technology node [nm]
[ITRS'05]
–O– High Perf.
–!– Low Standby
–V– Low Power
Nano CMOS : Supply Voltage
© Peter Kinget
13
Ultralow Voltage Analog/RF
• What analog/RF is possible in core nanoscale
digital?
• Scavenging applications
– E.g., single solar cell V
DD
0.40.5V
• Ultralow energy digital systems
– Optimal DV
DD
is 0.30.5V
– Analog support functions for digital
• SOC designs
– Analog/RF powered from onchip LDO
– AV
DD
is 0.2V below DV
DD
• Interesting research…
– Explore boundaries, develop design techniques
© Peter Kinget
14
MOST Biasing: CS or VCCS
• Transconductor or Current Source
V
DS
> 0.15 V (for V
GS
V
T
! 0.2 V)
• Moderate to Strong Inversion
(V
GS
V
T
) ! 0.15 V & V
T
= 0.15V ! V
GS
= 0.3V
Weak
Inversion
Strong
Inversion
5!
T
© Peter Kinget
15
UltraLV Challenges in OTAs
CMFB
V
in+
V
in
V
out+
V
out
V
casp
V
casp
V
casn
V
casn
0.5V
0.25V 0.25V
"
" "
"
"
"
0.15V
0.15V 0.15V
0.15V
0.15V
0.3V
0.15V
0.15V
0.3V
© Peter Kinget
16
Device Level
• RSCE
• Forward BodyBias
V
T
! as L"
deep nwell
NMOS
V
DD
V
BS
=0.5V "V
T
~ 50mV
© Peter Kinget
17
0.5 V Gateinput OTA stage
V
in+
V
in
V
out+
V
out
V
bn
V
NR
0.5 V
© Peter Kinget
18
0.5 V OTA in 0.18um CMOS
© Peter Kinget
19
Onchip biasing circuits
V
bn
generating circuit
Level shift biasing circuit
(Simplified OTA)
© Peter Kinget
20
Error amplifier for biasing
• 20 kHz GBW for 1 pF load
• 2 !A current
• Controlled body voltage
sets the amplifier threshold
V
in
V
out
V
o
u
t
[
V
]
V
in
[V]
© Peter Kinget
21
OTA DC transfer characteristics
and V
NR
generation
V
NR
generating circuit
Replica of OTA
stage 1
Input differential voltage [mV]
O
u
t
p
u
t
d
i
f
f
v
o
l
t
a
g
e
[
V
]
Increasing V
NR
© Peter Kinget
22
Open loop performance (meas.)
G
a
i
n
[
d
B
]
42 dB
GBW: 10 MHz
C
L
= 10 pF (diff.)
R
L
= 50 k"
I
DD
= 150 µA
62 dB 350 mV; automatic bias
Frequency [Hz]
© Peter Kinget
23
Lowvoltage tunable integrator
0.25 V
0.25 V
0.4 V
+

V
in
V
out
+

V
DD
V
DD
© Peter Kinget
24
0.5 V Fully integrated 5th order LPF
• Operation at 0.45 V to 0.6 V
• 1.1 mW power dissipation
• 57 dB dynamic range
Filter
PLL
Biasing circuits
OTAs
1mm
1
m
m
Frequency [kHz]
G
a
i
n
[
d
B
]
[Chatterjee, ISSCC05,
JSSC05]
© Peter Kinget
25
Performance summary at 27C
72 72 85 104 VCO feedthru @280kHz [!V rms]
69.0
150.5
84.5
148.0
88.0
154.5
96.5
153.0
Tuning range [kHz] V
tune
= V
DD
V
tune
= 0.0 V
58 57 57 55 Dynamic range [dB]
5 3 5 3 Outofband IIP
3
[dBV]
3 3 3 5 Inband IIP
3
[dBV]
50 50 50 50 Input [mV rms] (100kHz / 1% THD)
65 68 74 87 Noise [!V rms]
4.3 3.3 2.2 1.5 Total current [mA]
135.0 135.0 135.0 135.0 3 dB cutoff frequency [kHz]
0.60 0.55 0.50 0.45 V
DD
[V]
Functionality tested from 5C to 85C at 0.5 V
• Measured CMRR (10 kHz common mode tone): 65 dB
• Measured PSRR (10 kHz tone on power supply): 43 dB
© Peter Kinget
26
0.5V 1Msps 60dB T/H amplifier
• 0.25!m CMOS
• V
t
= 0.6V
• 60dB SNDR
• 1Msps
• 0.6mA at 0.5V
Trackandholds
Biasing circuits
• True low voltage
• No clk boosting
• [Chatterjee, VLSI 06, JSSC07]
Input amplitude [dBV]
S
N
D
R
© Peter Kinget
27
0.5V Differential Track and Hold
• Gateinput OTA used.
• Track phase during #
1
,
hold phase during #
2
.
• During track phase, pole
and zero cancel out to
enable fast response.
• pMOS switches have V
T
of about 0.5V.
© Peter Kinget
28
Track mode operation
• Resistors to 0.5V
maintain required
OTA input CM
voltage of 0.4V.
• To enable better
switching, both gate
and body of the
switch are used.
• No voltage swing on
either side of the
switches.
© Peter Kinget
29
Hold mode operation
• Gate and body of the
switch used for
better switching.
• No signal swing on
both sides of the
switches.
• OTA input voltages
held constant.
© Peter Kinget
30
Measured SNDR
Input differential rms [dBV]
S
N
D
R
[
d
B
]
© Peter Kinget
31
Measured performance
3.9MHz Track mode bandwidth
0.8mV Pedestal on diff. output
7.6"V/"V Hold mode droop rate on diff. output
57dB Peak SNDR f
IN
=495kHz; V
in,diff
=100mV
RMS
60dB Peak SNDR f
IN
=50kHz; V
in,diff
=178mV
RMS
188"V
RMS
Diff. input refd. integrated noise
1Msps Sampling rate
600"A Current consumption
0.5V Power supply
© Peter Kinget
32
0.5 V 74 dB SNDR 25kHz !" Modulator
• 0.18 !m CMOS
• MIM caps
• Triplewell devices
• Highres resistors
• Bodyinput, gate
clocked logic
• Returntoopen
feedback
• [Pun, Chatterjee,
Kinget, ISSCC 06]
© Peter Kinget
33
Digital
Output
Q
Q
+
Vin

#
DAC
3
rd
order CT !" Modulator
Using Active RC integrators
#
DAC
© Peter Kinget
34
Digital
Output
Q
Q
+
Vin

#
DAC
3
rd
order CT !" Modulator
Using Active RC integrators
#
DAC
Using BodyInput OTAs (2stages)
V
in+
V
in
V
out+
V
out
0.5 V
© Peter Kinget
35
Digital
Output
Q
Q
+
Vin

#
DAC
3
rd
order CT !" Modulator
Using Active RC integrators
#
DAC
Latch PreAmp
VDD
+Vin
Vin
Q
!
!
!
!
!
!
Q
M1 M2
M5
M6
M4 M3
M8
M7
Gateclocked Bodyinput Comparator
© Peter Kinget
36
Digital
Output
Q
Q
+
Vin

#
DAC
3
rd
order CT !" Modulator
Using Active RC integrators
#
DAC
© Peter Kinget
37
RZ Challenge: Switches at V
DD
/2
0.25 V
0.25 V
0.25 V
0.5V 0V
RZ DAC_n
0.5V 0V
RZ DAC_p
Ri
C
C Rdac
Rdac
VCM
!
RZ
D0 D1
VCM
!
RZ
D1 D0
+
Vin
0.25 V
Switch Conductance
0.5V
0V
Ts
Vdac
t
v
2
v
1
V
cm,ota
V
1
V
2
© Peter Kinget
38
Ts
t
D0
Ts
t
Q
Ts
t
D1
Solution: ReturntoOpen
v
2
0.5V
0V
Ts
Vdac
t
v
2
v
1
V
cm,ota
v
1
When RZ:
(Q=1)
Ri
C
C Rdac
Rdac
0.5V 0V
D0 D1
0.5V 0V
D1 D0
RTO DAC_n
RTO DAC_p
+
Vin
RZ
Problem
switches
removed
0.25 V
© Peter Kinget
39
Ts
t
D0
Ts
t
Q
Ts
t
D1
Solution: ReturntoOpen
v
2
0.5V
0V
Ts
Vdac
t
v
2
v
1
V
cm,ota
v
1
When RZ:
(Q=1)
Ri
C
C Rdac
Rdac
0.5V 0V
D0 D1
0.5V 0V
D1 D0
RTO DAC_n
RTO DAC_p
+
Vin
RZ
V
REFN
V
REFP
"
DAC
Q
V
DACp
"
DAC
"
DAC
Problem
switches
removed
© Peter Kinget
40
Returntoopen CT SDM
BW = 25kHz, fs = 3.2MHz,
Vin,max = 1Vppdiff.
Split Returntoopen DAC
Only switches to VDD or VSS
Digital
Output
R2ap
(88k$)
C2p
(7.8pF)
R2an
(88k$)
C2n
(7.8pF)
R2bn
(145k$)
R2bp
(145k$)
R3ap
(66k$)
C3p
(5.2pF)
R3an
(66k$)
C3n
(5.2pF)
R3bn
(93k$)
R3bp
(93k$)
!
Q
Q
!
DAC
!
DAC
!
DAC
!
DAC
R1ap
(275k$)
C1p
(31.25pF)
R1an
(275k$)
C1n
(31.25pF)
R1bn
(86k$)
R1bp
(86k$)
+
Vin

!
DAC
!
DAC
© Peter Kinget
41
Performance Summary at 25°C
0.6 mm
2
Active die area
370 µW
300 µW
70 µW
0.8V 0.5V 0.45V Supply Voltage
76 dB
74 dB
0.18 µm CMOS
(standard V
T
, triplewell, MIM, and HiRes Poly)
76 dB
71 dB
1 Vppdiff.
3.2 MHz / 64
25 kHz
1bit, 3rd order, continuoustime
74 dB
74 dB
Technology
Power consumption (total)
Sigma Delta Modulator
Output buffers
SNR @ Vin = 1Vppdiff.
SNDR @ Vin = 1Vppdiff.
Input range
Sampling frequency / OSR
Signal bandwidth
Modulator type
© Peter Kinget
46
Recent Work in 90nm CMOS
0.65/0.5V 2.42.6GHz
Fractional N
Freq. Synthesizer
0.5V 2.4GHz SlidingIF
Receiver + I/Q Baseband
0.5V 10Msps 8bit
Pipelined ADC
© Peter Kinget
47
0.65V/0.5V 2.42.6GHz
FractionalN Synthesizer
• Swings on all VCO nodes are
kept within the supply rails for
reliability.
• Forward body bias to enhance
the divider speed.
• FractionalN DSM dithering
shifted to later divider stages to
prevent noise injection into
forward biased body.
• Staggered clock to prevent
jittering caused by simultaneous
switching.
• 90nm CMOS
• [S. Yu & P. Kinget, ISSC07]
© Peter Kinget
49
Performance Summary
P
h
a
s
e
n
o
i
s
e
(
d
B
c
/
H
z
)
Frequency (MHz)
C
o
n
t
r
o
l
w
o
r
d
–!– @10kHz
–"– @1MHz
–#– @3MHz
$ ctrl word
• AVDD 0.5V  2.5mW
• DVDD 0.65V  3.5mW
• 0.14mm
2
 90nm CMOS
• RVT devices
• 2.42.6GHz
• Phase noise:
120dBc/Hz @ 3MHz
• Spurs: 52dBc
© Peter Kinget
50
A 0.5V 8bit 10Msps Pipelined ADC
in 90nm CMOS
• No internal voltage or clock boosting
• Regular devices
• Cascaded sampling technique to
reduce the channel leakage of the
switches
• 1.5bit/stage (remark: stages identical, stages
scaling not exploited)
• Frontend S/H amplifier eliminated by
with an S/H for the subADC.
• 0.5V OTAs with local CMFB
• 90nm CMOS
• [J. Shen & P. Kinget, VLSI07]
© Peter Kinget
53
A 0.5V 2.4GHz Receiver
• ISM band applications
• Sliding IF topology
• LNA, Mixers, VGA +
on chip RF, IF & BB
filtering
[Stanic, Balankutty,
Kinget, Tsividis,
RFIC07]
© Peter Kinget
58
0.5V Analog Roadmap
2004 2005 2006
Bodyinput
OTA
Gateinput
OTA & Biasing
0.5V Varactor
10b 1Ms
THA
135kHz LPF
+ Tuning
CT 74dB 25kHz
#$ A/D
2007
DT $# ADC
Basic blocks
C
o
m
p
l
e
x
i
t
y
Comparators
2.4GHz RCV
2.4GHz Synth.
8b 10Ms A/D
90nm
180nm
250nm
900MHz RF
Frontend
© Peter Kinget
59
Where do we go from here…
• Other nanoscale challenges:
– Gate & subthreshold (OFF) leakage,
– Smaller g
m
/g
o
,
– Reduced body effect.
• Opportunities
– Device speed significantly improves:
• Scale device operating points for larger (g
m
/I
D
),
– FinFETs, dual gate devices, ….
– Calibrate using abundant digital gates.
• But, some fundamental limitations are
against us…
© Peter Kinget
60
!
P " 8 kT f SNR
2
!
v
2
n,RMS
=
kT
C
!
SNR =
V
RMS
v
n,RMS
2
!
I
DC
= 2 f C 2V
RMS
Power Dissipation Limits
!
P " 24 C
ox
A
VT
2
f Acc
2
!
"
2
(V
os
) =
C
ox
A
VT
2
C
!
Acc =
V
RMS
3"(V
os
)
!
I
DC
= 2 f C 2V
RMS
• Noise limited circuits [Vittoz90]:
• Mismatch limited circuits [Kinget96]:
!
V
DD
= 2 2V
RMS
ideal class B
© Peter Kinget
61
Low Voltage Power Penalty
• Finite V
DSsat
:
V
DSsat
!
Penalty factor =1+
2V
DSsat
(V
DD
"2V
DSsat
)
!
V
DD
= 2 2V
RMS
+ 2V
DSsat
© Peter Kinget
62
LV Challenge: Interfaces
50#
CKT
0.5  1.0V
4dBm (2.5mW) @ 1.0Vpp
2dBm (0.625mW) @ 0.5Vpp
Z
Transf.
Filt./Z
Match
CKT
50#
out
in
© Peter Kinget
63
Ultra Low Voltage Analog Design
Techniques
• Device Level:
– Use body terminal for bias control or signal,
– Use RSCE, optimize L to reduce V
T
.
• Building Block Level:
– Eliminate transistor stacks,
– Use LCMFB, CMFF & Neg. G.
• Functional Level:
– Revise signaling & architecture,
– New tuning & biasing strategies.
• Demonstrated in 0.5V analog & RF building
blocks & systems:
– filters, THA, ADCs, RF frontends, freq. synthesizers,
– in 0.18um CMOS (V
T
=V
DD
) & 90nm CMOS.
© Peter Kinget
64
Selection of Recent Publications
0.5V Analog/RF Integrated Circuits:
• S. Chatterjee, K.P. Pun, N. Stanic, Y. Tsividis and P. Kinget, “Analog Circuit Design Techniques at 0.5V”, Springer, in press, 2007.
• J. Shen, and P. Kinget, "A 0.5V 8bit 10Msps Pipelined ADC in 90nm CMOS," IEEE Symposium on VLSI circuits, accepted, June 2007.
• N. Stanic, A. Balankutty, P. Kinget, and Y. Tsividis,"A 0.5 V Receiver in 90 nm CMOS for 2.4GHz Applications," IEEE Radio Frequency
Integrated Circuits Conference (RFIC), accepted, June 2007.
• S.A. Yu and P. Kinget, "A 0.65V 2.5GHz FractionalN Frequency Synthesizer in 90nm CMOS" in Digest of Technical Papers IEEE
International SolidState Circuits Conference (ISSCC), Feb. 2007.
• S. Chatterjee, and P. Kinget, "A 0.5V 1Msps TrackandHold Circuit with 60db SNDR," IEEE Journal of SolidState Circuits, vol. 42, no.
4, pp. 722729, Apr. 2007.
• K.P. Pun, S. Chatterjee, and P. Kinget, "A 0.5V 74dB SNDR 25kHz ContinuousTime DeltaSigma Modulator with a ReturntoOpen
DAC," IEEE Journal of SolidState Circuits, Vol. 42, no 3, pp. 496507, March 2007.
• N. Stanic, P. Kinget and Y. Tsividis, “A 0.5 V 900 MHz Receiver Front End”, IEEE Symposium on VLSI Circuits, June 2006.
• S. Chatterjee, Y. Tsividis and P. Kinget, "0.5 V Analog Circuit Techniques and Their Application in OTA and Filter Design," IEEE Journal of
SolidState Circuits, vol. 40, no 12, pp. 2373  2387, Dec. 2005.
RF Integrated Oscillators:
• B. Soltanian, H. Ainspan, W. Rhee, D. Friedman and P. Kinget, "An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with
Dynamic Common Mode Feedback", IEEE Journal of SolidState Circuits, in press, 2007.
• B. Soltanian, and P. Kinget, "A Low Phase Noise Quadrature LC VCO Using Capacitive CommonSource Coupling", European SolidState
Circuits Conference, pp. 436439, Sept. 2006
• F. Zhang and P. Kinget, "Design of Components and Circuits Underneath Integrated Inductors" IEEE Journal of SolidState Circuits, vol.
41, no. 10, pp. 22652271, Oct. 2006.
• B. Soltanian and P. Kinget, “AMFM Conversion by the Active Devices in MOS LCVCOs and its Effect on the Optimal Amplitude”, IEEE
RFIC Symposium, June 2006.
• B. Soltanian and P. Kinget, " Tail CurrentShaping to Improve Phase Noise in LC Voltage Controlled Oscillators " IEEE Journal of Solid
State Circuits, vol. 41, no. 8, pp. 17921802, Aug. 2006.
Ultrawideband Pulse Radio:
• TienLing Hsieh, P. Kinget, Ranjit Gharpurey, "An Approach to Interference Detection for Ultra Wideband Radio Systems", Fifth IEEE
Dallas Circuits and Systems Workshop, pp. 9194, Oct. 2006.
• F. Zhang and P. Kinget, "Low Power Programmable Gain CMOS Distributed LNA" IEEE Journal of SolidState Circuits, vol. 41, no 6, pp.
10331043, June 2006.
• A. Jha, R. Gharpurey and P. Kinget, "QuadratureDAC based pulse generation for UWB pulse radio transceivers" in Digest of Technical
Papers IEEE International Symposium on Circuits and Systems, pp. 666669, May 2006.
Injectionlocking:
• G. Gangasani and P. Kinget, "A timedomain model for predicting the injection locking bandwidth of nonharmonic oscillators" in
Transactions on Circuits and Systems II, pp. 10351038, Oct. 2006.
• G. Gangasani and P. Kinget, "InjectionLock Dynamics in NonHarmonic Oscillators" in Digest of Technical Papers IEEE International
Symposium on Circuits and Systems, pp. 16751678, May 2006.
Device Mismatch:
• P. Kinget, "Device mismatch and Tradeoffs in the Design of Analog Circuits", IEEE Journal of SolidState Circuits, vol. 40, no 6, pp. 1212
1224, June 2005.
© Peter Kinget
65
Acknowledgments
• Collaborators:
– Y. Tsividis (Columbia), K. P. Pun (City Univ. Hong
Kong), S. Chatterjee (now IIT Delhi), B. Soltanian
(now LSI)
– A. Balankutty, Y. Feng, A. Jha, J. Shen, N. Stanic,
S. Yu, F. Zhang.
• Analog Devices, Bell Labs, Intel, NSF,
Realtek, Silicon Labs, SRC for financial
support.
• Europractice, Philips (now NXP) and UMC for
fabrication support.
Thank you for your attention
Any Questions, contact:
kinget@ee.columbia.edu
http://www.ee.columbia.edu/~kinget