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Presented by

K.Kondal ID:kondal_kolipaka@yahoo.com

N.Chandra Mouli ID:mouli_n_chandu@yahoo.com

R.Srikanth ID:rai_srikanth@yahoo.com

CSE IV/IV

MAHABUBABAD, WARANGAL .
ABSTRACT

The level of integration possible on Silicon chip has been rising very fast. Processors
with one to ten million transistors are common in complex digital design. VLSI ICs
offer advantage of saving space, improved reliability, and better performance and are
inexpensive as compared to discrete implementation using MSL.

The VLSI electronics presents a challenge, not only to those involved


in the development of fabrication technology, but also to computer scientists and
architects. With the importance of the area and the expanding opportunities in the
realm of VLSI design, process technology , embedded systems and applications in the
areas of WAP ,Bluetooth and GSM one can feel that a lot more is achieved in the
discipline of VLSI technology.

The rate of systems innovating this remarkable technology need no


longer be limited by the perceptions of a handful of semiconductor companies and
large computer manufactures. New metaphors for computation, new design
methodologies, and an abundance of new application areas are arising within the
universities, within many system firms and within a multitude of new small
enterprise.
FUNDAMENTALS AND BACKGROUND OF VLSI

INTRODUCTION
The structural complexity of digital integrated circuits (usually expressed by the
number of transistors per chip) has been increasing at an exponential rate over the last
thirty years. This phenomenal growth rate has been sustained primarily by the
constant advances in manufacturing technology, as well as by the increasing need for
integration more complex functions on chip. Answering the demands of the rapidly
increasing chip complexity has created significant challenges in many areas;
practically
Hundreds of team members are involved in the development of typical VLSI product,
including the development of technology, computer-aided design (CAD) tools, chip
design, fabrication, packaging, testing and reliably qualification. The efficient
organization of these efforts under a well-structured system design methodology is
essential for the development of economically viable VLSI products, in a timely
manner.

EVOLUTION OF COMPUTER AIDED DIGITAL DESIGN:


Digital circuit’s designs have evolved rapidly over the last 25 years. The
earliest digital circuits were designed with vacuum tubes and transistors. Integrated
circuits were logic gates were placed on single chip. Then scale of integration came in
to the picture.
• SSI (Small Scale Integration) : the gate count was very small, about 10 gates
• MSI (Medium Scale Integration) : about 100 gates were place on single chip
• LSI (Large Scale Integration) : thousands of gates were place on single chip
When the designers tried to put thousands of gates on single chip, the design
process started getting complicated, and the felt the need to automate the process.
Computer Aided Design (CAD) techniques began to evolve. With advent of VLSI
(Very Large Scale Integration) technology, the designers could design circuits; it was
not possible to verify these circuits on breadboard. CAD techniques became critical for
the verification and design of VLSI design circuits
The basic classification of IC technology has been illustrated in the following figure.

VLSI FEATURES:
• High reliability & high performance.
• Low power dissipation
• Extremely low weight
• Low volume & minimum area.
• Low cost
• High complexity with minimum propagation delay
VLSI DESIGN STYLES:
Ics are made on a thin (a few hundred micron thick) circular Si wafer, with
each wafer holding hundreds of dies of chips. The transistors & wiring are made from
many layers built on top of one another. Several design styles can be considered for
chip implementation of specific algorithms or logic functions. Each design style has
its own merits and shortcomings, and thus a proper choice has to be made by
designers in order to provide the specified functionality at low cost and in a timely
manner.
The classification of design styles is shown in the following diagram

FULL CUSTOM DESIGN:


Using the Full-custom design style (where the geometry and the placement of
every transistor can be optimized individually) requires a longer time until design
maturity can be reached, yet the inherent flexibility of adjusting almost every aspect
of circuit allows far more opportunity for circuit performance improvement during
the design cycle. The final product typically has a high level performance and the Si
area is relatively small because of better area utilization. But this comes at a larger
cost in terms of design time.
The two types of semi custom ICs are:
• Standard cell Based ASIC (CBIC)
• Gate Array based ASIC (GA)
CBIC:
A cell based ASIC uses pre designed logic cells (AND, OR gates, MUX and
FF) known as standard cells. The standard cell areas in CBIC are built of rows of
standard cells. The Advantages of CBIC is that designer’s save time, money, reduce
risk by using a pre-designed standard cell library. The disadvantage is the expense of
buying the standard library and the time taken to design the cells.
GA:
The difference between CBIC and GA is that though both of them use pre-
designed library the transistor sizes can be changed in CBIC, not in GA
The following are the different types of GA based ASICs:
• Channeled GA
• Changeless GA
• Structured GA
• The channeled GA uses rows of cells between the channels.
• The channeled GA uses rows of unused transistors between the channels.
• The structured GA embeds the functions of CBIC and GA. But the
disadvantage is that the embedded fn. Is fixed.
Programmable ASICs:
A Programmable ASIC is a digital IC that can be programmed by the user to
implement any digital logic function. Some of the Programmable ASICs are
• FPGA
• PLDs
FPGA:
It consists of basically array of logic blocks and routing channels. The FPGA
has 3 major configurable elements:
 Configurable Logic Blocks (CLBs)
 Input/Output Blocks (IOB)
 Programmable Interconnects (PI)
FPGAs are customized by loading configuration data into the internal
Memory cells. Based on placement of logic cells they are classified into 4 categories:
 Symmetrical array
 Row based
 Hierarchical PLD
 Sea-of-gates
PLDs:
It consists of array of memory cells that can be programmed with user defined
bit pattern.
Advantages:
 Ease of design
 Design can be changed modified rapidly
 Cost is reduced

Disadvantages:
 Non utilization of complete circuit
 Increased power requirement
 Increase in size with increase in no. of input variables
The choice of particular design style for a VLSI product depends on
the Performance requirement, this technology being used, the expected lifetime of
the Product and the cost of the project.

VLSI DESIGN LANGUAGES:

HDL:
One of the drawbacks of the traditional design methods is manual translation
of design description into a set of logical equations or a schematic. This step can be
eliminated with HDL.
A Hardware Description Language (HDL) is a software programming
language used to model the intended operation of a pieces of hardware. There are two
aspects for the hardware that an HDL facilitates:
• True abstract behavior modeling
• Hardware structure modeling
There are several HDLs are in use today. The most popular ones are able,
palasm and Clup {used for less complex devices), verilog HDL and VHDL (used for
more complex devices CPLDs and FPGAs) VHDL (V stands for VHSIC which is
very high speed integrated circuit and HDL stands for Hardware Description
Language)

SYNTHESIS
“Synthesis is the process of translating a model of a hardware written in HDL to an
optimized, technology specific gate implementation.
Synthesis consists of basically 3 internal levels of translation and optimizations.
Automatic optimization occurs at each stage and is guided by the user defined
constraints.
Synthesis = translation + optimization

VLSI DESIGN FLOW:

Figure shows the sequence of steps to design an ASIC; we call this a design
flow. The steps are listed below (numbered to correspond to the labels in figure)
with a brief description of the function of each step.
 Design entry. Enter the design into as ASIC design system, either
using a Hardware Description Language (HDL) or schematic entry.
 Logic synthesis. Use an HDL (VHDL or Verilog) and a logic
synthesis tool to produce a netlist – a description of the logic cells and their
connections.
 System partitioning. Dividing a large system into ASIC – sized
pieces
 Prelayout simulation. Check to see if the design functions correctly.
 Floor planning. Arrange the blocks of the netlist on the chip.
 Placement. Decide the locations of cells in a block.
 Routing. Make the connections between cells and blocks.
 Extraction. Determine the resistance and capacitance of the
interconnect.
 Post layout simulation. Check to see the design still works with the
added loads, of the interconnect.
MOORE’S LAW
• As transistors become smaller and smaller, factors such as leakage
power, heat, and transistor variation become important. So Intel’s circuit research
department works first on control and avoidance techniques to minimize the
effects.
• The other approach is to improve computational efficiency for a higher
performance at lower power. For this, the company uses special – purpose
processor architectures that put the power where it will increase system
performance the most.
• Moore’s ultimate prediction was that transistors court would double
every 18 months.
ADVANCES OF VLSI:
 High performing computing system.
 Advances in Mathematics Issues in Large scale simulation (IMS)
 Advances in micro-electronic devices
 Advances in speech synthesis
 Security system integration
 Very large aperture Radio Telescope

CONCLUSION: To develop electronic devices with low power dissipation and


cost and high performance, the best alternative is VLSI