VERILOG CODE FOR 2:4DECODER

module deco1(y, a,b); output [3:0] y; input a,b; not(a_bar,a),(b_bar,b); and(y[0],a_bar,b_bar),(y[1],a_bar,b),(y[2],a,b_bar),(y[3],a,b); endmodule

(a)

(b) FIG SCHEMATIC DIAGRAM FOR 2:4DECODER

FIG SCHEMATIC DIAGRAM FOR 2:4DECODER

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