ChipScope Pro Software v12.

1 Script
1--Hello and welcome to this recorded e-Learning on the ChipScope Pro software.
My name is Srikanth and I'll e yo!r instr!ctor for this mod!le.
In this mod!le we will learn ao!t the in-circ!it "eri#cation capailities of the
ChipScope Pro tools.
$his mod!le also has %H&L and %erilog "ersions of two las yo! can complete that
will enale yo! to !se ChipScope Pro tools '!ickly.
$here are step-y-step la instr!ctions and so!rce #les for yo! to download
separately incl!ded with the (ip #le that contains the printale "ersion of these slides
and a copy of the script.
)--*click+ If yo! wo!ld like to print o!t this slide presentation and a copy of the
script, please feel free to do so, now.
*click+ -o! can pa!se the recording and download the script and the slides y
clicking on the .ttachments !tton in the !pper right-hand corner.
Incl!ded with the (ip #le are %H&L and %erilog "ersions of two ChipScope Pro
software las.
If yo! want to try !sing ChipScope we recommend yo! !se the IS/ software "ersion
1).1.
Howe"er yo! proaly will e ale to complete these las with the same la
instr!ctions 0with some minor modi#cations1 for older or e"en newer software. 2!t if
yo! want e"erything to work perfectly, and yo! don3t want to ha"e any risks of the
instr!ctions eing slightly o4, yo! will need to !se the 1).1 "ersion of the IS/ tools.
5-*click+ If yo! are an e6perienced .SIC designer or new to 7P8. design, this
mod!le will help yo! red!ce yo!r learning c!r"e and get prod!cti"e faster with yo!r
new 7P8. design.
*click+ $his mod!le will help yo! de!g and "erify the f!nctionality of yo!r design.
$he practices co"ered here promote fast and e9cient de!gging.
:; $he o<ecti"es of this mod!le are to get yo! !p to speed on the asics of !sing
the ChipScope Pro software.
*click+ $hat incl!des eing ale to descrie how the ChipScope Pro software works
!t also the ene#ts of !sing ChipScope.
*click+ =e will descrie the ChipScope cores that are a"ailale and
*click+ how to !se the ChipScope Core 8enerator and Core Inserter tools.
*click+ It will also e helpf!l to yo! if yo! can plan to !se ChipScope early in yo!r
design >ow. $his will enale yo! to plan for s!9cient reso!rces to e a"ailale for
de!gging yo!r design. 2!t #rst we are going to disc!ss the importance of eing ale
to perform on-chip de!gging of yo!r hardware design with the ChipScope Pro
software.
?;*click+ =ell as we all know 7P8. designs are ecoming larger and more comple6.
&esigns are r!nning at a higher speed and designers ha"e less time to design,
sim!late and de!g their 7P8. hardware. In fact a recent 7P8. design s!r"ey
indicated that de!gging and "eri#cation acco!nted for nearly half of the entire
design time.
*click+.s design speeds and si(e ha"e increased de!gging and "eri#cation has
ecome more challenging. $o help impro"e design time, @ilin6 recommends the !se
of its ChipScope Pro software. $his enales die-le"el testing of a design y applying
stim!l!s to internal nodes of a design and retrie"ing the res!lting signals !sing
ChipScope cores !ilt with 7P8. reso!rces. $o do in-circ!it "eri#cation with
ChipScope yo! will apply stim!l!s to many nodes in the 7P8. and store the
generated signals !sing 7P8. lock A.M and other logic reso!rces. $he generated
res!lts can then e displayed with a ChipScope Pro Logic .naly(er. $his allows yo! to
'!ickly "erify the operation of many nodes and "erify the operation of yo!r de"ice in-
circ!it.
B-*click+ /lectronic de!gging in"ol"es proing a design to determine what is
happening on the chip at the die-le"el.
*click+ $o do this the ChipScope cores are placed in the 7P8. and can e connected
to the nodes the !ser wants to test. $his enales a !ser to test portions of a design
independently. *click+ $hen "erify the design's f!nctionality in an iterati"e fashion
so the !ser can reak the design down into se"eral ma<or components, test the
"ario!s inp!t and o!tp!t signals of each component and #nally decide ao!t making
any design changes. $he design can then e changed, re-synthesi(ed, re-
implemented efore the 7P8. is then reprogrammed.
*click+ $his iterati"e de!g process is possile eca!se of the recon#g!rale nat!re
of the 7P8.. It speeds the entire design "eri#cation process and gi"es the engineer a
great deal of con#dence that his design is operating properly and relialy.
C;*click+ $he ChipScope Pro software makes de!gging easy since it allows !sers
to test parts of a design and enales a fast iterati"e process. $his can red!ce yo!r
o"erall design time y )?D and red!ce on-chip "eri#cation and de!g time y ?ED.
Since ChipScope !ses 7P8. reso!rces in its component constr!ction and "eri#es
f!nctionality at the die-le"el, there isn't any e6traneo!s delay inserted into a sample
path. $his remo"es the !nnecessary timing "ariation when yo! de!g with
oscilloscope or other Logic .naly(er sol!tions.
*click+ ChipScope software is also tightly integrated into the @ilin6 7P8. design >ow
and o4ers speciali(ed >ows that s!pport all of @ilin63s c!stomers. $his incl!des
optimi(ed cores for &SP and emedded design. So ChipScope is a powerf!l tool that
is easy to !se and tightly integrated with the IS/ software.
F;*click+ $he ChipScope Pro software was originally designed to sol"e the prolem
of looking inside an operational 7P8. witho!t ha"ing to ring collections of signals to
IGH, which impacts Performance, ro!ting, and re'!ires an e6ternal header for
connecting to a logic analy(er or scope.
*click+ H"er the years, it has gained in "ersatility and power and can now e !sed to
in<ect signals into the 7P8. !sing the %IH core. $he ChipScope Pro tool can display
sampled data in many fashionsI wa"eform, data lists, and data-time plots. $he
datalists can e sa"ed to disk and !sed as inp!ts into a sim!lation. Similarly, the
same stim!l!s that dri"es a sim!lation can eJplayed into a %IH core to dri"e the
hardware.
*click+ In this way, theChipScope Pro tool s!pports sim!lation;it sho!ld ne"er
e!sed to replace sim!lation.
*click+ $he System Monitor, which meas!res the 7P8.3s temperat!re,"oltages, and
other parameters, is accessile "ia the ChipScope Pro software.
K; $his slide shows the de!gging cores that may e re'!ired for de!gging yo!r
design.
*click+ $he %IH core or %irt!al Inp!tGH!tp!t core is !sed to apply stim!l!s and read
o!tp!t transitions on nodes that yo! select. -o! can think of this core as a "irt!al test
header that can e placed on any node in yo!r design. $he IL. core or Integrated
Logic .naly(er core is a capt!re core. It can e !sed to create c!stom triggers that
when acti"ated ca!se the storing of data d!ring circ!it operation. $hese conditions
are placed y yo! to control when yo!r system signals will e stored. -o!r sampled
signals are then encoded in yo!r 7P8.'s lock A.M for later retrie"al "ia L$.8.
*click+ $he IL. core allows the !ser to c!stomi(e the width and trigger ports, so that
di4erent si(es of data can e retrie"ed. $he IL. core is a asic core !sed in most H&L
designs.
*click+ $he I2. or Integrated 2!s .naly(er core is optimi(ed emedded designers
core that is !sed for !ilding designs !sing the @ilin6 Micro2la(e Soft Processor core
or a dedicated Power PC core. $he I2. core allows designers to analy(e PL2 and HP2
!s signals and o4ers protocol detection which is necessary since emedded
designers are often testing their c!stom peripherals !sing ChipScope. ChipScope
makes it easy to sample the most commonly sampled signals on these !sses s!ch
as control, address and data signals associated with these !ses.
*click+ $he .gilent $race Core ) is commonly called the .$C) core. $his core is
!sef!l for storing larger amo!nts of data o4chip or when a c!stomer is !sing the
.gilent $race Port analy(er. It o4ers on-chip de!gging of @ilin6 7P8.s with the
.gilent 7P8. &ynamic Proing feat!re. $he ChipScope cores !se 7P8. logic reso!rces
in their constr!ction.
1E--*click+ 2lock A.Ms and slice reso!rces are !sed for storing trigger conditions
and data. $he 7P8. slice reso!rces can also e !sed for comparing the internal
signals with yo!r trigger conditions.
*click+ $he ChipScope cores will re'!ire a signi#cant amo!nt of reso!rces so yo! will
ha"e to plan on lea"ing room for them in yo!r 7P8.. $his sometimes means that
!sers ha"e to !se a larger part for testing and prototyping and then !se a smaller
part in this same package for prod!ction.
$o help with planning s!9cient reso!rces for de!gging, the ChipScope Pro software
has a !ilt-in reso!rce estimator as part of the Core 8enerator and Core Inserter
tools. $his makes it easier for yo! to plan yo!r de!gging as part of the design
constr!ction.
11--$here are three >ows a"ailale to add the appropriate ChipScope cores to yo!r
design.
-o! can choose etween the Core 8enerator >ow, the Core Inserter >ow, and the
Plan.head >ow 0this is <!st like the Core Inserter >ow, !t integrated into the
Plan.head software1.
*click+ $he Core 8enerator >ow re'!ires yo! to directly instantiate the cores into
yo!r H&L code. $his has the ad"antage of gi"ing yo! access to all of yo!r H&L nodes
for testing. .dditionally, some of the ChipScope Pro cores can only e added to yo!r
design when instantiated into yo!r H&L. 7or e6ample the %IH core can only e added
with the Core 8enerator >ow. $he disad"antage is that yo!r H&L code will ha"e to e
modi#ed to instantiate these cores. .lso note that to remo"e these cores from yo!r
design yo! wo!ld ha"e to comment them o!t.
*click+ $he Core Inserter >ow is a simpler process that adds the cores directly into
yo!r synthesi(ed netlist. $his >ow is m!ch simpler if yo! are doing some r!dimentary
de!gging and don't re'!ire all of the a"ailale cores. Mote howe"er that the Inserter
>ow only allows cores to e connected to the nodes a"ailale after synthesis. So
@ilin6 recommends that yo! maintain yo!r design's hierarchy d!ring synthesis. $his
will ass!re that most of yo!r primary nodes are a"ailale for de!gging. .nother way
to ens!re that essential nodes will e a"ailale to yo! for de!gging is for yo! to
apply a keep or sa"e synthesis option. Please note the !se of this option will depend
on yo!r synthesis tool so check yo!r synthesis tools doc!mentation.
Aegardless of which >ow or synthesis tool yo! !se the implementation is completed
y the @ilin6 IS/ software. $here are no special implementation tools re'!ired. .fter
implementation yo! can then !se the ChipScope Pro software to program yo!r 7P8.
and de!g yo!r design.
7inally, note that insertion of the ChipScope cores is also s!pported y the /&N tool
kit for emedded design and System 8enerator software for &SP design. $he
ChipScope Pro software is a complete de!g and "eri#cation en"ironment that can e
!sed with any 7P8. design.
1);*click+ $o add ChipScope cores yo! add them like yo! wo!ld any H&L
component into yo!r design with the IS/ software. So !se the command Pro<ect +
Mew So!rce. $his opens the Mew So!rce =i(ard.
*click+ -o! name the ChipScope &e#nition and Connection #le. $his will contain all
of yo!r ChipScope cores into one so!rce #le. L!st name the #le and then the g!i will
open allowing yo! to add the cores into yo!r design.
*click+ Mote that the created cores are associated with yo!r top-le"el design #le
a!tomatically, !t this can e altered. &o!le-clicking the C&C #le a!tomatically
starts the ChipScope software.
15--*click+ $here are two types of ChipScope cores. $here are capt!re cores which
create triggers and store data, and control cores commonly called ICHM cores which
interface capt!re cores to the L$.8 chain. $he ICHM core or Integrated Control core
allows yo! to control and interface the L$.8 chain with !p to 1? capt!re cores.
*click+ $here are a n!mer of di4erent capt!re cores to choose from.
*click+ $he IL. is the most fre'!ently !sed for H&L designs. /ach IL. core can e
c!stomi(ed for the n!mer and width of signals to e capt!red or triggered. $he IL.
core is the most commonly !sed capt!re core, it and the ICHM core are s!pported
with the Inserter >ow.
*click+ $he IL.G.$C core is similar to the IL. core e6cept data is capt!red o4-chip y
the .gilent $race Port analy(er. $his is especially !sef!l if yo! are storing large
amo!nts of test data o4-chip. $his may e helpf!l since the a"ailale n!mer of
lock A.Ms "aries y de"ice and de"ice density. $his is a separate hardware prod!ct
a"ailale to ChipScope !sers. So for more information check o!r wesite.
*click+ $he Integrated 2!s .naly(er core has two "ersions, one for the HP2 and
another for the PL2 !s. $hese are emedded !sses that are fre'!ently !sed y o!r
c!stomers !sing o!r /medded &e"eloper's Nit or /&N and targeting either the
Micro2la(e Soft Processor core or the dedicated Power PC a"ailale in some of o!r
de"ice families. Mow these are especially helpf!l to !sers that are de!gging the
eha"ior of c!stom peripherals attached to either the PL2 or the HP2 !s.
*click+ $he %IH core as mentioned earlier is !sed to de#ne and generate "irt!al IH
ports.
1:;$he IL. cores can e instantiated into yo!r H&L code with either the Core
8enerator or added to yo!r design3s netlist with the Core Inserter >ow 0which wo!ld
also incl!de the Plan.head >ow1.
*click+ $he IL. s!pports !p to fo!r trigger ports with a single instantiation.
*click+ Op to )?B channels can e !sed per trigger port.
*click+ $here can also e m!ltiple match !nits for yo! to match yo!r signals against
on the same trigger port. So each IL. core s!pports !p to 1B match !nits. So for
e6ample, if a !ser employed all : trigger ports and set : match !nits on each trigger
port that system wo!ld !se all possile 1B match conditions.
*click+ If yo! are !ilding a more comple6 system yo! can add additional IL. cores
and cascade their o!tp!ts to check for comple6 trigger se'!ences that incl!de !p to
1B le"els as shown in this diagram. In this case, yo! see m!ltiple IL.s connected in
series to allow for the ma6im!m n!mer of match !nits. .ny design can contain !p
to 1B IL. cores.
1?;*click+ Since the IL. core is the most pertinent, it is s!pported with all three
>ows.
*click+ =hile any design can ha"e 1? IL. cores to make s!9cient match !nits, note
that the si(e and speed of the #nished system can e a4ected. $hat is why we
recommend that designers test part of the design each time and don3t add so many
cores to test the entire system at once. $hat is !s!ally not necessary.
*click+ $he speed of operation of each core will "ary y the chosen de"ice family,
speed grade and options yo! set for each IL. core. It is important to "erify the si(e of
the ChipScope cores efore adding them to yo!r design. $o that end, e s!re yo!
lea"e the Ose SAL1Bs and APM options asserted when c!stomi(ing the IL. cores.
$his will sa"e yo! LO$s and registers and red!ce the si(e of yo!r cores.
1B--*click+ $he %IH core enales yo! to insert "irt!al IH pins into yo!r design.
*click+ It often helps to think of the inp!ts to the %IH core as an o!tp!t node from
yo!r design yo! wish to test. M!ch like yo! wo!ld !se an L/&.
*click+ Likewise each o!tp!t of the %IH core is !sed as an inp!t to a node in yo!r
design. 7or e6ample a !ser might force a "al!e or p!lse train into the 7P8. y !sing
a %IH core con#g!red as an o!tp!t.
*click+ /ach %IH core can e de#ned as an inp!t or o!tp!t and programmed to e
synchrono!s or asynchrono!s to either the system clock or the L$.8 clock. /ach core
can also s!pport !p to )?B its. $he ChipScope Pro software also gi"es yo! "ario!s
ways to toggle the data. 7or e6ample yo! can !se a p!lse train or e"en te6t data to
toggle the data. $he %IH core can only e added with the Core 8enerator >ow. So
keep in mind yo! co!ld still add the ICHM and IL. cores yo! need with the Inserter
>ow, !t yo! may #nd it easier to <!st !se the Core 8enerator >ow if yo! are going to
e !sing the %IH core for de!gging.
1C- $here are some things to know ao!t the %IH core.
*click+ $he %IH core can only e created y the CHA/ 8enerator tool. *click+ =hen
the %IH core is generated it does not !se the lock A.M !t !ses the 7P8. logic.
*click+ $he inp!ts are like L/&s for e6amining signals and the H!tp!ts are like
switches or p!sh!ttons for dri"ing signals.
1F-$he Core Inserter >ow, which as I mentioned is also s!pported with the Plan.head
>ow, is often considered the easiest >ow to follow eca!se it is an a!tomatic means
of adding the cores to yo!r design.
*click+ $his >ow does ha"e one signi#cant limitation. It does not allow the !ser to
sample nodes internal to an H&L component.
*click+ Hnly post-synthesis nodes are a"ailale to e proed. So it is a good idea for
yo! to maintain hierarchy d!ring synthesis.
*click+ .fter the !ser !ses the Core Inserter to specify the post-synthesis nodes to
e proed the Inserter will perform the translate phase of implementation. $his is
necessary eca!se in the Core 8eneration >ow the cores are inserted as a netlist.
*click+$he >ows were designed to e tightly integrated into the IS/ tools and
Plan.head.
1K- So this slide <!st s!mmari(es the key points we ha"e made ao!t the Core
Inserter >ow. I am not going to repeat what I ha"e already told yo!.
$here are two new points here tho!gh. 7irst all make s!re all of yo!r software is
!pdated if yo! are going to !se the Core Inserter or Plan.head >ow. /specially since
the Plan.head >ow is new, yo! cannot mi6 and match software "ersions.
.lso one minor point, keep in mind yo!r implementation time will increase "ery
slightly when !sing the ICHM and IL. cores.
)E-- So in the #rst la yo! are going to add an IL. core to an e6isting design with the
Core Inserter.
.s I mentioned earlier this is proaly the easiest way to add the ChipScope cores to
yo!r design.
*click+ $his la will gi"e yo! a chance to !se the Core Inserter to add an IL. core,
*click+ gi"es yo! an opport!nity to c!stomi(e an IL. core y setting trigger
conditions and
*click+ !se the ChipScope software to con#g!re a de"ice, set trigger conditions,
analy(e and de!g a simple design. $his la shows ChipScope in its simplest form
and shows how easy it is to set!p design analy(e and de!gger design.
*click+ $he #les and la instr!ctions are in the (ip #le yo! can download with these
slides and script. Mote that a Spartan-B SPBE? demo oard is !sed in the la, !t if
yo! ha"e the #nished pino!t of yo!r demo oard, yo! sho!ld e ale to !se yo!r
demo oard with this same design. .ll yo! will need to do is modify the design3s Oser
Constraints 7ile to match yo!r demo oard pino!t.
)1-- Mow efore we show yo! a little it ao!t the Core 8enerator >ow and gi"e yo!
a chance to do a la with the Core 8enerator >ow, we want to introd!ce the
Plan.head >ow.
*click+ .s I mentioned this is "ery similar to the Inserter >ow. It allows yo! to
interacti"ely select signals to proe from the Plan.head software3s Metlist and
Schematic "iews. In this case, we see some screen shots that ill!strate <!st that
point.
*click+ .s yo! can see we ha"e synthesi(ed the design and Plan.head has loaded
the synthesi(ed netlist and allows !s to select some of the nodes from o!r design
with the schematic "iewer. $his is a "ery easy and powerf!l way to set !p for
de!gging and many c!stomers like this >ow.
=e also see that o!r "ario!s triggers nodes are listed and can e managed with
Plan.head.
*click+ $here is also a =i(ard that walks yo! thro!gh the set!p of yo!r ChipScope
cores when !sing this >ow which makes it "ery !ser friendly. *click+ $he Plan.head
software also inserts and compiles the cores, esides eing tightly integrated with
ChipScope.
));*click+ Selecting signals to e de!gged is "ery simple with the Plan.head >ow.
.s I mentioned this can e done with a schematic "iew, !t also can e accomplished
with a netlist 0or folders1 "iew. $he netlist "iew allows yo! to see a list of the inp!t
and o!tp!t nets from each le"el hierarchy and select which ones to add.
*click+ $he 7ind command can also e !sed to #nd a partic!lar node name yo! are
looking for to complete testing.
)5;*click+ $he si(e of each of the de!g cores can e easily fo!nd with the
Plan.head >ow, !t also with the other >ows.
Since the cores are added as netlists, gi"en the #le e6tension of M8C, they can e
selected and their si(e determined easily. $his is important eca!se the amo!nt of
reso!rces will "ary y the n!mer of match !nits yo! are sampling.
*click+ %erifying the si(e of any component or netlist is normally done y right-
clicking a component in Plan.head. $his will a!tomatically generate a g!i, like yo!
see here, where the n!mer and type of each reso!rce contained in the component is
listed. Howe"er, Plan.head will also show yo! the connecti"ity of each core in a
schematic.
*click+ Hne of the other side ene#ts of Plan.head is the aility to make e4ecti"e
area constraints. Some c!stomers choose to assign their ChipScope cores to speci#c
area constraints in order to a"oid ro!ting congestion or to keep the core near critical
logic. Howe"er, note that if yo! test nodes that are far away from the cores, then
yo! can ha"e some signi#cant ro!ting delay.
):--*click+ =ith the Core 8enerator >ow the cores are instantiated directly into the
H&L. *click+*click+ $his re'!ires man!ally editing yo!r H&L to make all of the
necessary connections to the cores and this takes more time to !ild. =e will !se
this >ow to de!g the same design we !sed in La 1 !t now we are going to !se the
Core 8enerator >ow and also !se the %IH core.
*click+ If later on in the design >ow yo! want to remo"e the cores from yo!r design,
yo! m!st comment them o!t. *click+ $his process !ses the standard
implementation process that wo!ld e done y any designer wanting to add a
component made y the @ilin6 Core 8enerator. *click+ $his is not nearly an
a!tomatic >ow !t does gi"e yo! complete control o"er the nodes yo! want to test
since yo! can proe inside of components.
*click+ $he Core 8enerator is now integrated in the latest 1).1 Planahaead tool. So
yo! can now add these cores man!ally in the Planahead design >ow.
)?-*click+ In la ) we are going to !ild on the knowledge we gained in the #rst la.
=e will add an IL. and a %IH core to the design !sing the Core 8enerator >ow this
time.
*click+ $his la will gi"e yo! a chance to work with a di4erent >ow, !se the %IH and
the %IH console cores to de!g, control and monitor yo!r design with the ChipScope
software and e ale to contrast the two >ows, "ery worthwhile la.
*click+ $he #les and la instr!ctions are in the (ip #le yo! can download with these
slides and script. Mote that a Spartan-B SPBE? demo oard is !sed in the la, !t if
yo! ha"e the #nished pino!t of yo!r demo oard, yo! sho!ld e ale to !se yo!r
demo oard with this same design. .ll yo! will need to do is modify the design3s Oser
Constraints 7ile to match yo!r demo oard pino!t.
)B--*click+ In s!mmary the ChipScope software enales yo! to shorten yo!r
de!gging time y ?ED and enales rapid de!gging iterations. It also allows yo! to
test yo!r design component y component. ChipScope also enales yo! to test any
node in yo!r design 0when !sing the Core 8enerator >ow1 and to test many nodes at
once.
*click+ -o! can add ChipScope cores at any time either d!ring design constr!ction
or after yo!r design has een made.
*click+ /ach of the ChipScope cores has a speci#c p!rpose. $he IL. core is !sed for
"iewing the operation of yo!r de"ice. .nd the %IH core is !sed for dri"ing stim!l!s to
yo!r design and sampling data from yo!r design.
*click+ .dding the ChipScope cores make minor impact to the design. It !s!ally
enales yo! to test yo!r design at system speed since the cores are optimi(ed for
oth speed and to !se minimal reso!rces.
)C--*click+-o! can learn more ao!t ChipScope from @ilin6's homepage. L!st go to
the cspro location speci#ed here to learn more ao!t what is o4ered.
*click+ -o! can also "iew ChipScope recorded demos, access the BE-day license for
ChipScope, and re"iew the !ser g!ide and other software doc!mentation. $here are
also recorded demos that disc!ss how to insert ChipScope cores and how to !se the
ChipScope software to de!g and "erify yo!r design.
*click+-o! can also learn more ao!t .gilent's prod!cts. .gilent's 7P8. &ynamic
proe comines the on-chip de!g f!nctionality with the power of a Logic .naly(er.
$he las yo!'re ao!t to complete co"er the most essential f!nctionality of the
ChipScope software. So e s!re to spend some time working with the tools now that
yo! ha"e completed the training presentation.
)F;If yo! wo!ld like to learn more ao!t other co!rses and A/Ls we o4er, incl!ding
o!r ChipScope Pro co!rse, please go to the /d!cation Ser"ices page. In this co!rse,
yo! will asically learn all that there is to know ao!t each de!gging >ow. $here are
las that go way eyond what we ha"e co"ered here. Incl!ding disc!ssion ao!t the
trigger options, data "is!ali(ation, scripting options 0incl!ding $CL scripting to
a!tomate data >ow1, and a disc!ssion ao!t remote access.
2!t whate"er yo! do, please take a second and gi"e !s yo!r feedack on this A/L.
.ll yo! ha"e to do is click on the icon at the end of the recording and s!mit an
e"al!ation. If yo! fo!nd this helpf!l, and I hope yo! did, it is important yo! take a
co!ple min!tes and tell !s that. .nd while yo! are at it, please let !s know what
other topics yo! wo!ld like to see co"ered in another A/L.
My name is Srikanth. 7inally, thanks for listening to this recorded e-Learning on the
ChipScope Pro Software. $hanks for yo!r time and attention. .nd thanks for yo!r
!siness.
)K;*nothing said+