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Author: Alma A. M.

Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

Analogue design – Multistage amplifier
1. Introduction: Analogue amplification is used to achieve necessary voltage and power gain, when a certain input of a system is too small to be fed to one of the subsystems [1]. The motive of using two stages is to get voltage amplification from input stage and then buffer that stage’s output in the output stage making the final output impedance low while keeping the voltage gain to required level. For acquiring such criteria using Bipolar Junction Transistors (BJT), common emitter circuit configuration as the input stage (to get voltage gain with high output impedance) and then emitter follower circuit configuration (to get a gain ≤ 1 with low output impedance) can be used. This particular lab exercise was focused on designing and building similar two stage analogue amplifier according to the given specification. 2. General specification and design criteria: The lab instruction contained specific design criteria and circuit configuration.

Figure 1: provided circuit configuration [2] The specifications were as follows: [2]  The design should use two stages (a common emitter stage with partially by-passed emitter resistance followed by a common collector stage).  The overall gain of both stages should be at least 5 ± 0.5.  The input impedance must be higher than 50 ± 5 kilo ohms.  The output impedance should be lower than 1.5 ± 0.15 kilo ohms.  The output impedance of the first stage should at least be ten times less than the input impedance of the second stage to avoid loading between two stages. The restrictions were as follows: [2]  BC547 (NPN transistor) must be used for circuit construction.  Supply voltages should be 0 and Vcc = 10 V.  The assumed value of β ≈ 200.

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

3. Theoretical analysis: 3.1 First stage – Common Emitter configuration:

Vo1

Figure 2: Common emitter stage [2] In such configuration, R1 and R2 works as a potential divider making the base voltage (VB) constant. This causes a current iB to flow making the voltage VB = VBE + IE (Re1+Re2). As VBE is constant and VB is made constant, it is apparent from the equation that the transistor becomes stabilized in terms of I E and accordingly the voltage drop across Re1+Re2. Thus the configuration sets the transistor to be in active region irrespective to the value of β. [3] Along with this, the transistor provides a voltage gain making the output voltage to be Vo1 with high output impedance. 3.1.1 Large signal analysis (DC analysis): Assumptions made:  Any capacitors behave like open circuit.  No AC sources are present in the circuit.

These assumptions result in the following circuit (where, RE = Re1 + Re2):

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

IB

IE

Figure 3: large signal analysis model using OrCad PSpice©

This can be simplified further as follows:

IB

IE

Figure 4: simplified large signal analysis model using OrCad PSpice ©

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

Here, R1 R2 Rth = R1 || R2 = R1 + R2 R2 Vth = R1 + R2 VE = IE RE = (β+1) IB RE Vth – VB IB = Rth VB – VE = VBE = constant - III From II; VB = Vth - IBRth Therefore; VBE = Vth - IBRth - VE = Vth - IBRth – (1+β) IBRE So, Vth - VBE IB = Rth + (1+β) RE We know; IC = β IB β (Vth - VBE) = Rth + (1+β) RE (Vth - VBE) = RE Here it is clear that this circuit configuration is largely independent of β. Now, gm = IC / (kT/q) and r π = β / gm (Assuming, Rth<< (1+β) RE and (1+β) RE ≈ β RE) - II -I (Since, IE = (β+1) IB) Vcc (Voltage drop across R2) (Equivalent resistance between Base and GND)

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

3.1.2 Small Signal Analysis (AC analysis): Assumptions made:  Any capacitors behave like closed circuit.  All DC sources are grounded.  RS is small making the voltage drop across it infinitesimal, i.e.; negligible. The assumptions result in the following circuit:
gmvbe

ib

ie

Figure 5: Small signal analysis model using OrCad PSpice © Now, ib = vbe / rπ ie = ib + gmvbe ve = ieRe2 = (ib + gmvbe) Re2 = (vbe / rπ + gmvbe) Re2 = vbeRe2 (gπ + gm) Now; (since, gπ = 1/ rπ)

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

vs = vb Therefore; vs = vbe + ve = vbe [1 + Re2 (gπ + gm)] On the other hand; vo1 = - gmvbeRc Therefore; Gain, Av1 = vo1 / vs - gmRc = 1 + Re2 (gπ + gm) = - Rc / Re2 (assumption: gmRe2 >>1 and gm>>gπ)

3.1.3 Input Impedance: To measure the input impedance, the impedance at base was measured first. After that the total impedance was calculated from the input. [4]
ib C rπ gmvbe

Zb1 Zin

D

Figure 6: Input impedance – Thévenin model using OrCad Pspice© Now, vb = vbe + ve = vbe [1 + Re2 (gπ + gm)] ib = vbe / rπ (From previous calculation)

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

Therefore, Zb1 = vb / ib = rπ [1 + Re2 (gπ + gm)] = rπ + (β+1) Re2 (Since, rπ = β / gm and gπ = 1/ rπ) Therefore; The total input impedance; Zin1 = R1 || R2 || Zb1 3.1.4 Output Impedance: To find the output impedance, the output nodes C and D were observed. Thévenin theorem was applied to find the equivalent resistance, i.e.; output impedance of the circuit (figure 6). Here, vo1 = - gmvbeRc isc = gmvbe Therefore; Zout1 = | vo1 / isc | = |- Rc| = Rc 3.2 Second stage – Common collector configuration: (Open circuit voltage across C and D) (Short circuit current between C and D)

vo1

Figure 7: Common collector stage [2]

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

In such configuration, the output is taken from the emitter and there is no collector resistance. Thus it works as a buffer presenting a gain < 1 with low output impedance. 3.2.1 Large signal analysis (DC analysis): Assumptions made:  Any capacitors behave like open circuit.  No AC sources are present in the circuit. These assumptions result in the following circuit:

Figure 8: large signal analysis model using OrCad PSpice© This can be further simplified as follows:

IB
1

1

VB VE IE

Figure 9: simplified large signal model using OrCad PSpice © Here, R3 R4 Rth1 = R3 || R4 = R3 + R4 (Equivalent resistance between Base and GND)

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

R4 Vth1 = R3 + R4 VE = IE Re = (β+1) IB Re Vth1 – VB IB = Rth1 VB – VE = VBE = constant - III From II; VB = Vth1 - IBRth1 Therefore; VBE = Vth1 - IBRth1 - VE = Vth1 - IBRth1 – (1+β) IBRe So, Vth1 - VBE IB = Rth1 + (1+β) Re We know; IC = β IB β (Vth1 - VBE) = Rth1 + (1+β) Re (Vth1 - VBE) = Re In this circuit configuration also it is apparent that I C is largely independent of β. Now, gm = IC / (kT/q) and r π = β / gm (Assuming, Rth1<< (1+β) Re and (1+β) Re ≈ β Re) - II -I (Since, IE = (β+1) IB) Vcc (Voltage drop across R2)

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

3.2.2 Small signal analysis (AC analysis): Assumptions made:  Any capacitors behave like closed circuit.  All DC sources are grounded.  RS is small making the voltage drop across it infinitesimal, i.e.; negligible. The assumptions result in the following circuit:
gmvbe

ib

ie

Figure 10: small signal analysis model using OrCad PSpice © Here, ib = vbe / rπ ie = ib + gmvbe = vbe (gπ+gm) ve = ieRe = vbe Re (gπ+gm) = vo vo1 = vbe + ve = vbe + ieRe = vbe [1 + Re (gπ+gm)] Therefore; (Since, gπ = 1 / rπ)

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

Av2 = vo / vo1 Re (gπ+gm) = 1 + Re (gπ+gm) This derivation shows that the circuit configuration of this stage is working like a buffer. 3.2.3 Input Impedance: The input impedance was found following similar procedure as before.
vb rπ gmvbe

≈1

(Since, Re (gπ+gm) >> 1)

ib Zin Zb2

ve

ie

Figure 11: Input impedance model using OrCad PSpice©

Here, vb = vbe + ve = vbe [1 + Re (gπ + gm)] ib = vbe / rπ Therefore, Zb2 = vb / ib = rπ [1 + Re (gπ + gm)] = rπ + (β+1) Re (Since, rπ = β / gm and gπ = 1/ rπ) (From previous calculation)

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

Therefore; The total input impedance; Zin2 = R3 || R4 || Zb2

3.2.4 Output Impedance: Assumptions made:  Source for this stage vo1 = 0.  Source resistance (output impedance of first stage) was counted.  The dependent current source’s (gmvbe) resistance = 1 / gm These assumptions resulted in the following circuit:

Zout

Figure 12: output impedance model using OrCad PSpice© Therefore; Zout2 = Zout1 || Re || rπ || 1/gm 3.3 Overall Gain: The overall gain can be calculated by multiplying the gain of both stages. Along with that another factor called loading effect should be accounted for, as it tends to reduce the overall gain. [5] The loading effect in this scenario was, Zin2

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

Zin2 + Zout1 Therefore; Zin2 Overall gain, Av(total) = Av1 Av2 Zin2 + Zout1 4. Designing for a certain scenario: 4.1 Design Consideration: For using a BJT amplifier two aspects must be considered as follows: 4.1.1 The value of IC – Avoiding cut-off:
Saturation region

IC (mA)

Active region

VAC
(peak)

IB (uA)
Cut-Off region

VBE

VCE

VCC

Figure 13: Ic and VCE consideration for active mode of operation from I-V characteristics of BJT The first consideration that must be made is to choose such a value of I C so that the transistor is not in cut-off mode. 4.1.2 The value of VCE – Avoiding saturation: The value of VCE must be greater than VBE in order to keep the BJT in active region. Since, an AC signal is expected as output, the maximum peak of that signal should also be considered i.e.; the output always stays in active region. This can be illustrated by the following equation: VCE > VBE + VAC(peak-maximum)

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

4.2 Estimated values: 4.2.1 First stage:

VC VCC = 10

VCE

VE

Figure 14: Circuit for calculation - first stage From the figure: VCE = 10 – IC RC – IE RE (where, RE = Re1 + Re2) ≈ 10 - IC (RC + RE) Now, VCE > VBE + VAC(peak-maximum) Let, VAC(peak-maximum) = 2 V and suitable IC = 1.8 mA. Now, VBE + VAC(peak-maximum) = 10 - IC (RC + RE) By putting respected values in I; 10 – 0.7 - 2 RC + RE = ≈ 4 kΩ 1.8 m Therefore; RC + Re1 + Re2 = 4 kΩ Again, From gain, AV1 = - Rc / Re2 ≥ 5 Estimated values; RC = 3.3 kΩ Re2 = .56 kΩ Re1 = .1 kΩ Therefore; AV1 = 5.9 ≥ 5 -I (since, IC = βIB and IE = (β+1) IB, thus IC ≈ IE)

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

RC + Re1 + Re2 = 3960 ≈ 4kΩ Now, Ic = 1.8 mA Therefore; IB = Ic / β = 1.8 m / 200 = 9 uA Hence; gm = Ic / (kT / q) = (1.8/25m) mS = 72 mS rπ = β / gm = 200 / 72m = 2.78 kΩ From previous calculation: Vth - VBE IB = β RE Therefore; Vth = β RE IB + VBE = (200) (660) (9u) + 0.7 = 1.89 V Again from previous calculation: R2 Vth = R1 + R2 Therefore; R1 / R2 = (Vcc / Vth) – 1 = 4.29 Estimated values: R1 = 390 kΩ R2 = 100 kΩ Vcc

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

4.2.2 Second Stage:

VCE VCC = 10

VE

Figure 15: Circuit for calculation – second stage From the figure: VCE = 10 – IE Re ≈ 10 - IC Re Now, VCE > VBE + VAC(peak-maximum) Let, VAC(peak-maximum) = 2 V and suitable IC = 1.8 mA. Now, VBE + VAC(peak-maximum) = 10 - IC Re By putting respected values in I; 10 – 0.7 - 2 Re = ≈ 3.9 kΩ 1.8 m Now, Ic = 1.8 mA Therefore; IB = Ic / β = 1.8 m / 200 = 9 uA Hence; gm = Ic / (kT / q) = (1.8/25m) mS = 72 mS rπ = β / gm = 200 / 72m = 2.78 kΩ Re (gπ+gm) Av2 = 1 + Re (gπ+gm) = 0.99 ≈ 1 -I (since, IC = βIB and IE = (β+1) IB, thus IC ≈ IE)

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

From previous calculation: Vth1 - VBE IB = β Re

Therefore; Vth1 = β Re IB + VBE = (200) (3900) (9u) + 0.7 = 7.72 V Again from previous calculation: R4 Vth = R3 + R4 Therefore; R4 / R3 = 1 / [(Vcc / Vth) – 1] = 3.3 Estimated values: R4 = 330 kΩ R3 = 100 kΩ Vcc

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

4.3 Simulation and associated values:

4.3.1 First stage:

Figure 16: Circuit construction of first stage using OrCad PSpice©

Figure 17: simulation of first stage using OrCad PSpice©

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

4.3.1.1 Gain calculation: vSp-p = 0.2 V v01p-p = 6.3 – 5.3 = 1 V Therefore; Gain = 1 / 0.2 = 5 4.3.1.2 Impedance calculation: Zin1 = R1 || R2 || Zb1 = R1 || R2 || rπ + (β+1) Re2 = 390k || 100k || [2.78k + (201)(560)] = 47.09 k Ω Zout1 = RC = 3.3 k Ω It is apparent that Zout1 is slightly out of range. This was because, lower value of Re2 was making Zin1 to go below the required range and for that Re2 had to be increased and the increase in RC followed the previous increase to maintain the gain. 4.3.2 Second stage: (which is within range (50±5) k )

Figure 18: Circuit construction of second stage using OrCad PSpice ©

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

Figure 19: simulation of second stage using OrCad PSpice© 4.3.2.1 Gain calculation: Vo1p-p = 1 V v0p-p = 6.85 – 5.87 = 0.98 V Therefore; Gain = 0.98 / 1 = 0.98 ≈ 1 4.3.2.2 Impedance calculation: Zin2 = R3 || R4 || Zb1 = R3 || R4 || rπ + (β+1) Re = 390k || 100k || [2.78k + (201)(3.9k)] = 72.28 k Ω Zout2 = RC = 3.3 k Ω (> 10 Zout1 )

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

4.3.3 Multistage:

Figure 20: Circuit construction of multistage using OrCad PSpice ©

Figure 19: simulation of second stage using OrCad PSpice ©

Author: Alma A. M. Rahat [2nd year, BEng in Electronic Engineering, University of Southampton], Nov’09

Overall gain calculation: Zin2 Overall gain, Av(total) = Av1 Av2 Zin2 + Zout1 = (5) (0.98) (0.96) = 4.704 5. Reference: 1. 2. 3. 4. http://www.electronicsinschools.org/page.php?ps=92&p=348 Lab notes, D3, University of Southampton ELEC1005 Analogue electronics notes, University of Southampton http://209.85.229.132/search?q=cache:xbtJOMSsnJcJ:notes.ump.edu.my/fkee/BE E2213_Farizan/6.%2520BJT%2520small%2520signal.ppt+loading+effect+bjt&cd=7& hl=en&ct=clnk 5. http://en.wikipedia.org/wiki/Loading_effect#Loading_effect 6. Mr. Tim Forcer, University of Southampton (Which is within range)