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In multicore chips, the processing cores are organized as rectangular tiles. Each core is attached
to a local router. When a core wants to communicate with another, it creates a packet containing
the required data which can then be sent to the neighboring cores through a well structured set of
routers and links. In NoCs with wormhole switching, each packet is serialized into a sequence of
flow control unitscalled flits. Flits move across the routers in a hop by hop manner.
Virtual channel router
The figure shows the bock diagram of a conventional Virtual Channel (VC) Router. It offers buffers for
storage (VC), a control unit for route and VC computation and a crossbar switch for routing the flits
The input unit of each input port accepts flits from that particular direction and store in an
available VC, the router compute the route for the flit residing in the VC. The VC allocator
checks if there are any free buffers in the input unit in the direction of the route computed. The
switch allocator performs necessary arbitration on its multiple input flits, to pass only singly flit
each to its five outputs. The crossbar switch passes its input flit to output.
There are various routing algorithms available for the router to fix the route of the flits. Some of
these include dimension order routing, turn model routing[1], odd-even routing[2], Congestion
Avoidance Scheme[5], Congestion Relief Scheme [5]etc.
The basic router architecture and the routing algorithms are first modeledin verilog (using Xilinx
tool). These are then synthesized to obtain the timing and latency parameters of various units in
the router module. One of the limitations of Xilinx tool is that, it cannot be customized to
specific process technology. The synthesizable verilog code generated using Xilinx is fed to
Synopsys Design Compiler(SDC) to obtain various technology specific aspects like area, static
power, routing constraints etc. SDC is the most popular technology tool used in major chip
manufacturing companies.
Inorder to find out the latency of packets generated in NoC (i.e. the time taken by the packets to
travel from the source to destination),we use Booksim[4].
From the synthesis report obtained from Xilinx, the various components involved in the
implementation are tabulated and the dynamic power can be obtained using Orion[3], the most
common interconnect power estimator model.
The Industrial Training is organized as learning of these three tools SDC, Booksim and Orion.
The key focus of this industrial training is to make myself equipped with design and analysis of
existing baseline NoC router architectures.
1. Synopsys Design Compiler: Continuing the trend of delivering innovative synthesis
technology, Synopsys Design Compiler streamlines the flow for a faster, more
predictable design implementation .As geometries shrink to 65nm and smaller, process
technologies, design complexities increase multifold, making it extremely difficult for
designers to complete projects on schedule. Nanometer effects such as coupling
capacitances between parallel interconnects have much higher impact on interconnect
delays and need to be considered during synthesis to ensure predictable design
implementation. Moreover, routing congestion, whether caused by the floorplan or the
presence of highly interconnected logic structures in the netlist, needs to be fixed early in
the design cycle to avoid iterations. RTL synthesis that produces a better starting point
for physical implementation improves schedule predictability and avoids costly iterations
between synthesis and place-and-route. The benefits of using this tool include creating a
better starting point for physical design, area, power and timing analysis, congestion
prediction, early detection and debugging of layout issues.
2. Booksim: BookSim [4] is a cycle-accurate interconnection network simulator written in
C++which models a multi stage NoC router pipeline in sufficient detail and accuracy. It
supports a wide range of topologies such as mesh, torus and flattened butterfly networks,
provides diverse routing algorithms and includes numerous options for customizing the
network's router microarchitecture.
3. Orion: It is a suite of dynamic and leakage power models developed for various
architectural components of on-chip networks, to enable rapid power-performance
tradeoffs at the architectural level [3].
1. C.J . Glass and L.M. Ni, The Turn Model for Adaptive Routing, Proc. 19th Ann. Int'l
Symp. Computer Architecture, pp. 278287, May 1992.
2. G. M. Chiu. The odd-even turn model for adaptive routing. IEEE Transactions on
Parallel and Distributed Systems, 11(7):729{738, July 2000.
3. A. B. Kahng, L. Bin, L.-S. Peh, and K. Samadi. Orion 2.0: A fast and accurate NoC
power and area model for early stage design space exploration . In DATE-'09:
Proceedings of the Design, Automation and Test in Europe Conference, pages 423{429,
4. W. Dally and B. Towles. Principles and Practices of Interconnection Networks.
Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2003.
5. Ying-Cherng Lan, Michael C. Chen, Alan P. Su, Yu-Hen Hu, Sao-J ie Chen. Fluidity
Concept for NoC: A Congestion Avoidance and Relief Routing Scheme, In SoC-'08:
Proceedings of 21st Annual IEEE International SoC Conference, pages 65{70, November