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Institutionen fr systemteknik

Department of Electrical Engineering


Examensarbete

Power management in embedded ARM HW


integrated with Embedded Linux
Examensarbete utfrt i Datorteknik
vid Tekniska hgskolan i Linkping
av

Bo Svangrd
LiTH-ISY-EX--09/4147--SE

Linkping 2009

Department of Electrical Engineering


Linkpings universitet
SE-581 83 Linkping, Sweden

Linkpings tekniska hgskola


Linkpings universitet
581 83 Linkping

Power management in embedded ARM HW


integrated with Embedded Linux

Examensarbete utfrt i Datorteknik


vid Tekniska hgskolan i Linkping
av
Bo Svangrd
LiTH-ISY-EX--09/4147--SE

Handledare:

Per Wolde

Examinator:

Olle Seger

Enea AB, Stockholm


, Linkpings universitet

isy

Linkping, 6 April, 2009

Division, Department
Division of Computer Engineering
Department of Electrical Engineering
Linkpings universitet
SE-581 83 Linkping, Sweden
Avdelning, Institution

Language
 Svenska/Swedish

 Engelska/English
Sprk

Date

Datum

2009-04-06

Report category

 Licentiatavhandling

LiTH-ISY-EX--09/4147--SE
 Examensarbete
 C-uppsats
 D-uppsats
Title of series, numbering 
 vrig rapport
Rapporttyp

ISBN

ISRN

Serietitel och serienummer ISSN


URL fr elektronisk version

http://www.ep.liu.se

Title

Titel

Author

Frfattare

Abstract

Power management in embedded ARM HW integrated with Embedded Linux


Bo Svangrd

Sammanfattning

Today, more and more embedded hardware devices are reaching the market and
consumers with a demand for smaller and better devices than yesterday. Increasing
the performance of a device decreases the operating time since more power is
consumed, still, decreasing the size of the device also decreases operating time as
the battery size decreases.
To allow the performance to increase and the size of the device to decrease, the
designer must nd techniques allowing the hardware to consume less power during
normal usage of a device than during the peak usage.
In this thesis an implementation of an ARM based microprocessor system is
presented and used for measuring and evaluation of the power consumption possibilities of the system.

Keywords ARM, Atmel, Microprocessor, Power saving


Nyckelord

Abstract
Today, more and more embedded hardware devices are reaching the market and
consumers with a demand for smaller and better devices than yesterday. Increasing
the performance of a device decreases the operating time since more power is
consumed, still, decreasing the size of the device also decreases operating time as
the battery size decreases.
To allow the performance to increase and the size of the device to decrease,
the designer must nd techniques allowing the hardware to consume less power
during normal usage of a device than during the peak usage.
In this thesis an implementation of an ARM based microprocessor system is
presented and used for measuring and evaluation of the power consumption possibilities of the system.

Contents
1 Introduction

1.1

Purpose

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2

Problem denition

1.3

Limitations

. . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Hardware specication

2.1

System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2

Hardware

2.3

Component selections

. . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1

Microprocessor

. . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2

Memories

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3

Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4

Power regulator . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Hardware design
3.1

3.2

3
3

11

PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11

3.1.1

Terminology

. . . . . . . . . . . . . . . . . . . . . . . . . .

11

3.1.2

Physical size

. . . . . . . . . . . . . . . . . . . . . . . . . .

12

3.1.3

Design rules . . . . . . . . . . . . . . . . . . . . . . . . . . .

12

3.1.4

Components

12

3.1.5

Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interconnections

. . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Software specication

13
13

15

4.1

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15

4.2

Subsystems

16

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1

AT91 RomBoot . . . . . . . . . . . . . . . . . . . . . . . . .

16

4.2.2

AT91 bootstrap . . . . . . . . . . . . . . . . . . . . . . . . .

16

4.2.3

U-Boot

4.2.4

Linux kernel

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .

5 Software design
5.1

QiLinux build system

16
17

19
. . . . . . . . . . . . . . . . . . . . . . . . .

19

5.1.1

AT91 bootstrap . . . . . . . . . . . . . . . . . . . . . . . . .

19

5.1.2

Linux kernel

20

. . . . . . . . . . . . . . . . . . . . . . . . . .
vii

viii

Contents

6 Power management
6.1

Overview
6.1.1

6.2

6.3

21

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power mode states

. . . . . . . . . . . . . . . . . . . . . . . . . . .

21
22
24

6.2.1

CPU power modes . . . . . . . . . . . . . . . . . . . . . . .

24

6.2.2

System power modes . . . . . . . . . . . . . . . . . . . . . .

25

Maximum power consumption . . . . . . . . . . . . . . . . . . . . .

25

6.3.1

Maximum current consumption on the system voltage

. . .

28

6.3.2

Maximum current consumption on the USB voltage

. . . .

29

7 Results

31

7.1

Power up

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31

7.2

Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . .

32

7.3

Power eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

7.4

Conclusion

36

7.5

Problems

7.6

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

36

7.5.1

Cadstar crashes . . . . . . . . . . . . . . . . . . . . . . . . .

36

7.5.2

Blind vias . . . . . . . . . . . . . . . . . . . . . . . . . . . .

36

7.5.3

Ethernet not working

36

7.5.4

Display not working

. . . . . . . . . . . . . . . . . . . . . .

37

7.5.5

Connector problems

. . . . . . . . . . . . . . . . . . . . . .

37

7.5.6

LTC3555 power regulator

. . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . .

37

Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

37

Bibliography

39

A Acronyms

43

B Jumper conguration

45

C Connector specication

46

D HW sketch

47

E HW schematics

49

F Boot messages

57

F.1

Boot ROM

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

57

F.2

Bootstrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

57

F.3

U-Boot

F.4

Linux Kernel

F.5

Init system

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G LTC3555 driver

57

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

58

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

61

63

Chapter 1

Introduction
1.1 Purpose
The purpose of this thesis work is to design and implement an embedded Linux
platform based on a Micro Controller Unit (MCU) with the Advanced Risc Machine
(ARM) architecture, aimed at power management features and low power consumption.
The system is to be used as a test platform for future designs and as an embedded platform for course related work in Enea Linux Competence Center (ELCC).
Features to reduce power consumption and features for power management are
to be added to the hardware platform, together with support in the software used.

1.2 Problem denition


This thesis works will give the reader an overview of the possible problems when
constructing an embedded ARM single board computer (SBC) where low power
consumption is preferred.
The hardware constructed is a subset of the AT91SAM9263-EK evaluation
platform available from Atmel.

To allow for power management support and

tests, the on board power regulator needs to be modied.


The Linux operating system includes support for the AT91SAM9263 processor
and for the AT91SAM9263EK platform from Atmel. Support for the processor is
continuously improved with new features and these modications are released in
the form of a patch to the kernel source. These patches are collected by kernel
maintainers for inclusion into the kernel source.

1.3 Limitations
Due to time being a limited resource during the course of this project, the subject
of designing an ARM based system is limited to implementing a subset of an ARM
based evaluation board. The focus of this report is power management and power
1

Introduction

saving techniques in general and how some of those are implemented in the design.
Much work has been done on the hardware level, searching for suitable components
and the work should be seen as a test implementation for further development.

Chapter 2

Hardware specication
2.1 System
Designing an embedded low power microprocessor hardware platform requires
many small steps to reach a fully functioning system. During the design phase of
this work, application notes and reference designs were studied to help minimize
risks of the project during component selection and system schematics design.
The requirements for the system is support for the Linux operating system
and power management. These issues aects the hardware component selections,
as the selected components need to be supported by Linux and also support low
power modes. Linux support for components and features in the microprocessor
and peripheral circuits has been exploited by studies of the Linux kernel sources
[20]. More information on the software selections is found in section 4 on page 15.

2.2 Hardware
The required hardware resources and system interfaces are:

64

MiB SDRAM

64

MiB Flash

SRAM

Generic interfaces








JTAG
USB Host
USB Device
Serial Debug port
Ethernet
LCD
3

Hardware specication




GPIO
SPI
I2C

The system is powered by battery or by an external voltage power supply to


charge the battery. The external voltage supply should also be able to fully power
the board when the battery is disconnected. A sketch of the hardware system is
seen in the gure 2.1.

Figure 2.1.

Sketch of system

2.3 Component selections


2.3.1

Microprocessor

The hardware platform designed is required to run the Linux operating system,
thus there is a need for the microprocessor to include a Memory Management
Unit (MMU). Several hardware architectures exists that are viable, among them
are ARM, MIPS, Power PC (PPC), Hitachi SuperH, i386 and the AVR32. ARM
is selected as it is already being used within ELCC and is also the architecture of
choice for many embedded platforms today[27]. Over

75%

of the mobile phones

on the market today are ARM Powered [28], among them are several mobile
phone platforms from Sony Ericsson, Nokia, Samsung, Motorola, Apple[37] and
OpenMoko[31].

2.3 Component selections

The popularity of the ARM microprocessor has to do with the licensing program of the ARM architecture, where several dierent chip manufacturers are
making their own specialized version of the microprocessor[29].
Choosing the Arm architecture is therefor a simple choice as it is the microprocessor family of choice in the industry today and because it will integrate well
within the current systems in ELCC.
Selection of the specic microprocessor is a little harder, since each manufacturer will develop their microprocessor with their own peripheral additions. The
base architecture can be the same but the interfaces and programming of the chip
will dier. Support is thus needed in software for the base architecture and the
chip manufacturers additions to the microprocessor.

The software support for

dierent processors is discussed in chapter 4 on page 15.


Among the chip manufacturers developing microprocessors for the ARM architecture, a few were selected for closer study by reading the Linux devices
website[22]. Among the most popular manufacturers are Marvell, Samsung, Atmel and Cirrus Logic. Marvell produces a family of processors called XScale, this
family is quite large and includes processors dedicated to several dierent applications. Samsung provides the S3C24xx series which is used in among other, the
NEO Freerunner [31] phone, Atmel which has the AT91SAM series that is being
used within ELCC and Cirrus Logic has EP93xx series which is interesting due
to a very good and easily accessible documentation and reference designs and also
due to the Maverick Crunch oating point co processor embedded in several processors. Researching application notes and design help for the processors available
from each manufacturer, found that Atmel and Cirrus provided good documentation and reference designs available which are suitable to use as a reference for
an implementation of a board.

Samsung had less information available on the

Internet and no schematics could be found of a working system at the time.


As processors in the AT91SAM series is being used within ELCC, knowledge
and software is present in the company. The selection of microprocessor is therefore
to use the AT91SAM9263 from Atmel.

2.3.2

Memories

The AT91SAM9263 has two separate memory interfaces, EBI0 and EBI1. Each
interface supports Static Random Access Memory (SRAM), Synchronous Dynamic
Random Access Memory (SDRAM) and NandFlash memories, EBI0 also supports
Compact Flash memory cards.

Looking at the designs for the AT91SAM9263-

EK [10] board, SDRAM memory is connected to the EBI0 interface and SRAM
memory is connected to the EBI1 interface.

Further investigations of the data

sheet show that EBI0 is optimized for application memory space, and EBI1 allows
support for external frame buer for the Liquid crystal display (LCD) controller
without impacting on processor performance[9]. Therefore the SDRAM memory
will be placed on the EBI0 bus, and SRAM memory is placed on the EBI1 bus.

Hardware specication

SDRAM
SDRAM is used as the main memory for the system and its applications.

The

processor supports standard SDRAM memories, and a low power type called mobile SDRAM. The dierence between the two types are that the mobile device
uses a lower supply voltage and consumes much less power compared to what the
standard memory consumes in all power modes. The power consumption of mobile
and standard SDRAM is presented in table 2.1 derived from [3], [30]. To reach

64

MiB memory, one chip of the mobile type presented in table 2.1 is required

or two chips of the standard type, this, and the overall lower power consumption
of the mobile memory, shows that selecting memory of the mobile type, a large
power saving can be gained, however, since our prototype had a limited budget,
two memory chips of the standard SDRAM type is selected, providing the system
with

64

MiB memory.

Type

name

voltage

operating (mA)

standby (mA)

Mobile

MT48H1M32LFCM

Standard

MT48LC16M16A2P

3.3V
3.3V

185
270

1
2.5

Table 2.1.

SDRAM

Comparison per chip between power usage of mobile SDRAM and standard

The schematic for the SDRAM memory was implemented with [10], [11] and
[30] as references. Using a connection for two 16-bit chip carriers interface to the
SDRAM controller.

SRAM
The SRAM memory is connected to a secondary memory bus on the AT91SAM9263
and is used as a frame buer memory for the graphic controller. Placing this memory on the secondary memory bus allows for greater bandwidth during the transfer
of the data to the LCD controller, which can be performed with the Direct memory
access (DMA) controller.
The required amount of SRAM memory is

640x480@60Hz

and

16

Mbit using a resolution of

bits per pixel.

The connection of the SRAM to the processor is implemented using [10] and
[11] as references.

Flash
Non-volatile storage is needed for the device to store data for the start up process
of the processor, le storage and root le system. The supported ash memory
types of the AT91SAM9263 memory controller are NandFlash, NOR Flash, Compact Flash. It is also possible to connect any type of ash with a serial interface
compatible with the microprocessor. Most notable are DataFlash memories and
Secure Digital Cards. A comparison of the boot capabilities of the Central Processing Unit (CPU) and the access method to the memory is seen in table 2.2.

2.3 Component selections

Flash type

Bootable

File system

Nand Flash

MTD

Secure digital

RAW

USB Flash

RAW

Data Flash

MTD

NOR Flash

RAW

Compact Flash
Table 2.2.

RAW

AT91SAM9263 supported memories for booting and le systems

In this design, the boot memory choosen is a DataFlash device with a capacity
of

4M iB .

The root le system can be selected to the DataFlash or be a replace-

able memory of either Secure digital or an Universal Serial Bus (USB) connected
memory device. Booting from a secure digital memory is possible when using the
B revision of the CPU, however this is currently not supported as the bootstrap
or U-boot boot loader currently does not support this memory type.

2.3.3

Ethernet

Support for ethernet is provided by the AT91SAM9263 microprocessor, which delivers a MII (MII) or Reduced Media Independent Interface (RMII) interface that
is attached to an Ethernet physical interface circuit. The physical interface converts the bus data to the 10/100BASE-T twisted-pair interface, other conversions
are possible but most consumer computer products today supports this standard.
Many interface circuits exists for this purpose, and investigation of the market
for power usage among the available circuits, showed that these components consume quite a lot of power. The result of the investigation is presented in table 2.3.
Data is taken from each circuits data sheet [15], [16], [17], [24], [33].
The selected device is the DM9161 from Davicom. The DM9161 is a successor
to the DM9161A that is used on the evaluation kit AT91SAM9263-EK.
PHY Chip

DM9161

DM9161A

DM9161B

LXT971

DP83848C

100BaseTX

88

92

130

92-110

81

mA

10Base-T TX

70

72

66-82

92

mA

10Base-T idle

25

25

mA

Power reduced

18

25

17

40-45

14

mA

Power down

3.8

51

mA

Table 2.3.

Current requirement for Ethernet PHY:s

The DM9161 enters power reduced mode when no signal is detected on the
ethernet port. It will automatically wake up when signal is detected on the port.
When further decrease in power consumption is required, it also features a power
down mode, in which only the MII interface is powered.

The MII interface is

supplied to allow a reset of the device so it can enter a non power save mode.

Hardware specication
Connecting the DM9161 physical interface circuit to the microprocessor is per-

formed with the RMII interface, which is a specication for a interface between
an Ethernet connector and Switch ASIC [7], in this design, RMII is used between
the network interface of the microprocessor and the network connector.

2.3.4

Power regulator

The power regulators on this board are supplied by a

4.2V

5V

external voltage and a

battery. The connected devices on the circuit board needs several dierent

voltages, the AT91SAM9263 microprocessor requires


host port needs

12V

5V

1.2V

and

3.3V .

The USB

to power external USB devices and the LCD display uses

current limited for the back light.

requires a supply voltage of

All other components on the board

3.3 V. A sketch of the system power generation blocks

is shown in gure 2.2

Figure 2.2.

System voltages

Previous designs in ELCC shown that the LM2672 simple switcher is being
used in several successful designs, however to generate all required voltages several
chips would be required and additional chips for battery charging support. Further
searching for power regulators revealed the LTC4066 and the LTC3555 from Linear
technologies.
Linear LTC4066 is an USB power controller [34] circuit, and can provide the
system with one voltage output from USB voltage input, external

V input and

a battery input. To provide all system voltages, several regulators are necessary
when using this solution. Another solution is to use the Linear circuit LTC3555 [35]
which has a similar USB power manager. Compared to the LTC4066, the LTC3555
provides four voltage outputs, however it lacks the external voltage input. Three
of the regulators on the chip can be individually shut down by controlling the

2.3 Component selections

enable inputs of the LTC3555 or through the Inter Integrated Circuit (I

C ) serial

interface. The fourth regulator is always activated and provides low current backup
power to the CPU.
The LTC3555 is selected to provide power to the CPU, SDRAM, SRAM,
ethernet PHY, DataFlash and the touch controller. To provide power to the USB
host connectors and the LCD monitor, additional boost regulators are used to
generate the voltages required.
Output

Voltage range

Setting

Always on LDO

3.3 V
0.8 3.6
0.8 3.6
0.8 3.6
3.3 V

3.3
3.3
1.2
3.3
3.3

Regulator 1
Regulator 2
Regulator 3
LDO
Table 2.4.

V
V
V

Current

25mA
400mA
400mA
1A
25mA

V
V
V
V
V

Available voltages and current of the LTC3555

The USB host ports requires a voltage of

5V

100mA to power external


500mA. The available
voltage at 5V is the external
at

devices, and possibly if the devices are power hungry, up top


current is not sucient to power this, as the only

voltage input (from USB port), which is not suitable because the primary concerns
is to provide power to the CPU.
provide a shut down of the
Also required is a

12V

5V

Instead we use a

3.3V

regulated voltage and

net using a step up regulator.

voltage to power the LCD back light. This voltage is

required to be shut down, so the display does not consume power when the display
isn't in use.
The step up regulator LM2731 was selected, as it was small and easy implemented in the design. This regulator supports both regular step up mode of the
voltage according to equation 2.1, and a white led mode, where the output current
can be controlled using a single resistor.


VOU T = 1.23 + 1.23

RADJ
51.1 103


(2.1)

Chapter 3

Hardware design
3.1 PCB Layout
This hardware design will uses a microprocessor with Ball Grid Array (BGA) foot
print. Designing with this type of components have some advantages and some
disadvantages.
Advantages consists of a smaller surface used by the component, leading to
denser and neater placement of components on the circuit board, but because of
the denser placement of components, the routing also is denser and has to be
planned to t underneath the BGA component. Additional layers are required on
Printed Circuit Board (PCB) to t all required connections to the components.
Also, since several connection layers are used on the board, vias are required to
connect between the layers. The vias which normally are through-hole, might need
to be congured as blind-vias or embedded vias to save routing space in the inner
layers.

3.1.1

Terminology

Escape routing is the methodology for routing all BGA pads to the edge of
the BGA package, performing this step is required when working on large
BGA packages.

Multi layer PCB uses several copper layers inside the laminate material.
Components are placed on the outer layers, and routing is performed either
on the outer layers or the inner layers.

Via is a connection between the electrical layers of a Multi Layer PCB.


Dierent types of vias exists, examples are through hole, blind and buried,
see gure 3.1. In our design through hole and blind vias are used.

0
11

12

Hardware design
Blind

Blind

Buried

Through hole

Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6

PCB Material

Figure 3.1.

3.1.2

Hole

Dierent Via types

Physical size

During the initial work in of this thesis work the board size was dened to be

120x70mm. Early during construction work the size was revised to a board size of
100x160mm, to make the placement of components and routing of copper tracks
easier.

3.1.3

Design rules

The recommended foot print pattern for the AT91SAM9263 BGA package is specied in the data sheet for the processor[9]. Each pin is connected to a pad with
diameter of

0.4mm

shrunken with a solder mask opening of

0.275mm.

This de-

nition of the PCB pad is a Solder Masked Dened (SMD) pad. According to application note[32], Non Solder Mask Dened (NSMD) pad is preferred over SMD
pads, and also during conversations with our printed circuit board manufacturer.
In this design, the NSMD pad is used based on the recommendations of the
application note[32] and the recommendation from the manufacturer.
The vias used are blind vias, with a hole diameter of
ring of

15

mil, and an annular

mil. This via is placed in the middle of four PCB pads and the signal is

routed on one of the signal layers.


The sizes are derived from the guidelines and from application notes found on
BGA routing and viewing the design rules constraints from Elprint[1].

3.1.4

Components

Each component mounted on the PCB needs a specication in the PCB CAD
program, Cadstar electronic CAD software. The specication includes denitions
of which symbol to use for the schematic, which foot print symbol to use on the
PCB and a specication on the connections between the schematic symbol and
the foot print. Many component specications already exist in Cadstar however
several of the components used in this project does not exist and needs to be
specied in Cadstar.
Usually components have pin or pad connectors on the edge of the device,
as components gain more features, the number of required connections to the

3.2 Interconnections

13

circuit board also increases.

Several methods exists to allow for the increase in

number of connections, popular methods are to just increase the number of pins,
but this increases the component size which is disadvantageous since circuit board
space often is a limited resource. Other methods are to decrease the pitch between
component, however ner control of the placement of the component on the circuit
board is required. Components with the BGA foot print have their connections
in a matrix under the component, allowing a large increase in the number of
connections to the circuit board while keeping the surface area small.
The foot print for a BGA component are dened either with or without a
solder mask. These are named SMD and NSMD pads, the dierences is presented
in gure 3.2 [32].
NSMD PAD

SMD PAD

PCB Material

Copper

Solder resist

Solder

Figure 3.2.

3.1.5

SMD and NSMD pads

Placement

Placement of components on the circuit board, if done correctly greatly reduces


the task of routing the PCB. The components with most connections to the microprocessor are the SDRAM, SRAM and the LCD interfaces. These components
were placed rst so the path of the copper tracks is kept as short as possible for
these components. The power supply is kept collected away from the other circuits
on the circuit board and the power is distributed to the components on a separate
power plane. The placement of components on the completed circuit board is seen
in gure 3.3.

3.2 Interconnections
According to the routing and placement guideline in [26], all the copper tracks are
to be kept as short as possible. Additional help for the placement and routing of
the dierent components were found in the data sheet of the components or an
application not from the supplier. Data sheets providing information on placement
details and routing are [11], [23], [15], [35].

14

Hardware design

Figure 3.3.

Picture of the system

Chapter 4

Software specication
4.1 Software
As mentioned in chapter 2.1, the board is designed using the Atmel evaluation
board AT91SAM9263EK and application notes as references. The Linux kernel
provided by Atmel for the evaluation board is expected to work for the initial
boot of the system on this board, as the SDRAM memory interface and network
interface is the same as for the reference board. The problem is to allow the board
to start on USB power alone, which will require power partitioning to allow a
shutdown of the SDRAM memory and an USB stack very early during the boot
process. To display an image on the LCD display, a frame is stored in memory
on the processor and the LCD controller reads the memory through DMA access.
The display also uses a three wire serial interface that is required to activate and
set the mode of the LCD display. The power regulator LTC3555 have inputs to
enable and disable the voltage outputs of the device and also to set working mode
of the switch regulators.

The functions are controlled either using a

I 2C

serial

interface or through General purpose input/output (GPIO) pins.


The software needed for the system is the Linux operating system.

Several

Linux distributions exists for the ARM architecture, among them are Emdebian
and Embedded Ubuntu. These distributions often contain software that will remain unused for the intended application but for this platform, we need to have a
minimal Linux system. A minimal Linux system for the selected processor requires
four separate software parts, the AT91 Bootstrap, U-Boot boot loader, the Linux
kernel and BusyBox system shell and applications.

The available data storage

space for system applications are limited to the size of the DataFlash chip, this
chip is

4M B
15

16

Software specication

4.2 Subsystems
4.2.1

AT91 RomBoot

The AT91SAM9263 processor has two selections for the boot memory, the CPU
can boot from either an internal Read Only Memory (ROM) or from a external
memory. The circuit board does not have an external memory suitable to use for
boot, so this module will always start with the internal boot program. A owchart
of the boot program is found in gure 4.1.

START

Yes
SD Card Boot?

No

Yes
NAND Flash Boot?

Download
to RAM

No
Yes
DataFlash Boot?
RUN
No

SAM-BA Boot

Figure 4.1.

ROM Boot Program[9]

If no application is found in either of the memories on the gure, it starts


the SAM-BA application that enables downloading and starting of applications
through a serial interface. The SAM-BA program can also be used to download
and store applications in the ash memories on the processor.

4.2.2

AT91 bootstrap

AT91 Bootstrap[2] program is responsible for conguring the CPU interfaces and
register to a state suitable for starting further applications. The tasks performed
are to enable crystal oscillators, Phase locked loop (PLL) oscillators, enabling the
SDRAM interface, peripheral pins of the CPU and initial interrupt conguration.
The bootstrap also load the U-Boot boot loader application from the DataFlash
device and begin the execution.

4.2.3

U-Boot

The U-Boot boot loader is used to setup and initialize the system to a state that
the Linux kernel can take over from. The essential tasks to perform are:
1. Setup and initialize the RAM.

4.2 Subsystems

17

2. Initialize one serial port.


3. Detect the machine type.
4. Setup the kernel tagged list.
5. Call the kernel image.
More information on each of these tasks performed during boot are found in
the le arm/Booting of the kernel documentation[20].

4.2.4

Linux kernel

The Linux kernel needs modication in several places.

The support for devices

not implemented on the board should be removed, and the LCD display requires
a driver module. The display will also require a Serial Peripheral Interface (SPI)
interface to control the display modes documented in [8].

The SPI interface is

connected to GPIO pins and a software module is required to implement the serial
interface over the pins.
Also the LTC3555 power supply circuit will need a driver to enable us to shut
o dierent power nets when they are not needed, and one of the LM2731 boost
regulators has a shut down function to turn o LCD back light on pin PA14.

Chapter 5

Software design
5.1 QiLinux build system
The Linux operating system environment is built using the build system developed
by ELCC.

The build system can build minimal Linux boot images for several

embedded Linux boards.

The procedure for adding new boards to the system

is done by adding conguration les for the required software to a conguration


directory and providing necessary patches for all software which are built for the
board.

5.1.1

AT91 bootstrap

During the hardware design, contacts within Atmel suggested that a

16

MHz

clock crystal should be used instead of the clock crystal frequency used on the
AT91SAM9263-EK evaluation board. This design change aects the PLL lters
and division ratios, which are set up by the bootstrap program.

Recalculating

the PLL lters is done with software provided by Atmel[5]. The loops has been
calculated for output frequencies

196M Hz

and

96M Hz .

The calculated PLL lter

values is presented in table 5.1


PLLA

PLLB

FIN

16

16

MHz

FOUT

196

96

MHz

MUL

98

24

DIV

OUT

2b00

2b00

PLLCOUNT

0x3f

0x3f

USBDIV
Table 5.1.

2b01

PLL Conguration

19

20
5.1.2

Software design
Linux kernel

The Linux kernel adaptations made for the designed board is based on the AT91SAM9263EK tree of the kernel sources. Changes performed to the source is changing the
main clock oscillator frequency to

16

MHz, and to add the drivers for the hard-

ware parts that have changed, mainly the LCD display, which require changes
of the synchronization frequencies and also a driver to control the mode of the
LCD display through. The driver for the LCD display mode is available from the
OpenMoko project[18], although the serial interface of the display is connected to
GPIO pins instead of directly to the SPI interfacek.

Power management
Additional device drivers is implemented to add power management interfaces to
the chip for control of the functions of the LTC3555 power regulator and the LCD
back light controller to the Linux kernel.

Bit banged SPI bus


The SPI interface used to control the mode of the LCD display is connected to
GPIO pins and a serial interface is generated in software using a bit bang driver
from the Linux kernel tree source.

Chapter 6

Power management
6.1 Overview
Lowering the total consumed power of the system is necessary to allow an increased
operating time when the system is battery powered.

On the chip level, power

can be reduced by employing layout techniques so certain variables change in a


favorable way. In this work, chip level layout is not possible, since it is out of the
scope of this work to design a processor. The components could instead be selected
with low power consumption in mind. A short presentation will however be made
in regards to chip level improvements, while keeping the focus on selecting the
components with low power consumption or capabilities, such as dierent power
modes.
Methods to save power on the system level includes selecting low power components, which according to [21] is perhaps the most important up-front decision
which directly drives power eciency. Other decisions mentioned by [21] are to
partition voltages and clocks into separate domains and to enable scaling of the
frequency and the voltages.
Unfortunately, the selected CPU does not support scaling of the voltages, but
the clock frequency is switchable using the Power Management Controller (PMC),
seen in gure 6.1 of the PMC. During operation the processor will use the PLLA
frequency which is congured to

196M Hz .

The Linux kernel does not support

switching the processor clock frequency for the AT91SAM type of processors[20].
However, for power saving the processor clock could be lowered, keeping the system
waiting for an interrupt.

When the processor clock is lowered, the SDRAM is

recongured to self-refresh mode, and it is not possible to read the data in SDRAM
until the processor has returned to the faster clock frequency. The CPU can switch
between the clocks as seen in gure 6.1. Of these clocks, the

32kHz

clock crystal

will cause the most power saving possible in the CPU core.

32kHz
500Hz to be used by the processor. Although scaling the clock frequency
than 32kHz hasn't been shown to be stable on the selected CPU according

It is possible using the PMC to further scale the input frequency from
down-to
lower

to a comment by Anti Sullin in the le pm_slowclock.c of the AT91 Linux patch
21

22

Power management

series [19]. The power consumed on the


is

500Hz

is between

248 2720A,

V Core net when the CPU clock frequency

depending on core voltage and temperature

[9].

PMC_MCKR offset 0x0030

CSS
32 kHz

00

16 MHz

01

PRES

MDIV

Master
Clock
Divider

PRESCALER
PLLA

PLLB

10

11

Master clock

Divide with 1, 2, 4

Divide with 1, 2, 4,
8, 16, 32, 64

Processor clock controller

Figure 6.1.

6.1.1

Master clock controller [9]

Hardware

Static power consumption


The static power consumption is the static leakage of the chip. This leakage occurs
whenever the chip is powered. The leakage can be lowered by reducing the supply
voltage, reducing the size of the circuit, cooling the chip or to increase the threshold
voltage of the transistors[36]. To reduce the size of the circuit or increasing the
threshold voltages of the transistors, a redesign of the selected chip is required.
Reducing the supply voltage to the chip is possible.
Also forced cooling could be applied to the chip by placing a heat sink or a fan
over the chip.

Dynamic power consumption


Dynamic power consumption comes from switching activity on the chip.

The

consumed power can be approximated using the formula in (6.1)

Pdynamic v aCV 2 f
Reducing the dynamic power consumption
reducing the supply voltage to the chip

V,

Pdynamic

(6.1)
can be accomplished by

reducing the capacitance's on the chip

or reducing the switching activity on the chip

f.

Reducing the voltage powering the chip is very attractive since there is a
quadratic relationship to the dynamic power consumption. However, care needs
to be taken so performance is not aected.
Reducing the switching activity of the chip is done by either switching to a
lower clock input frequency, or by turning o the clock to certain parts of the

6.1 Overview

23

chips that are temporarily unused. Switching the input clock to a lower frequency
reduces the switching frequency for the whole chip, although throughput of data
in the CPU will also reduce so it will need more time to complete the execution.
Thus the total energy consumed for the system might be lower by running the
processor at full speed during execution and then power down the whole system
until the next task[36].

PCB
On the circuit board, power consumption can be reduced by selecting low power
components which according to [21] is perhaps the most important up-front decision, which directly drives power eciency.

Selecting components which in-

clude power management techniques will give us possibilities to dynamically reduce power consumption by enabling the power modes when the components are
temporarily unused. Other methods which are considered in [21] are to reduce the
load on outputs, minimize the number of active PLL, and using clock dividers for
a quick way of selecting an alternate frequency.
Another method to reduce power consumption, according to [21] is to Partition
separate voltage and clock domains.

Using the AT91SAM9263 processor, this

is already present in some degree, because the core voltage to this processor is
considerable lower than the I/O voltage of the processor. Also it is possible to use
a lower voltage on the memory interfaces if the memories used are of low power
type supporting the lower voltage. By using several voltage domains, some of these
domains may be left un-powered during boot-time until a device on the voltage
domain is requested by the software, and components not supporting any power
modes could be completely shut down by removing power to the component.
The SDRAM could be of a low power type and functions is implemented on
the SDRAM for self-refresh when the microprocessor is inactive.

Power regulator modes


The data sheet of the power regulator LTC3555 [35] indicates that the regulator
supports four regulation modes for the three switched voltage outputs. The modes
are named Pulse-skip, Burst, Forced burst and LDO.

Pulse-skip: Pulse skip mode provides a high eciency when the regulator is
operating with a high current load, the graphs in the data sheet [35] shows
that the load need to be greater than
one and two, and greater than

70mA

40mA

to reach

> 80%

for regulator

for regulator three.

Burst: The burst mode provides good eciency over a larger span compared
to the pulse skip mode. The disadvantage of burst mode is higher ripple on
the output voltage[6]. At high loads, the regulator is in the same manner
as pulse skip mode [35]

Forced burst: Provides slightly better performances than Burst mode at low
current output, but also gives a slightly more output ripple and the mode is
only useable when a low current is required by the load.

24

Power management

LDO: The switching regulators are converted to linear type, and provides a
continuous current to the load. The mode can only be used when the load
consumes very little current.

The change between the dierent modes is performed from Linux using a kernel
driver module found in appendix G. During measurements on the system, there is
also an additional method by toggling the pins in hardware directly on the PCB.
The current consumption is measured on jumper

J15

when the system is powered

by the USB connector, or directly on the battery when the board is supplied with
power from the USB connector when the board is powered from the battery.

Table 6.1.

PB4

PB5

Mode
Burst

Forced Burst

LDO

Pulse Skip

Pin settings for the modes of the LTC3555

6.2 Power mode states


6.2.1

CPU power modes

The AT91SAM9263 have ve dened operating modes according to the data
sheet[9].

The dened modes are Normal mode, Idle mode, Slow clock mode,

Standby mode and Backup mode. Selection of the dierent modes is done with
the PMC.

Normal mode:
CPU running at a programmable clock frequency.

Idle mode:
Processor stopped, waiting for an interrupt.

Slow clock mode:


Processor and peripherals are running on a lower clock frequency than in
Normal mode

Standby:
Processor stopped and waiting for an interrupt.

Peripherals in low power

states.

Backup:
Only VDDBU power the microprocessor. All peripherals are turned o.

6.3 Maximum power consumption


6.2.2

25

System power modes

The system uses the transition diagram specied in gure 6.2.

Run

Idle

Standby

Figure 6.2.

Suspend to RAM

Power Off

The dierent power modes

Run mode:
The processor is running at full speed in Normal mode.

Standby mode:
In Standby mode, all external interfaces are disabled. The SDRAM is put
in self-refresh mode and the microprocessor is waiting for interrupt.

The

system will wake up on activity on the serial port or the touch buttons on
the circuit board.

Suspend to RAM mode:


Suspending the system to Random Access Memory (RAM) memory is the
same mode as the Standby mode with a reconguration of the SDRAM
memories to enter auto-refresh mode and the processor enters Slow clock
mode. In auto-refresh mode, the SDRAM memory is able to keep the data
stored without receiving an external refresh signal. In this mode the system
will wakeup on the touch buttons on the circuit board.

Power o mode:
In power o mode, the power to the system and the processor is disabled,
leaving only the backup voltage to the processor active. The backup voltage
powers the slow clock oscillator, two real-time timers and 20 general purpose
registers.

6.3 Maximum power consumption


The three voltages provided to the system by the regulator are specied as seen
in table 2.4 on page 9 and the conguration is also found in table 2.4. The power
consumption presented in the tables are maximum ratings for the whole system,
and the conclusion to be taken from these theoretical values are that the system
should be able to be powered by only the USB power input of
regulators have an eciency of at least

80%.

2.5W , if the switching

26

Power management

Regulator conguration

Regulator 1: This regulator provide power to the SDRAM, the LCD display
and the analog to digital converter. A sketch of the power distribution and
regulators attached is seen in gure 6.3. The data in table 6.2 and equation
6.2 is taken from [13],[14], [23] and [30].

Figure 6.3.

Regulator 1

The current consumed by the LCD back light on the output of the LTC3555
is the combined power requirement of the LCD back light diodes and the
LM2731 step up regulator. The LM2731 will have an eciency of
with output voltage

12V

and a load of

20mA

70%

according to [13]. Thus the

power consumed by the LCD back light is calculated in equation 6.2

IBACKLIGHT _3V 3 = IBACKLIGHT _12V


unit
LM2731 Quiescent
LCD IO Supply
LCD back light
AD converter

P
Table 6.2.

(6.2)

maximum current consumption

LCD Panel Supply

SDRAM

1
1
= 43
61mA
0.7
0.7

20mA
3mA
50A
61mA
270mA
780A
360mA

Current consumption on Regulator 1

Regulator 2: This regulator provides power to the VDDCORE voltage of


the CPU. The power distribution and regulators for this voltage is seen in

6.3 Maximum power consumption

27

gure 6.4. Power consumption on the output of the regulator is presented in


table 6.3. The data in table 6.3 is taken from [9].

Figure 6.4.

Regulator 2

mode

consumption

CPU@240MHz, MCK@120MHz, T=25, VDDCORE=1.2 V


CPU Idle, MCK@96MHz, T=25, VDDCORE=1.2 V
CPU Shutdown, Static current, VDDCORE=1.2 V
Table 6.3.

70.9mA
19.5mA
240A

Power consumption on Regulator 2

Regulator 3: This regulator provides power to CPU interfaces and external


circuits such as the ethernet interface and the SRAM.
regulator have an eciency of

500mA.

80%

5V
100

The LT2731

when supplying a current of

500mA to both USB port, and


500
=
625mA
to be able to supply the USB
0.8
external devices with 500mA. A system sketch of the power distribution
The USB port is limited to supply

the step up regulator need

for this regulator is seen in gure 6.5 and in table 6.4 the maximum power
consumption is presented.

Figure 6.5.

Regulator 3

28

Power management
unit

Maximum power consumption

625mA
3mA
110mA
88mA
15mA
3.5mA
850mA

+5V USB
LM2731 Quiescent
SRAM
Ethernet PHY
DataFlash

50M
P Hz

oscillator

Table 6.4.

Power consumption on Regulator 3

Regulator LDO: The current consumed on the low dropout regulator (LDO)
output of the LTC3555 is regulated to

1.2V

using a second LDO regulator.

This voltage powers the backup registers, real time timers and the

32kHz

oscillator of the CPU. In gure 6.6 the power distribution is shown. The

V DDBU
25 C

voltage input of the CPU consumes

The LP2980 consumes

< 125A
LDO.

90A

3A

when the temperature is

when the output current is

when the output current is

1mA[12].

0,

increasing to

No data is available for the

No data is available for the LDO regulator of the LTC3555, but if

the data of the LP2980 is assumed to be similar to the LTC3555, the power
consumption added by the LDO can be assumed to always be

< 125A

on

VOUT. See gure 6.6 for a sketch of the LDO power distribution.

Figure 6.6.

6.3.1

Regulator LDO

Maximum current consumption on the system voltage

In the previous section, the power consumption presented have been presented
on output of each of the four regulators on the LTC3555 chip. Translating these
voltages to the system voltage output of the LTC3555 (VOUT ) chip adds the
power eciency of each regulator. The eciency factor VOUT voltage is found in
the data sheet of the LTC3555 [35] and presented in table 6.5. Calculation of the
current consumption on the
6.3 and 6.4.

V OU T

and

U SBV oltage

is performed by equations

6.3 Maximum power consumption




P3
IV OU T =

n=1

29

In Un
ef f iciencyn

V OU T

IU SBV OLT AGE =


+ ILDO

(6.3)

UV OU T IV OU T
ef f iciency

(6.4)

U SBV oltage Vf d

switch

name

voltage

current consumption

eciency

SW1

VSDRAM
VCORE
VIO

3.3V
1.2V
3.3V
4V

400mA
70.9mA
850mA

0.85

SW2
SW3
VOUT
Table 6.5.

0.85
0.90

Eciency of the power regulators at maximum power consumption

Applying equation 6.3 with data from table 6.5 gives the current on the system
voltage

VOU T . IOU T 920mA

6.3.2

Maximum current consumption on the USB voltage

From the

VOU T

voltage to the

VU SB

voltage, there is another switch regulator and

a protection diode. The eciency of this switch regulator is


consumption is

1000mA

90% when the current

according to the data sheet [35]

IU SB =

IOU T VOU T
ef f iciency

VU SB

9204
0.90

920mA

(6.5)

The maximum current consumed on the USB port is presented in equation 6.5.
The available input power to the LTC3555 is
voltage source and can be increased to

1A

500mA

when powered from a USB

when powered from other sources. In

the calculations above, the board is supplying

500mA

to USB devices, removing

this current from the calculation above leads to power consumed on the USB port
is

460mA,

allowing it to be powered from USB.

Chapter 7

Results
7.1 Power up
1
2
and the external power connector which contained errors that made it impossible
During inspection of the circuit boards manufactured, some errors from the hardware design was detected. Most obvious was the foot prints for the USB interface

to place the USB host connector and the external power connector on the PCB
without adjustments to the connector and PCB, see chapter 7.5.5 on page 37 for
more information.
When powering up the rst card, only the LDO voltage output of the power
regulator was detected correctly. The backup voltage generated by IC6 were measured to

3.3V ,

but should be

1.2V ,

no other output voltages from the regulator

were present. The missing voltages are presented in more detail together with a
solution in 7.5.6 on page 37. After corrections to the circuit board, all voltages
on the board are within acceptable levels. The voltages measured on the circuit
board is shown in table 7.1.
With the voltages on the board within tolerable levels, the microprocessor is
powered up. When the processor is powered, the

32

kHz clock crystal oscillates,

and the processor proceeds print a message on the serial debug port and read boot
from the non-volatile memories on the board as presented in gure 4.1, on page
16.

On the initial boot, no valid boot data is stored on the DataFlash and no

data was received on the debug port. However the SPI clock and data lines did
show activity. When the polarity of the serial debug port were swapped, the board
presented the message:

RomBOOT
>
on the serial debug port.
The Linux operating system and root le system is downloaded and started
on the target board using an application from Atmel called SAM-BA. The system

1 P8
2 CONN6
31

32

Results
name

regulator

nominal value

measured value

Vin

VBat

Vout

IC1

3V3 LDO

IC1

3V3 SDRAM

IC1

VCore

IC1

3V3 IO

IC1

VDDBU

IC6

+12V

IC7

+5V

IC8

5V
3.7V
V Bat + 0.3V
3.3V
3.3V
1.2V
3.3V
1.2V
12V
5V

5V
4.10V
4.41V
3.34V
3.24V
1.25V
3.26V
1.22V
10.3V
4.41V

Table 7.1.

Voltages provided by the power supply

boot up messages on the debug port of the CPU is shown in appendix F on page
57.

7.2 Power consumption


The power consumed by the device can be measured from either the USB connector
or on the battery. For the power consumption measurements a ampere meter is
connected to the board as shown in gure 7.1.
During the tests the voltage connections to the board have been supplied with
an external power box to the battery input or the USB voltage input. The voltage
conguration is shown in table 7.2
During normal usage all systems will not be used, so power consumption is expected to be lower than the maximum values calculated in 6.3. Several test points
suitable for power measurement exists on the circuit board, these test jumper
points are presented in table B.1. During these tests, measurements are limited to
only measure the power delivered from the power regulator, thus the measurement
points used are the measurement points J8, J14, J17 and J19. In table 7.3 the
measured power consumption on the output voltages from the power regulator is
shown. In table 7.6 the power eciency of the system is shown.

7.2 Power consumption

Figure 7.1.

33

Measurement of power consumption

Voltage conguration
A
B

VBAT
0V
3.9V

Voltage conguration used for measurements

Table 7.2.

node

VU SB
5V
0V

Reset state

Boot

Standby

Suspend

36mA
15mA
0mA

70mA
110mA
60mA

42mA
2mA
50mA

32mA
2mA
0mA

VIO
VSDRAM
VCORE
Table 7.3.

Power consumption on the system voltages

The power consumption shown in table 7.3 is not directly comparable with the
maximum power consumption calculated in chapter 6.3 on page 25, since there are
no USB units attached to the device, the LCD is not connected and the Ethernet
port is not correctly working. Removing the USB and LCD current consumption
gives a reduced maximum power consumption according to table 7.4.
Comparing the power consumed in Boot mode in table 7.3 to table 7.4 it can be
noted that both the current of
value and that

VCORE

VIO

and

VSDRAM

is only slightly lower.

is much lower than the maximum

VCORE

is connected directly to

the CPU core voltage input, and thus the consumption is only aected by the
activity of the CPU.

The current consumption presented in 6.3 have the clock

34

Results
net

consumption

VSDRAM
VCORE
VIO

280mA
70.9mA
225mA
< 125A

LDO
Table 7.4.

Reduced maximum power consumption

frequency of the CPU set to

240M Hz ,

while the measured value uses

198M Hz .

Assuming a linear relationship between current consumption and clock frequency


of the CPU the maximum current consumption can be recalculated from equation
7.1 to

58.5mA

IAP P ROX =

fM AX f
1
fM AX

The current consumption on the

VIO

and


IM AX

VSDRAM

(7.1)

voltages is believed to

be reduced due to the CPU not working all interfaces all full activity, therefore
both SDRAM SRAM and DataFlash are consuming much less current than the
maximum value.

The data sheets of the DataFlash device[4] inform that the

25A

DataFlash consumes

during standby and

7mA

during read.

The device

enters standby mode when the chip select connected to the device is deactivated.
During boot, data is read by the microprocessor and stored in SDRAM, and the
Linux kernel and le system is then accessed directly from the SDRAM memory,
thus, when the system has initiated the boot sequence, the DataFlash device is
deactivated, consuming only

25A.

The purpose for the SRAM memory were to

be used for storing the frame buer data sent to the display, since no display is
present, the SRAM memory is not used. The standby current of the SRAM device
is specied to

20mA

in the data sheet[25]. Also no external devices are connected

to the system during the measurements performed, reducing the current consumed
on the

VIO

voltage to

120mA.

The power consumption of the Ethernet PHY is

unknown, in the data sheet[15] the chip is specied to consume maximum power
during 100 Mbit TX, during idle use, the current consumption drops to

30mA.

The

chip also have two low power modes, Power Reduced mode and Power Down mode
consuming

18mA

and

3mA

respectively. The Power Down mode is automatically

entered when there is no cable attached to the ethernet interface, however, if the
Ethernet PHY only consumes

18mA,

the theoretical current consumption derived

from the maximum current consumption is reduced to

50mA which is less than the

measured value in 7.3 making this option unlikely. It is harder to nd information
on the SDRAM power consumption during light load, the data sheet [30] have
two currents specied that are interesting, the operating current and the standby
current. Applying the changes specied above to table 7.4 renders the data found
in table 7.5, that compared to the Boot mode power consumption in 7.3 shows a
much better matching of the current consumptions than earlier.

7.3 Power eciency

35
net

consumption

VSDRAM
VCORE
VIO

280mA
58.5mA
120mA
< 125A

LDO
Table 7.5.

Further Reduced maximum power consumption

7.3 Power eciency


During the measurements a comparison of the power eciency of the LTC3555
regulator were performed. The comparison was performed by dividing the power
on the outputs of the LTC3555 with the power fed into the LTC3555 for each
dened power mode of the CPU and each power mode of the power regulator. A
table of the power eciency factors are presented in table 7.6.
Voltage conguration

Mode

Reset state

Boot

Standby

Suspend

A
B

Pulse skip

0.52

0.54

0.54

0.48

Pulse skip

0.71

0.69

0.75

0.67

Forced burst

0.79

0.72

0.62

0.89

LDO

0.82

0.54

0.56

0.82

Burst mode

0.86

0.73

0.86

0.89

Table 7.6.

Power eciency of the system

From table 7.6 it is seen that the LTC3555 have a bad eciency when being
powered from the USB port with no battery connected.

The eciency in this

mode is aected partly by a second switch regulator, seen in gure 2.2 on page 8,
but probably also aected by the battery charging circuits within the regulator.
When the system is powered from the battery, the eciency increases, however,
the eciency is still low in Boot and Standby mode, with eciency factor under

80%.

This could be improved if the regulation modes of the LTC3555 could be

individually selected for each of the regulators in the package.

36

Results

7.4 Conclusion
In this thesis we have presented some ideas for power saving in embedded microprocessor system and applied them to a developed hardware platform. The system
have low power modes and the user may activate them.

The current consump-

tion were hard to measure correctly and to present as some errors in the design
made components unusable and the real power consumption of the components
unknown. Initially the goal were to have a board with as much interfaces as possible to only require USB power, were shown to be a little optimistic but is possible
by removing power hungry devices, in this case, mainly the LCD. More work is
required to investigate power eciencies of the power management circuits and to
increase the power eciencies.

7.5 Problems
7.5.1

Cadstar crashes

Cadstar is the program used for design of the schematics and printed circuit board
during this thesis work. The work was done using Cadstar version 10, which were
released a month prior to the start of the thesis work. Unfortunately this version
had several bugs which were both hard to detect what caused the bug, and work
around. The major hassle during the thesis work was unexpected crashes with no
warning or explanation of the error detected. This bug would most often occur
during a change of the viewed layers.

When the user changed the layers, and

started working on the new layer, the program would crash. This was possible to
work around by saving the project directly after a change in the viewed layers,
which would prevent the program from crashing. Another cause of the program
crashing was during the conversion from schematic layout to a PCB layout.

If

a component or foot print used in the layout had a space character as the last
character of the name, the program would crash, again with no error message
explaining the fault.

7.5.2

Blind vias

When the card was manufactured it was shown that it was hard for the PCB
manufacturer to create reliable blind vias between the rst and second layer. This
resulted in three separate deliveries of the PCB. Although possible to manufacture,
it should perhaps be tried to keep blind vias down to a minimum.

7.5.3

Ethernet not working

Initially when the U-Boot application started, the DM9161 ethernet circuit was
not correctly detected. This was traced to the DM9161 not receiving a reset pulse
during initialization. When this was corrected, the chip was detected, however it
would not indicate a network link when the ethernet cable was connected to the
board.

7.6 Future work


7.5.4

37

Display not working

The LCD display have not worked reliable on this card, and many errors have been
found during development with the selected LCD display. The display is connected
to both the LCD interface of the processor and a SPI interface. Initially, the SPI
interface were created in software using drivers already present in the Linux kernel
source.

The display did not react to any congurations sent over the software

SPI interface. When the SPI interface was changed to a hardware SPI bus of the
microprocessor, a mode change was detected on the display when congurations
were sent over the SPI bus.

7.5.5

Connector problems

The connectors for the USB host interface and the external power input connector
did not t in their connections to the circuit board.

The power connector was

both mirrored and both connectors had wrong hole sizes. Also the LCD connector
was mirrored on the PCB, but successfully mounted to the PCB.
The problems with the power connector and the USB connector did not render
any problems other than modications to the components to allow mounting to
the PCB. The LCD connection though, shorted the power supplied to the LCD
to ground. Thus when an LCD display is attached to the PCB, the system did
not work.

7.5.6

LTC3555 power regulator

The design surrounding the LTC3555 regulator Integrated circuit (IC) was incorrect, the enable pins of the regulator was tied down to ground, disabling the
regulators in the IC. To work correctly the chip will require an external

I 2C

device

to send activation data to the regulator. But since the CPU is not supplied with
power, it is not possible to send this command as planned. To resolve the board to
working condition, a decision was taken to remove the possibility of enabling and
disabling the voltages of the regulator by software in the microprocessor. Hardware modications are required, the ground connection on the PCB connecting
the EN2 and EN3 pins of the LTC3555 were cut and the pins were connected to
the

3V 3LDO

power net, the schematic visible in the schematics in appendix E on

page 49 shows the unmodied circuit.

7.6 Future work


The thesis work have been successful in developing a working ARM embedded
microcomputer platform. Although the platform lacks a working LCD and Ethernet interface. If the board is to be continued, a new platform is suggested with
a rework of those interfaces. Also a change of SRAM module is suggested as the
selected part unfortunately consumed too much power than normal SRAM devices. Also the power regulation circuits needs to be looked over since the idea of
disabling the power to the CPU and surrounding components when the CPU is

38

Results

disabled did not work. Perhaps a smaller micro controller unit needs to be added
to control the power to the main CPU.
The board lacks a prototype area which is very useful to have when extending
board functions and adding new connection interfaces.
Also if a new board is built, more care should be taken to mechanical parts of
the design such as an enclosure to the board.
Ideas for further enhancements of the board depends on which features are
most wanted, to increase data processing capabilities and interface reconguration
possibilities, a Field programmable gate array (FPGA) device should be added.
Or, the board size could be shrunken allowing for hand-held operation of the
system.
Mobile SDRAM was considered in the SDRAM section 2.3.2 on page 6, but not
used in this project. By using Mobile SDRAM, power consumption will be greatly
reduced in both active and idle modes, a comparison of the power requirements of
both Mobile and standard SDRAM is presented in table 2.1 on page 6.

Bibliography
[1] Elprint AB. Elprint - capabilities.

59,

http://elprint.se/index.php/pages/

2008. [Online; accessed 5-September-2008].

[2] Atmel. AT91Bootstrap framework, 2006.


[3] Atmel.

Optimizing Power Consumption of AT91SAM9261-based Systems,

2006.

[4] Atmel. 32-megabit 2.7-volt DataFlash , 2008.


Atmel pll lft lter calculator.
http://www.atmel.com/dyn/
resources/prod_documents/PLL_LFT_filter_CALCULATOR_AT91.zip,

[5] Atmel.

2008. [Online; accessed 24-September-2008].


[6] Gregg Castellucci.

Monolithic buck regulator operates down to 1.6v input.

Linear Technology Magazine, XVI(3):40, 2006.


[7] RMII consortium. RMII Specication. RMII Consortium, 1998.
[8] Toppoly Optoelectronics Corp. TD028TTEC1 Software Design Guide, 2007.
[9] Atmel Corporation. AT91 ARM Thumb Microcontrollers AT91SAM9263 Preliminary Datasheet, 2007.
[10] Atmel Corporation. AT91SAM9263-EK Evaluation Board User Guide, 2007.
[11] Atmel Corporation.

AT91SAM9263 Microcontroller Schematic Check List,

2007.
[12] National Semiconductor Corporation. LP2980-ADJ Micropower SOT, 50 mA
Ultra Low-Dropout Adjustable Voltage Regulator Datasheet, 2000.
[13] National Semiconductor Corporation. LM2731 0.6/1.6 MHz Boost Converters
With 22V Internal FET Switch, 2007.
[14] TPO

Display

corporation.

TFT

LCD

Specication

Model

Name:

TD028TTEC1, Unknown.
[15] Davicom. DM9161 10/100 Mbps Fast Ethernet Physical Layer TX/FX Single
Chip Transceiver, 2006.
39

40

Bibliography

[16] Davicom. DM9161A 10/100 Mbps Fast Ethernet Physical Layer Single Chip
Transceiver, 2007.
[17] Davicom. DM9161B 10/100 Mbps Fast Ethernet Physical Layer Single Chip
Transceiver, 2008.
[18] Openmoko Docs. root/trunk/src/target/kernel/patches/gta01-jbt6k74.patch.

http://http://docs.openmoko.org/trac/browser/trunk/src/target/
kernel/patches/gta01-jbt6k74.patch?rev=1883, September 2008.

[19] Andrew Victor et al. At91 linux 2.6 patches, v2.6.25.

za/AT91RM9200/2.6/2.6.25-at91.patch.gz,

http://maxim.org.

September 2008.

Linux kernel v2.6.25. http://www.eu.kernel.org/


pub/linux/kernel/v2.6/linux-2.6.25.tar.bz2, 2008. [Online; accessed

[20] Linux Torvalds et al.


28-August-2008].

[21] Scott Gary. Optimizing power consumption in embedded dsp apps.

//www.ddj.com/embedded/193400975,

[22] Zi

Davis

Enterprise

linuxdevices.com,

Holdings

Inc.

http:

October 2006.
Linuxdevices.com.

http://www.

2008. [Online; accessed 27-August-2008].

[23] Texas Instruments. ADS7846: TOUCH SCREEN CONTROLLER, 2005.


[24] Intel.

LXT970 LXT971 3.3V Dual-speed Fast Ethernet PHY Transceiver,

2002.
[25] ISSI.

512K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

WITH 3.3V SUPPLY, 2005.


Pcb design tutorial.
http://www.alternatezone.com/
electronics/files/PCBDesignTutorialRevA.pdf, 2004. [Online; accessed

[26] David L. Jones.

18-September-2008].
[27] Linuxdevices.com.

Snapshot of the embedded linux market  april, 2007.

http://linuxdevices.com/articles/AT7065740528.html,

2007.

[Online;

accessed 27-August-2008].
[28] ARM Ltd. Arm powered products.

solutions/app.html,

http://www.arm.com/markets/mobile_

2008. [Online; accessed 27-August-2008].

[29] ARM Ltd. Licensing arm processor technology.

licensing/index.html,

http://arm.com/products/

August 2008. [Online; accessed 27-August-2008].

[30] Micron. Synchronous DRAM MT48LC64M4A2, 1999.

http://wiki.openmoko.org/index.
php?title=Neo_FreeRunner_Hardware&oldid=48606, 2008. [Online; ac-

[31] OpenMoko. Neo freerunner hardware.


cessed 27-August-20080].

[32] National Semiconductors. AN-1126 BGA (Ball Grid Array), 2002.

Bibliography

41

[33] National Semiconductors. DP83848C PHYTER - Commercial Temperature


Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver, 2008.
[34] Linear technology corporation. LTC4066/LTC4066-1 Datasheet, 2005.
[35] Linear technology corporation. LTC3555/LTC3555-1 Datasheet, 2007.
[36] Vasanth Venkatachalam and Michael Franz. Power reduction techniques for
microprocessor systems. ACM Comput. Surv., 37(3):195237, 2005.
Iphone  wikipedia, the free encyclopedia.
http://en.
wikipedia.org/w/index.php?title=IPhone&oldid=233574629, 2008. [On-

[37] Wikipedia.

line; accessed 27-August-2008].

Appendix A

Acronyms
ARM Advanced Risc Machine
BGA Ball Grid Array
CPU Central Processing Unit
ELCC Enea Linux Competence Center
GPIO General purpose input/output
I 2C

Inter Integrated Circuit

IC Integrated circuit
LCD Liquid crystal display
LDO low dropout regulator
MCU Micro Controller Unit
MII MIIMedia Independent Interface
MMU Memory Management Unit
NSMD Non Solder Mask Dened
PCB Printed Circuit Board
PLL Phase locked loop
PMC Power Management Controller
PPC Power PC
RAM Random Access Memory
RMII Reduced Media Independent Interface
43

44

ROM Read Only Memory


SBC single board computer
SDRAM Synchronous Dynamic Random Access Memory
SMD Solder Masked Dened
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
USB Universal Serial Bus
DMA Direct memory access
FPGA Field programmable gate array

Acronyms

Appendix B

Jumper conguration
The jumpers regarding voltages in table B.1 are suitable for current measurements
of the connected part of the circuit.
Jumper

Function

J2

VDD PLLA, PLLB, OSC

closed

J3

VDD IOP0

closed

J4

VDD IOP1

closed

J5

VDD IOM0

closed

J6

VDD IOM1

closed

J7

VDD Core

closed

J8

VDD

closed

J10

JTAGSEL

open

J11

VDD LCD Back light

open

J12

VDD USB +5V regulator

open

J13

DataFlash write protect

open

J14

VDD LDO 3V3

closed

J15

Input voltage from USB

closed

J16

Boot mode select

open

J17

VDD 3V3

closed

J18

LTC3555 DVCC in

closed

J19

VDD SDRAM

closed

1.2V
Backup 1.2V

Table B.1.

Jumper conguration

45

Appendix C

Connector specication
Connector

Function

CONN1

Ethernet jack

CONN2

Dual USB host connector

CONN3

SD Card socket

CONN4

JTAG

CONN5

LCD FH23

CONN6

External voltage

P1

USB device connector

P2

Touch pad connector

P3

Battery connector

P5

I2C

P9

LCD Header

P12

External IO, Serial Debug

Table C.1.

Connector specication

46

Appendix D

HW sketch

47

48

Sketch of system

HW sketch

Figure D.1.

Appendix E

HW schematics

49

50
HW schematics

Figure E.1.

Memory bus and CPU power

51

Figure E.2.

CPU Ports

52
HW schematics

Figure E.3.

Power supply

53

Figure E.4.

Memories

54
HW schematics

Figure E.5.

Interfaces and oscillators

55

Figure E.6.

Ethernet

56
HW schematics

Figure E.7.

LCD display, IO header

Appendix F

Boot messages
F.1 Boot ROM
RomBOOT
>

F.2 Bootstrap
Start

AT91Bootstrap

for

E1219A . . .

F.3 U-Boot
UBoot

1 . 1 . 5 g 4 8 d 9 f 3 c 7 d i r t y

DRAM:

6 4 MB

( Jul

23

D a t a F l a s h : AT45DB321
Nb p a g e s :
Page

8192

Size :

528

S i z e= 4 3 2 5 3 7 6

bytes

Logical

address :

0 xC0000000

Area

0:

C0000000

to

C0003FFF

Area

1:

C0004000

to

C0007FFF

Area

2:

C0008000

to

C0037FFF

Area

3:

C0038000

to

C041FFFF

In :

(RO)
(RO)

serial

Out :

serial

Err :

serial

DM9161A PHY D e t e c t e d
No

link

MAC:

error

during

RMII

initialization
57

2008

17:48:33)

58

Boot messages

Hit

any

key

## B o o t i n g

to

stop

image

at

Image Name :
Image

autoboot :
20000000

Linux

Type :
Size :

Load

Address :

20008000

Point :

20008000

Verifying

1374652

Checksum

2.6.25

ARM L i n u x

Data
Entry

3
...

Kernel

Image

Bytes =

...

( uncompressed )

1 . 3 MB

OK

OK
Starting

kernel

...

F.4 Linux Kernel


Uncompressing

Linux

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
done ,
Linux

booting

version

Debian

3) )

4.2.3

ARM926EJS

CPU :

the

2.6.25

kernel .
( bobo@hp7300 )

#41 Thu

[41069265]

Jul

( gcc

24

version

14:41:58

revision

4.2.3

CEST 2 0 0 8

(ARMv5TEJ) ,

cr

=00053177
Machine :

ELCC E1219A

Ignoring

unrecognised

Memory

policy :

Clocks :
CPU0 :

CPU 1 9 6 MHz,

D VIVT

CPU0 :

CPU0 :

D cache :
1

Kernel
PID

writeback

main

1 6 . 0 0 0 MHz

cache

16384

bytes ,

associativity

4,

32

byte

lines ,

16384

bytes ,

associativity

4,

32

byte

lines ,

zonelists
pages :

command
160

hash

gpio
table

Console :

[ tty0 ]

console

[ ttyS0 ]
cache

in

Zone

order ,

mobility

grouping

on .

16256
line :
irqs

r o o t =/d e v / s d a 2
in

entries :

colour

console
Dentry

cache

sets

Total
AT91 :

Data

98 MHz,

sets

128
Built

0 x54410008

master

w r i t e b a c k

cache :

128

tag

ECC d i s a b l e d ,

dummy

r o o t d e l a y =5

banks
256

device

( order :

8,

1024

bytes )

80 x30

enabled
enabled

hash

table

entries :

8192

( order :

3,

32768

bytes )
I n o d e c a c h e

hash

table

entries :

4096

( order :

2,

16384

bytes

)
Memory :

64MB = 64MB t o t a l

Memory :

6 2 0 1 2KB a v a i l a b l e

( 2 5 0 0K c o d e ,

)
Mountc a c h e

hash

table

entries :

512

2 2 3K d a t a ,

1 2 0K

init

F.4 Linux Kernel


CPU :

Testing

59

write

net_namespace :
NET :

Registered

AT91 :

Power

AT91 :

Starting

SCSI

buffer

152

protocol

Management
after

subsystem

coherency :

ok

bytes
family

( with

user

16

slow

clock

mode )

reset

initialized

usbcore :

registered

new

interface

driver

usbfs

usbcore :

registered

new

interface

driver

hub

usbcore :

registered

new

device

NET :
IP

Registered

route

cache

protocol
hash

driver

family

table

usb

entries :

1024

( order :

0,

4096

bytes )
TCP

established

hash

table

entries :

2048

( order :

2,

16384

bytes )
TCP b i n d
TCP :

hash

Hash

TCP r e n o

entries :

configured

2048

( order :

( established

1,

8192

2048

bytes )

bind

2048)

registered

NetWinder
JFFS2

table

tables

Floating

version

Point

E m u l a t o r V0 . 9 7

c 2001 2006
(NAND)

2.2.

io

scheduler

noop

io

scheduler

anticipatory

atmel_lcdfb

( double

precision )

Red Hat ,

Inc .

registered
registered

atmel_lcdfb . 0 :

backlight

atmel_lcdfb . 0 :

1 5 0 KiB

( default )
control

is

not

available
atmel_lcdfb
( mapped

at

atmel_lcdfb
mapped

atmel_lcdfb . 0 :

at

frame

buffer

at

23 d40000

ffc00000 )
c485c000 ) ,

atmel_usart . 0 :

ttyS0

fb0 :

irq

Atmel LCDC a t

0 x00700000

26

a t MMIO 0 x f e f f e e 0 0

( i r q = 1)

is

a t MMIO 0 x f f f 8 c 0 0 0

( i r q = 7)

is

ATMEL_SERIAL
atmel_usart . 1 :

ttyS1

ATMEL_SERIAL
brd :

module

loop :

loaded

module

loaded

MACB_mii_bus :

probed

eth0 :

Atmel MACB a t

eth0 :

a t t a c h e d PHY d r i v e r

0 xfffbc000

phy_addr= f f f f f f f f : 0 0 ,
usbcore :
Driver

atmel_spi
irq

needs

new

(00:00:00:00:00:00)
( mii_bus :

i r q =1)
interface

updating

atmel_spi . 0 :

21

driver

please

use

kaweth
b u s_ t yp e

methods

Atmel

SPI

Controller

at

0 xfffa4000

Atmel

SPI

Controller

at

0 xfffa8000

14)

atmel_spi
irq

registered

' sd '

irq

[ Davicom DM9161E ]

atmel_spi . 1 :

15)

at91e1219a_spi_init :
at91e1219a_spi_probe :
No Bus : s p i 2

AT91 E1219A INIT TEST


SPI2

d e t e c t e d <7>PM:

Adding

info

for

60

Boot messages

jbt_init :

entering

jbt_probe :

entering

jbt6k74_enter_state :
standby_to_sleep :
sleep_to_normal :

e n t e r i n g ( o l d _ s t a t e =0 ,

entering

jbt_init_regs :

entering

jbt_init_regs :

e n t e r i n g VGA mode

jbt6k74_display_onoff :

entering

usbmon :

available

debugfs

is

not

at91_ohci

at91_ohci :

AT91 OHCI

at91_ohci

at91_ohci :

new USB b u s

number
at91_ohci

at91_ohci :

usb1 :

configuration

hub

0:1.0:
1 0:1.0:

Initializing
1 2:

usb

1 2:

scsi0

detected

ports

full

configuration

Storage

PS/ 2

from

choice

driver . . .

device

#1 c h o s e n

emulation

at91_udc

support

mouse

spi0 . 3 :
ADS784x

r t c a t 9 1 s a m 9

for

new

version

using

at91_ohci

and

as

from

USB Mass

interface

choice

Storage

driver

devices

usb s t o r a g e

registered .

3 May 2 0 0 6

device

g p i o k e y s

input :

Storage

s p e e d USB

USB Mass

ads7846

bus

SCSI

input :

assigned

i o mem 0 x 0 0 a 0 0 0 0 0

found

registered

mice :

29 ,

#1 c h o s e n

USB hub

usbcore :
udc :

irq

USB Mass

new

address
usb

registered ,

usb
hub

n e w _ s t a t e =2)

entering

common

for

all

mice

/ c l a s s / input / input0

touchscreen ,
Touchscreen

irq

as

31

/ c l a s s / input / input1

at91_rtt . 0 :

rtc

core :

at91_rtt . 0 :

rtc0 :

registered

at91_rtt

as

rtc0
r t c a t 9 1 s a m 9
i2c

/ dev

entries

i 2 c g p i o

i 2 c g p i o :

at91sam9_wdt :
TCP c u b i c

SET TIME !

driver
using

invalid

pins

timeout

68

(SDA)

( must

be

Registered

protocol

family

NET :

Registered

protocol

family

17

RPC :

Registered

udp

transport

module .

RPC :

Registered

tcp

transport

module .

r t c a t 9 1 s a m 9
hardware

at91_rtt . 0 :

hctosys :

unable

to

clock

5 sec
is

before

mounting

root

device . . .

r e a d o n l y

mmc0 :

card

mmc0 :

new SD c a r d

mmcblk0 :

69

between

( SCL )
1

and

read

the

registered

NET :

Waiting

and

mmc0 : a 5 b c

at

address

SD064

a5bc

6 0 9 2 8 KiB

( ro )

16)

F.5 Init system

61

mmcblk0:<7>mmc0 :

starting

CMD18 a r g

00000000

flags

000000

b5
p1
scsi
sd

D i r e c t A c c e s s

0:0:0:0:

1 . 1 3 PQ :

0 ANSI :

0:0:0:0:

[ sda ]

Kingston

DataTraveler

II

0 CCS

1398784

512 b y t e

hardware

sectors

( 7 1 6 MB

)
sd

0:0:0:0:

[ sda ]

Write

sd

0:0:0:0:

[ sda ]

Assuming

Protect

sd

0:0:0:0:

[ sda ]

1398784

is

drive

off

cache :

512 b y t e

write

hardware

through

sectors

( 7 1 6 MB

)
sd

0:0:0:0:

[ sda ]

Write

sd

0:0:0:0:

[ sda ]

Assuming

sda :
sd

sda1

sda2

0:0:0:0:

EXT2 f s

Protect

is

drive

off

cache :

write

through

sda3

[ sda ]

warning :

Attached
mounting

SCSI

removable

unchecked

fs ,

disk

running

e2fsck

is

recommended
VFS :

Mounted

Freeing

root

init

( ext2

memory :

filesystem ) .

1 2 0K

F.5 Init system


init

started :

BusyBox

multic a l l
starting
Startup

pid

Setting
Setting
No NFS
cat :

proc

network

' / e t c / i n i t . d/ rcS '

'/ etc / version ' :

No

such

n u x.
847 ,

login :

tty

' ':

'/ sbin / getty '

root

to
i

n u x.

login [847]:

root

login

on

' ttyS0 '

/ proc / cpuinfo

Processor

CEST)

mounted

open

pid

armlinux

' ':

to
i

11:39:02

filesystem . . .

up

starting

Welcome

tty

logging

can ' t

(2008 06 25

running . . .

up

server

Welcome

# cat

826 ,

script

Mounting

v1 . 6 . 0

binary

ARM926EJS

rev

( v5l )

file

or

directory

62

Boot messages

BogoMIPS

97.68

Features

swp

0 x41

CPU a r c h i t e c t u r e :

5TEJ

CPU i m p l e m e n t e r

half

CPU v a r i a n t

0 x0

CPU p a r t

0 x926

CPU

revision

fastmult

Cache

type

w r i t e b a c k

Cache

clean

cp15

Cache

lockdown

format C

Cache

format

Harvard

size

16384

assoc

line

32

sets

length

128

size

16384

D assoc
D

line

sets

length

c7

edsp

ops

32

128

Hardware

ELCC E1219A

Revision

0000

Serial

0000000000000000

# reboot
The

system

is

going

# S e n d i n g SIGTERM t o
Sending

down NOW!
all

SIGKIRequesting

Restarting

processes
system

reboot

system .

RomBOOT
>S t a r t

AT91Bootstrap

for

E1219A . . .

java

Appendix G

LTC3555 driver
/* Module for controlling the LTC3555 switch regulator modes
*
*
* read from /proc/ltc3555_read,it will tell the current operating mode
* of the device.
* Write to /proc/ltc3555_write, selections are 00, 01, 10, 11
*
*|-----+-----+--------------|
*| PB4 | PB5 |
|
*|-----+-----+--------------|
*|
1 | 1 | Burst
|
*|
0 | 1 | Forced Burst |
*|
1 | 0 | LDO
|
*|
0 | 0 | Pulse Skip
|
*|-----+-----+--------------|
*
*
* 2008-06-26 bo.svangard@enea.com
*
*/
#include
#include
#include
#include
#include
#include
#include
#include

<linux/init.h>
<linux/module.h>
<linux/delay.h>
<asm/gpio.h>
<linux/fs.h>
<asm/uaccess.h>
<linux/proc_fs.h>
<linux/platform_device.h>

#define PROCFS_MAX_SIZE 1024


63

64

LTC3555 driver

static char procfs_buffer[PROCFS_MAX_SIZE];


MODULE_AUTHOR("Bo Svangrd");
MODULE_LICENSE("GPL");
static struct proc_dir_entry *Proc_File;
static unsigned long procfs_buffer_size = 0;
/* Globals */
unsigned int PB4 = AT91_PIN_PB4;
unsigned int PB5 = AT91_PIN_PB5;
static int ltc3555_remove(struct platform_device *dev)
{
printk(KERN_DEBUG "LTC3555: Removing\n");
return 0;
}
static int ltc3555_suspend(struct platform_device *dev, pm_message_t state)
{
printk(KERN_DEBUG "LTC3555: Suspending, Burst mode selected\n");
at91_set_gpio_value(PB4, 0);
at91_set_gpio_value(PB5, 0);
return 0;
}
static int ltc3555_resume(struct platform_device *dev)
{
printk(KERN_DEBUG "LTC3555: Wake up\n");
return 0;
}
static int __init ltc3555_probe(struct platform_device *pdev)
{
/* assume LTC3555 is present in system */
return 0;
}
static struct platform_driver ltc3555_driver = {
.driver = {
.name = "ltc3555",
.owner = THIS_MODULE,
},
.probe = ltc3555_probe,

65
.remove = __devexit_p(ltc3555_remove),
.suspend = ltc3555_suspend,
.resume = ltc3555_resume,
};
int ltc3555_gpio_read_proc(char *buf, char **start, off_t offset,
int count, int *eof, void *data)
{
int len = 0;
if (at91_get_gpio_value(PB4)) {
if (at91_get_gpio_value(PB5) == '1') {
/* 1 1 -- Burst mode */
len += sprintf(buf + len, "LTC3555: Burst mode\n");
} else {
/* 1 0 -- LDO mode */
len += sprintf(buf + len, "LTC3555: LDO mode\n");
}
} else if (at91_get_gpio_value(PB5)) {
/* 0 1 -- Forced burst mode */
len += sprintf(buf + len, "LTC3555: Forced burst mode\n");
} else {
/* 0 0 -- Pulse skip mode */
len += sprintf(buf + len, "LTC3555: Pulse skip mode\n");
}
return len;
};
/*
* This function is called with the /proc file is written
*
*/
int ltc3555_gpio_write(struct file *file, const char *buffer,
unsigned long count, void *data)
{
/* get buffer size */
procfs_buffer_size = count;
if (procfs_buffer_size > PROCFS_MAX_SIZE) {
procfs_buffer_size = PROCFS_MAX_SIZE;
}
/* write data to the buffer */
if (copy_from_user(procfs_buffer, buffer, procfs_buffer_size)) {
return -EFAULT;
}

66

LTC3555 driver

/*|-----+-----+--------------|
*| PB4 | PB5 |
|
*|-----+-----+--------------|
*|
1 | 1 | Burst
|
*|
0 | 1 | Forced Burst |
*|
1 | 0 | LDO
|
*|
0 | 0 | Pulse Skip
|
*|-----+-----+--------------|
*/
if (buffer[0] == '1') {
if (buffer[1] == '1') {
/* 1 1 -- Burst mode */
printk(KERN_DEBUG "LTC3555: Burst mode\n");
at91_set_gpio_value(PB4, 1);
at91_set_gpio_value(PB5, 1);
} else {
/* 1 0 -- LDO mode */
printk(KERN_DEBUG "LTC3555: LDO mode\n");
at91_set_gpio_value(PB4, 1);
at91_set_gpio_value(PB5, 0);
}
} else if (buffer[1] == '1') {
/* 0 1 -- Forced burst mode */
printk(KERN_DEBUG "LTC3555: Forced burst mode\n");
at91_set_gpio_value(PB4, 0);
at91_set_gpio_value(PB5, 1);
} else {
/* 0 0 -- Pulse skip mode */
printk(KERN_DEBUG "LTC3555: Pulse skip mode\n");
at91_set_gpio_value(PB4, 0);
at91_set_gpio_value(PB5, 0);
}
return procfs_buffer_size;
}
static int modinit(void)
{
int ret;
at91_set_gpio_output(PB4, 1);
at91_set_gpio_output(PB5, 1);
printk(KERN_ALERT "Loading LTC35555 GPIO Mode control\n");
ret = platform_driver_probe(&ltc3555_driver, ltc3555_probe);

67
create_proc_read_entry("ltc3555_read", 0, NULL,
ltc3555_gpio_read_proc, NULL);
Proc_File = create_proc_entry("ltc3555_write", 0644, NULL);
if (Proc_File == NULL) {
remove_proc_entry("ltc3555_write", NULL);
printk(KERN_ALERT
"Error: could not init /proc/ltc3555_write\n");
return -ENOMEM;
}
Proc_File->write_proc = ltc3555_gpio_write;
Proc_File->owner = THIS_MODULE;
Proc_File->mode = S_IFREG | S_IRUGO;
Proc_File->uid = 0;
Proc_File->gid = 0;
Proc_File->size = 37;
return ret;
};
static void modexit(void)
{
printk(KERN_ALERT "Unloading LTC3555 GPIO Mode control\n");
platform_driver_unregister(&ltc3555_driver);
remove_proc_entry("ltc3555_read", NULL);
remove_proc_entry("ltc3555_write", NULL);
}
module_init(modinit);
module_exit(modexit);