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MC14042B

Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic “0” state, data is transferred
during the low clock level, and when the polarity input is in the logic
“1” state the transfer occurs during the high clock level.

http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648

Features









Buffered Data Inputs
Common Clock
Clock Polarity Control
Q and Q Outputs
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
These Devices are Pb−Free and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable

MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter

Unit

−0.5 to +18.0

V

−0.5 to VDD + 0.5

V

Input or Output Current
(DC or Transient) per Pin

±10

mA

PD

Power Dissipation,
per Package (Note 1)

500

mW

TA

Ambient Temperature Range

−55 to +125

°C

Tstg

Storage Temperature Range

−65 to +150

°C

TL

Lead Temperature
(8−Second Soldering)

260

°C

VDD
Vin, Vout
Iin, Iout

DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)

MC14042BCP
AWLYYWWG
1
16

SOIC−16
D SUFFIX
CASE 751B

14042BG
AWLYWW
1

A
WL
YY, Y
WW
G

= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator

ORDERING INFORMATION
Value

Symbol

16

See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.

Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.

© Semiconductor Components Industries, LLC, 2013

April, 2013 − Rev. 8

1

Publication Order Number:
MC14042B/D

com 2 .MC14042B PIN ASSIGNMENT Q3 1 16 VDD Q0 2 15 Q3 Q0 3 14 D3 D0 4 13 D2 CLOCK 5 12 Q2 POLARITY 6 11 Q2 D1 7 10 Q1 VSS 8 9 Q1 TRUTH TABLE Clock Polarity Q 0 1 1 0 0 0 1 1 Data Latch Data Latch LOGIC DIAGRAM 5 D0 LATCH 1 4 CLOCK POLARITY Q0 2 Q0 3 6 D1 LATCH 2 7 Q1 10 Q1 9 D2 LATCH 3 13 VDD = PIN 16 VSS = PIN 8 Q2 11 Q2 12 D3 LATCH 4 14 Q3 1 Q3 15 http://onsemi.

002 0.004 0.5 or 4.05 0.0 10 15 0.0 mA/kHz) f + IDD 2.0 10 15 − − − 1.0 11 2.0 4. 4.2 – 0.6 – 4.75 1.1 − ± 0.64 – 1.95 9.0 − − − 0.5 Vdc) (VOH = 13.9 2.4 0.36 – 0.0 10 15 − − − 0. and k = 0. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.0 − − − 1.5 − − pF Quiescent Current (Per Package) IDD 5.8 − − − − – 1.3 – 3.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOL = 0. http://onsemi.64 1.0 − − − 30 60 120 mAdc IT 5.95 14. V = (VDD − VSS) in volts.3 3.0 10 15 − − − 4.2 − − − − – 2.0 10 15 3.0 10 15 − − − 1.0 mA/kHz) f + IDD IT = (3.0 10 15 Vin = 0 or VDD (VO = 0.25 − − − 3.4 – 0.0 11 − − − 3.4 − − − − IOL 5.25 – 8.4 Vdc) (VOL = 0.05 0.0 2.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.4 – 4.6 Vdc) (VOH = 9.0 2.0 “1” Level VIH 5.006 1.0 − − − 2.75 5.88 – 2.25 8.0 11 − − − 5.0 – 0.6 4.50 6. The formulas given are for the typical characteristics only at 25_C.5 Vdc) VIL 5.5 or 1.95 − − − 4.0 4.1 − ±1.5 Vdc) (VO = 1.5 3.com 3 mAdc .4 − − − mAdc Input Current Iin 15 − ±0.0 5.0 10 15 – 3.0 7.5 Vdc) (VOH = 4.36 0.004.5 7. CL in pF. 3.7 – 0.0 4.50 8.05 0.0 10 15 4.00001 ±0.95 5.0 or 9.05 0.5 3.95 14. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk where: IT is in mA (per package). Per Package) (CL = 50 pF on all outputs all buffers switching) IOH Vdc Vdc mAdc IT = (1.MC14042B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol − 55_C 25_C 125_C VDD Vdc Min Max Min Typ (Note 2) Max Min Max Unit “0” Level VOL 5.25 4.05 0.5 Vdc) (VO = 9.5 3.05 Vdc “1” Level VOH 5.0 or 1.5 7.95 − − − Vdc Input Voltage “0” Level (VO = 4.5 Vdc) Source Sink Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent.5 7.05 − − − 0 0 0 0.0 4.51 1.95 9.88 2.9 – 2.5 or 0.0 4.5 or 13.5 Vdc) (VOL = 1.95 9. f in kHz is input frequency.0 Vdc) (VO = 1.8 − − − 0.0 mA/kHz) f + IDD IT = (2.05 0.51 – 1.05 − − − 0.0 Vdc) (VO = 13.95 14.2 − − − 0.

Q tPLH.7 ns/pF) CL + 135 ns tPLH. http://onsemi. ORDERING INFORMATION Package Shipping† MC14042BCPG PDIP−16 (Pb−Free) 500 Units / Rail MC14042BDG SOIC−16 (Pb−Free) 48 Units / Rail SOIC−16 (Pb−Free) 2500 Units / Tape & Reel Device NLV14042BDG* MC14042BDR2G NLV14042BDR2G* †For information on tape and reel specifications.55 ns/pF) CL + 9. tPHL = (0.0 10 15 50 30 25 0 0 0 − − − Unit ns no ns ns tTLH.MC14042B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF.5 ns/pF) CL + 35 ns tPLH. TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH.0 10 15 100 50 40 50 25 20 − − − 5.0 10 15 300 100 80 150 50 40 − − − 5. tTHL th Setup Time VDD ms ns tsu ns 5. BRD8011/D.0 5.5 ns/pF) CL + 25 ns tTLH. tPHL = (0. tTHL = (1.com 4 .5 ns/pF) CL + 35 ns tPLH.75 ns/pF) CL + 12. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements.5 ns tTLH. D to Q.0 10 15 − − − 220 90 60 440 180 120 5.7 ns/pF) CL + 135 ns tPLH. tPHL = (1. Q tPLH.0 10 15 − − − − − − 15 5.0 10 15 − − − 100 50 40 200 100 80 5. including part orientation and tape sizes. tPHL = (0.66 ns/pF) CL + 57 ns tPLH.66 ns/pF) CL + 57 ns tPLH. The formulas given are for the typical characteristics only at 25_C. tPHL = (0. tPHL Clock Pulse Width tWH Clock Pulse Rise and Fall Time Hold Time Min Typ (Note 6) Max 5. tTHL = (0. tPHL = (1. tTHL = (0. please refer to our Tape and Reel Packaging Specifications Brochure. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. AEC−Q100 Qualified and PPAP Capable.0 4. tPHL Propagation Delay Time.0 10 15 − − − 220 90 60 440 180 120 5. tTHL Propagation Delay Time. Clock to Q.5 ns tTLH. 6.

AC and Power Dissipation Test Circuit and Timing Diagram (Data to Output) VDD 16 PULSE GENERATOR 1 5 PULSE GENERATOR 2 4 CLOCK 6 POLARITY D0 7 D1 13 D2 14 D3 NOTE: CL connected to output under test. VSS tTHL Figure 1.com 5 tTHL tPHL 90% 10% 8 50% 10% tTLH Q OUTPUT 10% 50% tTLH .G. AC Test Circuit and Timing Diagram (Clock to Output) http://onsemi. each output is loaded with capacitance CL. 1 10% tWH 20 ns 90% 50% DATA INPUT P. 2 tsu th tPLH Q OUTPUT 90% 50% 10% *Input clock rise time is 20 ns except for maximum rise time test. Figure 2.G. 20* ns 8 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 2 3 10 9 11 12 1 15 VSS 20 ns 90% 50% CLOCK INPUT P.MC14042B VDD 1 f 16 20 ns 5 6 4 PULSE GENERATOR 1 7 13 2 3 10 9 11 12 1 15 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 CLOCK POLARITY D0 D1 D2 14 D3 20 ns 90% 50% DATA INPUT tPLH tPHL 90% Q OUTPUT For Power Dissipation test.

21 0.040 0. CONTROLLING DIMENSION: INCH.015 0.39 0.040 MILLIMETERS MIN MAX 18.MC14042B PACKAGE DIMENSIONS PDIP−16 P SUFFIX PLASTIC DIP PACKAGE CASE 648−08 ISSUE T NOTES: 1.130 0.020 0.com 6 DIM A B C D F G H J K L M S INCHES MIN MAX 0.44 0.305 0_ 10 _ 0. 1982.54 BSC 1.55 6.250 0.100 BSC 0.5M.145 0.53 1.295 0. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.015 0. ROUNDED CORNERS OPTIONAL.02 1.770 0.77 2. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.270 0.008 0. 3.80 3.35 6.050 BSC 0.175 0.50 7.70 0.74 0_ 10 _ 0. 4.021 0.110 0.80 19.38 2.30 7.740 0.69 4.51 1.85 3. 2.27 BSC 0.010) M T A M http://onsemi.25 (0.01 . −A− 16 9 1 8 B F C L S −T− H SEATING PLANE K G D M J 16 PL 0.

com/site/pdf/Patent−Marking. and other intellectual property. 2.15 (0. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application. even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC reserves the right to make changes without further notice to any products herein.27 BSC 0. intended.20 0.35 1. 9 −B− 1 P 8 PL 0.00 1.006) PER SIDE.80 6. Denver.80 4.127 (0.010 0.35 0. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe.O.009 0_ 7_ 0.00 3. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Buyer shall indemnify and hold SCILLC and its officers. trademarks. SCILLC owns the rights to a number of patents.27 PITCH 8 9 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries.229 0. DIMENSIONING AND TOLERANCING PER ANSI Y14.onsemi.com 7 ON Semiconductor Website: www. copyrights.019 16 PL 0. costs. SCILLC is an Equal Opportunity/Affirmative Action Employer.25 0_ 7_ 5. any claim of personal injury or death associated with such unintended or unauthorized use. Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi. or other applications intended to support or sustain life. LLC (SCILLC). SCILLC makes no warranty.010) M T B S A S SOLDERING FOOTPRINT 8X 6.054 0.050 BSC 0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.58 1.com Order Literature: http://www.157 0.pdf.25 0. Box 5163.40 16X 1 1.008 0.75 0.12 16 16X 0.150 0.onsemi.068 0.25 (0. 3. or authorized for use as components in systems intended for surgical implant into the body. and reasonable attorney fees arising out of. 4. including without limitation special.25 1.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.014 0. and specifically disclaims any and all liability. affiliates.19 0. employees.004 0.016 0. and expenses.com N.40 1.019 0. and distributors harmless against all claims.393 0. directly or indirectly. CONTROLLING DIMENSION: MILLIMETER. damages. 1982. please contact your local Sales Representative MC14042B/D . nor does SCILLC assume any liability arising out of the application or use of any product or circuit. consequential or incidental damages. trade secrets. Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.386 0. or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. SCILLC products are not designed.50 INCHES MIN MAX 0.244 0.49 0.009 0.onsemi. representation or guarantee regarding the suitability of its products for any particular purpose.10 0. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.25 0. subsidiaries.MC14042B PACKAGE DIMENSIONS SOIC−16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B−05 ISSUE K −A− 16 NOTES: 1. This literature is subject to all applicable copyright laws and is not for resale in any manner. MAXIMUM MOLD PROTRUSION 0.80 10. A listing of SCILLC’s product/patent coverage may be accessed at www. SCILLC does not convey any license under its patent rights nor the rights of others. including “Typicals” must be validated for each customer application by customer’s technical experts. 5.com/orderlit For additional information. All operating parameters.5M.049 0.