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International Journal of Contemporary Research in Engg. and Tech. Vol. 1, No.

1, 2011 69
* School of Electronics, CDAC, Noida, U.P.
Implementation and Verification of TCAM using
System Verilog
Vineet Dhingra and Arti Noor*
Abstract
Ternary Content Addressable Memories (TCAM) are the memories that search the
data on the basis of content stored in them. They are one level higher than Content
Addressable Memory (CAM) because they can search unknown bits also i.e. ternary
states. If a match is found, it returns the address of the data, unlike RAM, in which
data is returned for a given address. TCAM is used in network routers, ATM switch,
Cache Tag, data compression. The present paper contributes to test a TCAM cell
for its search operation and further its verification environment is created using
SystemVerilog.
Keyword: RAM, CAM, TCAM, System Verilog, Verification environment
INTRODUCTION
A
CAM (Content Addressable
Memory) is a special type of
storage device. Unlike traditional
storage devices (SRAM’s), in CAMs, the
operating system provides the data and the
CAM returns a list of addresses where the
data is stored.
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It searches the entire
memory concurrently in single operation
and is much faster than the SRAM cell,
which does it sequentially. The CAM makes
use of SRAM cell but with a different
searching mechanism. The para-meters of
SRAM cell used are calculated and listed
below in Table I.
CAMs can be divided into two categories:
(i) binary CAMs and (ii) ternary CAMs
(TCAMs).A binary CAM can store and
search binary words i.e. ‘0’s and ‘1’s. Thus,
binary CAMs are suitable for applications
that require only exact -match searches. A
more powerful and feature-rich TCAM can
store and search ternary states (‘1’, ‘0’, and
‘X’). The state ‘X’, also called ‘mask’ or
Table I. Measurement Results of SRAM
Parameters at 180nm
Parameters Value
SNM 300mV
CR 1.5
PR 1
DRV 0.1 V
70 International Journal of Contemporary Research in Engg. and Tech. Vol. 1, No. 1, 2011
‘don’t care’, can be used as a wild card
entry to perform partial matching.
CAM-based table lookup is very fast
due to the parallel nature of the SEARCH
operation.
1
The phenomenal growths in the
number of Internet users and the increasing
popularity of bandwidth-hungry real-time
applications have resulted in a demand for
very high-speed networks. A CAM can be
used as a co-processor for the network
processing unit to off load the table lookup
tasks.
charged to VDD. Finally, the search key
bit and its complementary value are placed
on SL1 and SL1c, respectively. If the search
key bit is identical to the stored value
(SL1=BL1, SL1c=BL1c), both ML-to -GND
pull-down paths remain ‘OFF’, and the ML
remains at VDD indicating a “match”.
Otherwise, if the search key bit is different
from the stored value, one of the pull-down
paths conducts and discharges the ML to
GND indicating a “mismatch”. Fig. 1 shows
the SEARCH operation in CAM. When ‘0’
is stored in the cell (Vx = ‘0’ and Vy = ‘1’).
For SL1 = ‘1’ (SL1c = ‘0’), ML is discharged
to ‘0’ detecting “mismatch” while for SL1
= ‘0’, ML remains at ‘1’ detecting a “match”
.In this way, the searching operation is
performed.
Match
Flag
Address
RAM
Data
Data
CAM
Address
The major application of CAM in recent
time is for IPV6. IPV6 is expected to
gradually replace IPV4. The list of some
other applications of CAM/TCAM is listed
below.
• Tag comparison in cache memory
• Data Compression and Radar Signal
Tracking
• Real-time pattern matching
• Virus-detection and Intrusion-detection
systems
• Gene pattern searching in bioinformatics
• Very high-speed data transfer
• Packet Forwarding
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in the Networking
Industry
• Network Routers
• Translation look-aside buffers (TLBs) in
microprocessors
• I.P. Filters
• ATM Switches
The SEARCH operation is performed in
three steps. First, search lines (SLs) SL1 and
SL1c are reset to GND. Second, ML is pre-
Fig. 1. Conventional CAM cell
ML
SL1c SL1
BL1 BL1c
WL
N1 N3
N2 N4
P1 P2
N8 N9
N6 N7
V
x
V
y
A typical 16T static TCAM cell is shown
in Fig. 2. It is similar to the binary CAM
cell, except that it has two SRAM cells. Due
to this, the TCAM are faster than CAM. The
READ, WRITE, and SEARCH operations in
this cell are performed in the same way as
described for CAM cell. For the given
circuit style, masking can be achieved by
turning off both ML-to-GND pull-down
Vineet Dhingra and Arti Noor
International Journal of Contemporary Research in Engg. and Tech. Vol. 1, No. 1, 2011 71
paths. For example, global masking is
performed by SL1 = SL2 = ‘0’, and local
masking is achieved by Vx = Vy = ‘0’.
Fig. 4 shows an example of local
masking. Word 110-XX-010 (located at
address 2) will match with any of the
following search keys: 110-00-010, 110-01–
010, 110-10-010 and 110-11–010.
BL1 BL2
ML
SL1 SL2
N1 N3
BL1c BL2c
V
x
V
y
WL
N2 N4
Fig. 2. Conventional TCAM cell with two
6 transistor SRAM memory devices
and a XNOR gate
BINARY CAM VERSUS TCAM
Masking can be done both globally (in the
search key) and locally (in the table entries).
Fig. 3 shows an example of global masking.
The search key 10110XXX will match with
all the entries that fall in the following
range: 10110000 to 10110111. It is called
global masking because the last three bits
of all the table entries are ignored.
Fig. 3. Global Masking in TCAM
2
Match
Match
Match
Priority
Encoder
Search Key
ML
‘0’ ‘0’
‘0’ ‘1’
N1 N3
N2 N4
Fig. 4. Local Masking in TCAM
Match
Search Key
ML
‘0’ ‘0’
‘0’ ‘1’
N1 N3
N2 N4
In case of Binary CAMs, the search key
can only be a string of ‘0’s and ’1’s. It
performs only complete search. It doesn’t
have ternary state i.e. ‘X’. The Fig. 5 shown
below shows the operation of a Binary
CAM. The search key is 11010010. The entry
in the 2nd row matches with search key.
NEW PROPOSED DESIGN FOR
TESTING
The TCAM cell was added with an addi-
tional circuitry to test the ML operation.
The above circuitry is modified by adding
Implementation and Verification of TCAM using System Verilog
72 International Journal of Contemporary Research in Engg. and Tech. Vol. 1, No. 1, 2011
ground. So, to perform the searching
operation again, we need to apply a high-
to-low pulse to pre-charge the capacitor. In
this way, we can test the searching
operation in a TCAM cell.
Table II. Matchline delay and power for
180nm
Parameters CAM TCAM
Results Results
Total Power 714.1031 uW 686.407 uW
Dissipation
Delays 0.020n sec 0.0179n sec
The Table II shows the comparison
between power
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and delays associated with
CAM/TCAM.
TCAM SIMULATION
Fig. 7 shows the timing analysis of the
TCAM cell. The discharge time is calculated
using this wave. The discharge time gives
the Search time of a TCAM cell.
Fig. 5. Search Operation in Binary CAM
Match
Search Key
an additional transmission gate (T.G.) and
a capacitor. The modified circuitry is shown
below to test the searching operation.
In Fig. 6, the input pulse is applied at
the input terminal. When the input pulse is
high, the ML is pre-charged to Vdd through
the transmission gate (T.G.) and so is the
capacitor. When the input pulse goes low,
the capacitor holds the charge making ML
voltage as Vdd. In this phase, when the
input pulse is low, the searching operation
is performed. As we know that when we
don’t find a match, the ML is discharged to
Vdd
Input
ML
WL
BL1 BL2
SL1 SL2
BL1c BL2c
V
x
V
y
Fig. 6. Modified TCAM cell
Fig. 7. TCAM cell schematic
Fig. 8 shows the output of a TCAM cell.
When IN=1, the ML is charged to VDD. In
the next low cycle, the searching is
performed. In the next case, when VX=0,
VY=1and SL=0, the ML remains at VDD
because 0 is found in the TCAM cell. In the
next cycle, ML is again Pre-charged to VDD
Vineet Dhingra and Arti Noor
International Journal of Contemporary Research in Engg. and Tech. Vol. 1, No. 1, 2011 73
for the next searching cycle. In the next
cycle, when both VX=VY=1, this condition
is the masking condition. At this condition,
ML discharges to ground.
TCAM HDL IMPLEMENTATION
After checking the CAM/TCAM at
schematic level, we moved a level higher at
HDL level and designed CAM/TCAM
using SystemVerilog. The design was
verified using the verification environment
that was created to enable testing for
different sizes of CAM/TCAM.
The CAM/TCAM was implemented
using SystemVerilog
10
and its verification
environment was created using OVM. The
design was verified with random inputs
generated by the environment, which was
reusable and flexible.
The TCAM output of the verification
environment
12
is shown in Fig. 9. This
environment can be used to test the
TCAM/CAM design of different sizes
because the verification environment is
parameterized, and we can change the size
of the memory as required. Table III shows
the power consumption of CAM for
different sizes.
Fig. 8. Wave Output of TCAM cell
Fig. 9. TCAM Environment simulation
output
EXPERIMENTAL RESULT
Power consumption in TCAM is 0.96 times
lesser than CAM even the search time is
also 3.54 times less. So, in speed as well as
in power aspect the TCAM is a better
option than any other memory element.
CONCLUSION
TCAMs are gaining importance in high-
speed lookup-intensive applications.
However, the high-power consumption of
TCAMs is limiting their popularity and
versatility. The work done here gives a
reusable Verification Environment for
CAM/TCAM. This work also proposed a
circuit to test the ML operation. The
searching operation was successfully
performed using the additional circuitry that
was added to the TCAM cell. The output
obtained was satisfactory and was in
accordance with the actual results obtained.
REFERENCES
1. Nitin Mohan, Derek Wright and Manoj
Sachdev, “Design Techniques and Test
Table III. Power consumption for different
sizes of CAM
Size Power (nW)
6*8 12808649.151
7*8 12812262.432
8*8 12814423.889
9*8 12815048.890
10*8 12915582.741
Implementation and Verification of TCAM using System Verilog
74 International Journal of Contemporary Research in Engg. and Tech. Vol. 1, No. 1, 2011
Methodology for Low-Power TCAMs,” IEEE
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ABOUT THE AUTHORS
Dr Arti Noor, Scientist-E, is
presently posted as Head of
Deartment, M.Tech. Division
VLSI at Centre for Develop-
ment of Advance Computing,
NOIDA. She is an alumni of
Banaras Hindi University,
Varanasi. She has 21 years of
research experience in the field
of VLSI Design and Technology Characterization,
VHDL, Computer Programming and Speech
Synthesis. She has more than 40 Research Articles
published in various National and International
Journals and Conferences to her credit. She is Life
member of Semiconductor Society and Broadcast
Engineering Services, Member of VLSI Society
of India, IEEE Member. She has supervised more
than 50 postgraduate theses in the area of VLSI
Desi gn, Exami ned 15 M. Tech. theses and
supervising three Ph.D. student in the area of
Microelectronics.
Vineet Dhingra received
B.Tech. degree in Electronics
and Instrumentation in 2008
from ITM Gurgaon, M.Tech. in
VLSI design from Guru
Gobind Singh Indraprastha
Uni versi ty, Del hi i n 2010.
The research interest is System
Level Design using System
Verilog and Digital Design.”
Vineet Dhingra and Arti Noor