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Lab Experiment No.

4 Kirchhoff’s Laws

I. Introduction
In this lab exercise, you will learn –
• how to read schematic diagrams of electronic networks,
• how to draw and use network graphs,
• how to transform schematics into actual component connections,
• correct ways to layout a breadboard connection of a network,
• how to connect the DMM to network components, and
• the verification of KCL and KVL.

II. Experiment Procedure
Four resistive networks N
1
through N
4
are shown on the following pages. Each network is accompanied with its
oriented graph, a simplified connection diagram, and a photo of its suggested breadboard layout. Your job in this
lab experiment is to fill out the three tables included with each network with the following data: (where ‘x’ denotes
the network number; eg, x = 1 for network 1, x = 2 for network 2, etc.)
(a) Table x.1 (variable map) – measure and record
i. the value of each network element,
ii. the voltage across each network element with node polarities, and
iii. the current through each voltage source with node polarities.
(b) Table x.1 (variable map) – calculate and record
i. the current through each resistor using Ohm’s law, and
ii. the power dissipated by each element.
(c) Table x.2 (KCL) – calculate and record
i. the total current into each node,
ii. the total current out of each node, and
iii. verification of KCL at each node.
(d) Table x.3 (KVL) – calculate and record
i. the total clockwise voltage drop around each circuit,
ii. the total counter clockwise voltage drop around each circuit, and
iii. verification of KVL for each circuit.

III. Lab Report
The report for this lab experiment must be word-processed and contain the following items –
• Title Page.
• Introduction.
• Procedure.
• Results.
• Discussions.
(a) Comment with respect to accuracy versus convenience on the application of Ohm’s law to determine
element current.
• Conclusion. Provide detailed comments and discussions on the items listed below for each resistor network.
(a) Does the total power dissipated equal the total power supplied? Explain why or why not.
(b) Are the network laws KCL and KVL verified? Explain any discrepancies.
• Appendix.
• References.

IV. Resistor Networks

Network N
1


v
1
v
2
e
V1
e
R1
(a) (b)
R
1
1K
2 1
(c)
V1 R
1
1K
1
2
10V
Agilent E3620A
V1 V2
N
1
G
1

Figure 1.1
(a) Network N
1

(b) Graph G
1
of N
1

(c) Component connections


Figure 1.2
Breadboard layout of N
1


Table 1.1
Voltage, current, and power map for N
1






Element




Specified
value




Measured
value
Element voltage Element current




Element
power (W)
Nodes


Measured
value (V)
Nodes


Calculated
value (A)
+ − + −
R
1
1KΩ
V1 10V 1 2

Table 1.2
Kirchhoff current law
Node
Total current
into (I
in
) (A)
Total current
out of (I
out
) (A)
KCL
(I
in
– I
out
) (A)
1
2

Table 1.3
Kirchhoff voltage law
Circuit
Total cw voltage
drop (V
cw
) (V)
Total ccw voltage
drop (V
ccw
) (V)
KVL
(V
cw
– V
ccw
) (V)
V1, R
1





Network N
2


Agilent E3620A
V1 V2
R
1
R
2
R
3
1
2 3
4
V1
R
1
1K
1
4
2
3
R
2
R
3
2K
3K
9V
e
V1
v
1
v
2
v
3
v
4
e
R1
e
R2
e
R3
(a) (b)
(c)
N
2
G
2
Figure 2.1
(a) Network N
2

(b) Graph G
2
of N
2

(c) Component connections


Figure 2.2
Breadboard layout of N
2



Table 2.1
Voltage, current, and power map for N
2






Element




Specified
value




Measured
value
Element voltage Element current




Element
power (W)
Nodes


Measured
value (V)
Nodes


Calculated
value (A)
+ − + −
R
1
1KΩ
R
2
2KΩ
R
3
3KΩ
V1 9V 1 4

Table 2.2
Kirchhoff current law
Node
Total current
into (I
in
) (A)
Total current
out of (I
out
) (A)
KCL
(I
in
– I
out
) (A)
1
2
3
4

Table 2.3
Kirchhoff voltage law
Circuit
Total cw voltage
drop (V
cw
) (V)
Total ccw voltage
drop (V
ccw
) (V)
KVL
(V
cw
– V
ccw
) (V)
V1, R
1
,
R
2
, R
3





Network N
3


R
1
R
2
R
3
R
4
R
5
R
6
V1
1 2 3
4 5 6
3.9K 1.2K
12K 9.1K
4.7K 2.2K
15V
e
R1
e
V1
e
R2
e
R3
e
R4
e
R5
e
R6
v
1
v
2 v
3
v
4 v
5
v
6
Agilent E3620A
V1 V2
(a) (b)
N
3
G
3
R
1
R
2
R
3
R
4
R
5
R
6
1
2
3 4
5
6
(c)

Figure 3.1
(a) Network N
3

(b) Graph G
3
of N
3

(c) Component connections


Figure 3.2
Breadboard layout of N
3

Table 3.1
Voltage, current, and power map for N
3






Element




Specified
value




Measured
value
Element voltage Element current




Element
power (W)
Nodes


Measured
value (V)
Nodes


Calculated
value (A)
+ − + −
R
1
3.9KΩ
R
2
1.2KΩ
R
3
9.1KΩ
R
4
2.2KΩ
R
5
12KΩ
R
6
4.7KΩ
V1 15V 1 6

Table 3.2
Kirchhoff current law
Node
Total current
into (I
in
) (A)
Total current
out of (I
out
) (A)
KCL
(I
in
– I
out
) (A)
1
2
3
4
5
6

Table 3.3
Kirchhoff voltage law
Circuit
Total cw voltage
drop (V
cw
) (V)
Total ccw voltage
drop (V
ccw
) (V)
KVL
(V
cw
– V
ccw
) (V)
V1, R
1
,
R
5
, R
6


R
5
, R
2
,
R
3
, R
4


V1, R
1
,
R
2
, R
3
,
R
4
, R
6



Network N
4


V1
V2 R
1
R
2
R
3
R
4
R
5
R
6
R
7
1
2
3
4
5
6
5V
10V 220K
82K 47K
150K
12K
4.7K
3.3K
v
1
v
2
v
3
v
4
v
5
v
6
e
R1
e
R2
e
R3
e
V1
e
V2
e
R4
e
R5
e
R6
e
R7
(a) (b)
Agilent E3620A
V1 V2
1
3
2
6
4 5
R
1
R
2
R
3
R
4
R
5
R
6
R
7
(c)
N
4
G
4

Figure 4.1
(a) Network N
4

(b) Graph G
4
of N
4

(c) Component connections





Figure 4.2
Breadboard layout of N
4


Table 4.1
Voltage, current, and power map for N
4






Element




Specified
value




Measured
value
Element voltage Element current




Element
power (W)
Nodes


Measured
value (V)
Nodes


Calculated
value (A)
+ − + −
R
1
220KΩ
R
2
82KΩ
R
3
47KΩ
R
4
150KΩ
R
5
12KΩ
R
6
3.3KΩ
R
7
4.7KΩ
V1 5V 1 3
V2 10V 2 5



Table 4.2
Kirchhoff current law
Node
Total current
into (I
in
) (A)
Total current
out of (I
out
) (A)
KCL
(I
in
– I
out
) (A)
1
2
3
4
5
6

Table 4.3
Kirchhoff voltage law
Circuit
Total cw voltage
drop (V
cw
) (V)
Total ccw voltage
drop (V
ccw
) (V)
KVL
(V
cw
– V
ccw
) (V)
R
1
, R
2
,
V2, R
6


V2, R
3
,
R
4
, R
5


R
2
, V1, R
3

R
6
, R
5
, R
7