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Problem of VLSI Routing And Minimum Steiner Tree

M S Santosh Kumar
year, BTe!h, "le!tri!al "ngineering
Indian Institute of Te!hnology, Madras
#hennai, India
AbstractThis paper provides a review on the problem of
VLSI routing and the approximate optimization algorithm that is
used in practice, the problem of finding a Minimum Steiner Tree,
to solve the problem of global routing
KeywordsRouting, Minimum Spanning Tree, Minimum
Steiner Tree, Optimization algorithms, N ! hard"
I I&TR'()#TI'&
Routing is an im*ortant *hase in the *hysi!al design of
VLSI !ir!uits This *hase !onsists of finding the layout of the
+ires !onne!ting the terminals on !ir!uit blo!$s or gates A
terminal is a lo!ation on a blo!$, ty*i!ally along one of the
edges, +hi!h needs to be !onne!ted to some other blo!$s on
the layout A net is a set of terminals that are re,uired to be
!onne!ted together A netlist is a !olle!tion of nets that are to
routed The routing space is the s*a!e in +hi!h +e are allo+ed
to *la!e the +ires and the routing s*a!e bet+een t+o blo!$s is
!alled a channel. The *roblem of VLSI routing is to !onne!t all
the nets in the netlist through +ires running in the routing
s*a!e The routing *roblem is !om*utationally -ery diffi!ult
Infa!t, it is &P.hard
Be!ause of this hardness, most of
routing algorithms are a**ro2imate and a fe+ ty*i!al
sim*lifi!ations are generally made The first one is to di-ide
the *roblem into t+o *hases !alled global routing and detailed
routing. In global routing, +e ignore the e2a!t geometri!
details and only does a !oarse.grain assignment of routes to
routing regions These routes are !on-erted into e2a!t layout in
the latter *hase Detailed routing !om*letes the *oint to *oint
+iring by s*e!ifying the geometri! information and layer
assignments There are also ste*s of routing in-ol-ed in the
design of VLSI !hi*s namely Timing-Driven routing, Non-
Manhattan and clock routing. 'ur fo!us in this *a*er +ill be
the *roblem of global routing
A. Input to the algorithm
The in*ut is a netlist !onsisting of a set of nets ea!h of +hi!h is
a set of terminals In addition to the netlist, the s*e!ifi!ations
on the routing s*a!e has to be *ro-ided All this information is
ty*i!ally *ro-ided in terms of a gra*h The are t+o gra*h
models that are ty*i!ally used4 Grid graph model and Channel-
Insertion graph model. In Grid-graph model, the !hi* is
modelled as n m grid gra*h +ith -erti!es that do not belong
to the routing s*a!e li$e blo!$s are remo-ed and +ires !an be
routed along any edge of the gra*h 5e assume that the gra*h is
un.+eighted All the edges in this model ha-e the same length
In the channel-insertion graph model, -erti!es are *la!ed at all
interse!tions of the !hannels and the terminals The lengths of
the edges are no longer same
!. "teiner Trees
6i-en a gra*h 67V,"8 +ith set of -erti!es V and set
of demand *oints 7 nets in our !ase 8 (, the Steiner tree is a set
of edges that !onne!t all the demand *oints ( A minimum
s*anning tree is a tree +hi!h !onne!ts all -erti!es +ith edges
+ith minimum total +eight
The minimum "teiner tree *roblem is similar to
minimum spanning tree *roblem4 6i-en a set of -erti!es V,
find the set of edges su!h that the total edge length is
minimi9ed The only differen!e bet+een the "teiner tree
problem and the "panning tree problem is that, in Steiner tree
*roblem, not all set of -erti!es in the gra*h are in the set of
demand *oints 5e !an add e2tra intermediate -erti!es and
edges to redu!e the length of the s*anning tree The ne+
-erti!es that are introdu!ed are !alled "teiner points or "teiner
vertices. Sin!e finding MST is hard, the ty*i!al initial ste* is
to start +ith a minimum s*anning tree
C. "teiner trees in #$"I routing
In VLSI !ir!uits, +ires are to be laid do+n in hori9ontal
and -erti!al dire!tions Thus for the grid 3 model, the demand
*oints ( are the set of -erti!es on the grid and routing *roblem
is to find minimum re!tilinear Steiner tree 7MRST8 Again
MRST is &P.hard Thus in *ra!ti!e, the a**ro2imate minimum
RST is obtained by re!ti lineari9ing ea!h edge of minimum
s*anning tree It is *ro-ed that ratio of the !ost of a re!tilinear
MST to that of an o*timal RST is no greater than 0:
7;+ang<s Theorm8
;ere !ost is defined using Manhattan
distan!e as !ost7 V0, V> 8 ? @ 20 3 2> @ A @ y0 3 y> @ +here V0 and V>
are -erti!es at 720,y08 and 72>,y>8 res*e!ti-ely
Various methods for re!tilinear edges in a MST e2ist

The method +hi!h transforms ea!h diagonal edge using only

one turn is !alled a L.RST
, if it uses t+o.turns for ea!h
diagonal edge, it is !alled a C.RST
The one +hi!h uses
arbitrary number of turns is !alled S.RST 5e des!ribe an
o*timal S.RST for se*arable MSTs "eparabilit% here means
that any *air of non.adDa!ent edges should ha-e non.
o-erla**ing bounding re!tangles See Eigure 708
Eigure7084 The first gra*h a set of -erti!es on MST +hi!h is
not se*erable The se!ond gra*h sho+s the same set of -erti!es
on MST that are se*arable
"-ery *oint set has a se*arable MST
and if the gi-en
gra*h obeys the se*arability *ro*erty, then there e2ists a
method to find an o*timal S.RST from the MST The algorithm
*ro!eeds in the follo+ing lines
#al!ulate the minimum s*anning tree of the gi-en
Then, the resultant MST is hung by one of the lea-es
of the tree
Starting at the root edge, re!ursi-ely !om*ute the
o*timal C.layouts of the sub.trees rooted at the !hildren
"a!h !ombination of o*timal C.layout is then finally
!ombined to get +hole layout The merged layout +ith
least !ost is the o*timal C.layout of the entire tree
An a**ro2imate *seudo !ode of re!ursi-ely !om*uting
o*timal C.layout is des!ribed belo+
def Z-layoutmin( z[i] , T[i] ):
# z[i] a z-layout for an edge i
# T[i] the subtree of edges hanging from
edge e
f T[i] is em!ty then return z[i]
for ea"h "hild edge # in T[i]:
for ea"h Z-layoutmin z[#] of #:
Z-layoutmin( z[#], T[#] )
for all the "ombinations of Z-layout:
return minimum "ost Z-layout
D. Comple&it% Anal%sis'
The se*arable MST !an be found using *rim<s algorithm in
'7VA"8 The re!ursion !an be done in '7>
"8 +here d is
total no of *ossible C.RST !onfigurations for a gi-en
MST edge +hi!h is F? B So, this is *olynomial time
(. Need )or good algorithm'
Although, the one des!ribed here gi-es the solution in
*olynomial time It doesn<t gi-e o*timal RST This method
of se,uential +ire layout !an result in -arious *roblems
li$e blo!$ing due to already laid +ires et! introdu!ing the
need to Gre.routeH the +ires es*e!ially as the in*ut gets
larger and larger and the routing s*a!e de!reases to
fa!ilitate miniaturi9ation of I#s There are other interesting
de-elo*ments in this area that are mentioned in /B1, /I1,
/J1 Detailed routing, not mentioned in this *a*er !an be
found at /K1, /0L1
/01 MR6arey and (SMohnson, The re!tilinear Steiner tree *roblem,
SIAM MA**l Math,3>7=8, **J>B.J3=
/>1 M;anan, 'n Steiner<s *roblem +ith re!tilinear distan!e MSIAM
A**lMath 0=70KKB8,**>::.>B:
/31 "&6ilbert and ;'Polla$, Steiner Minimal Trees MSIAMA**l Math
0B708, **0.>K
/=1 EK;+ang,(SRi!hards,P5inter70KK>8 The Steiner Tree Problem
Annals of (is!rete Mathemati!s :3 &orthN;olland4 "lse-ier ISB& L.
/:1 Steiner Tree *roblem, Routing 7ele!troni! design automation8, Minimum
S*anning Trees, 5i$i*edia, the free en!y!lo*edia
/B1 Man.Ming.;o,6o*alaKrishnan ViDayan and #K5ong, &e+ Algorithms
for the Re!tilinear Steiner Tree Problem, I""" Transa!ations on
#om*outer.AidedP(esign VolK &o> Eebruary 0KKL
/I1 LiengigM, A *arallel geneti! algorithm for *erforman!e dri-ern 3VLSI
routing , I""" transa!tions, A*r 0KKI
/J1 Kahng,ABQ$+o$.Shing Leung, "ffi!ient algorithms for the minimum
shortest *arth Steiner arbores!en!e *roblem +ith a**li!ations to VLSI
*hysi!al design
/K1 Sagar, VK, Tas$.farming of the detailed routing *roblem in VLSI design
/0L1 Andre+ BKahng, Mens Lienig,Igor L Mar$o-, Min ;u, VLSI Physi!al
(esign4 Erom 6ra*h *artionting to Timing #losure