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Advanced Configuration and

Power Interface Specification


Hewlett-Packard Corporation
Intel Corporation
Microsoft Corporation
Phoenix Technologies Ltd
Toshi!a Corporation
"evision #$
Septe%!er &' &$$(
Cop)right * +,,-' +,,.' +,,/' +,,,' &$$$' &$$+' &$$&' &$$#' &$$( Hewlett-Packard Corporation' Intel
Corporation' Microsoft Corporation' Phoenix Technologies Ltd' Toshi!a Corporation
All rights reserved
I0T1LL1CT2AL P"3P1"T4 5ISCLAIM1"
THIS SP1CI6ICATI30 IS P"37I515 8AS IS9 :ITH 03 :A""A0TI1S :HATS3171" I0CL25I0;
A04 :A""A0T4 36 M1"CHA0TA<ILIT4' 6IT01SS 63" A04 PA"TIC2LA" P2"P3S1' 3" A04
:A""A0T4 3TH1":IS1 A"ISI0; 32T 36 A04 P"3P3SAL' SP1CI6ICATI30' 3" SAMPL1
03 LIC10S1' 1=P"1SS 3" IMPLI15' <4 1ST3PP1L 3" 3TH1":IS1' T3 A04 I0T1LL1CT2AL
P"3P1"T4 "I;HTS IS ;"A0T15 3" I0T10515 H1"1<4
HP' I0T1L' MIC"3S36T' PH310I=' A05 T3SHI<A 5ISCLAIM ALL LIA<ILIT4' I0CL25I0;
LIA<ILIT4 63" I06"I0;1M10T 36 P"3P"I1TA"4 "I;HTS' "1LATI0; T3 IMPL1M10TATI30 36
I063"MATI30 I0 THIS SP1CI6ICATI30 HP' I0T1L' MIC"3S36T' PH310I=' A05 T3SHI<A 53
03T :A""A0T 3" "1P"1S10T THAT S2CH IMPL1M10TATI30>S? :ILL 03T I06"I0;1 S2CH
"I;HTS
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Microsoft, Win32, Windows, and Windows NT are registered trademarks of Microsoft Corporation.
All other product names are trademarks, registered trademarks, or service marks of their respective owners.
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"evision Change 5escription
Affected
Sections
3.
!ept. 2"
Ma#or specification revision. $eneral configuration enhancements. %nter&
'rocessor power, performance, and throttling state dependenc( support added.
!upport for ) 2*+ processors added. N,MA -istancing support added. 'C%
./press support added. !ATA support added. Am0ient 1ight !ensor and ,ser
'resence device support added. Thermal model e/tended 0e(ond processor&
centric support.
2.c
Aug.. 23
.rrata and clarifications added.
2.0
2ct. 22
.rrata and clarifications added.
2.a
Mar. 22
.rrata and clarifications added. AC'% 2. .rrata -ocument 3evision 4.
through 4.* integrated.
AC'% 2.
.rrata -oc.
3ev. 4.*
.rrata and clarifications added.
AC'% 2.
.rrata -oc.
3ev. 4."
.rrata and clarifications added.
AC'% 2.
.rrata -oc.
3ev. 4.3
.rrata and clarifications added.
AC'% 2.
.rrata -oc.
3ev. 4.2
.rrata and clarifications added.
AC'% 2.
.rrata -oc.
3ev. 4.4
.rrata and clarifications added.
AC'% 2.
.rrata -oc.
3ev. 4.
.rrata and clarifications added.
2.
Aug. 2
Ma#or specification revision. +"&0it addressing support added. 'rocessor and
device performance state support added. Numerous multiprocessor workstation
and server&related enhancements. Consistenc( and reada0ilit( enhancements
throughout.
4.0
5e0. 4666
.rrata and clarifications added. New interfaces added.
4.a
7ul. 4668
.rrata and clarifications added. New interfaces added.
4.
-ec. 466+
2riginal 3elease.
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Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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Contents
+ I0T"352CTI30+
++ Principal ;oals +
+& Power Manage%ent "ationale &
+# Legac) Support #
+( 31M I%ple%entation Strateg) #
+A Power and Sleep <uttons #
+- ACPI Specification and the Structure 3f ACPI(
+. 3S and Platfor% Co%pliance A
4.9.4 'latform %mplementations of AC'%&defined %nterfaces...................................................................................*
4.9.2 2!'M %mplementations................................................................................................................................. 8
4.9.3 2! 3e:uirements........................................................................................................................................... 6
+/ Target Audience ,
+, 5ocu%ent 3rganiBation ,
4.6.4 AC'% %ntroduction and 2verview................................................................................................................. 4
4.6.2 'rogramming Models................................................................................................................................... 4
4.6.3 %mplementation -etails................................................................................................................................ 4
4.6." Technical 3eference..................................................................................................................................... 44
++$ "elated 5ocu%ents ++
& 516I0ITI30 36 T1"MS+#
&+ ;eneral ACPI Ter%inolog) +#
&& ;lo!al S)ste% State 5efinitions+,
&# 5evice Power State 5efinitions&+
&( Sleeping State 5efinitions &&
&A Processor Power State 5efinitions &&
&- 5evice and Processor Perfor%ance State 5efinitions&#
# ACPI 371"7I1:&A
#+ S)ste% Power Manage%ent &-
#& Power States &.
3.2.4 'ower ;utton............................................................................................................................................... 28
3.2.2 'latform 'ower Management Characteristics...............................................................................................28
## 5evice Power Manage%ent &,
3.3.4 'ower Management !tandards..................................................................................................................... 26
3.3.2 -evice 'ower !tates..................................................................................................................................... 26
3.3.3 -evice 'ower !tate -efinitions....................................................................................................................3
#( Controlling 5evice Power #$
3.".4 $etting -evice 'ower Capa0ilities...............................................................................................................3
3.".2 !etting -evice 'ower !tates.........................................................................................................................3
3.".3 $etting -evice 'ower !tatus........................................................................................................................34
3."." Waking the Computer................................................................................................................................... 34
3.".* ./ample< Modem -evice 'ower Management............................................................................................33
#A Processor Power Manage%ent#-
#- 5evice and Processor Perfor%ance States #-
#. Configuration and 8Plug and Pla)9#-
3.9.4 -evice Configuration ./ample< Configuring the Modem............................................................................39
3.9.2 N,MA Nodes.............................................................................................................................................. 39
#/ S)ste% 1vents #.
#, <atter) Manage%ent #/
3.6.4 ;atter( Communications.............................................................................................................................. 38
3.6.2 ;atter( Capacit(........................................................................................................................................... 36
3.6.3 ;atter( $as $auge....................................................................................................................................... 36
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3.6." 1ow ;atter( 1evels...................................................................................................................................... 36
3.6.* ;atter( Cali0ration....................................................................................................................................... "2
#+$ Ther%al Manage%ent (#
3.4.4 Active and 'assive Cooling Modes............................................................................................................ ""
3.4.2 'erformance vs. .nerg( Conservation........................................................................................................""
3.4.3 Acoustics =Noise>....................................................................................................................................... ""
3.4." Multiple Thermal ?ones............................................................................................................................. ""
( ACPI HA"5:A"1 SP1CI6ICATI30(A
(+ 6ixed Hardware Progra%%ing Model(A
".4.4 5unctional 5i/ed @ardware.......................................................................................................................... "*
(& ;eneric Hardware Progra%%ing Model(-
(# 5iagra% Legends (/
(( "egister <it 0otation (,
(A The ACPI Hardware Model (,
".*.4 @ardware 3eserved ;its............................................................................................................................... *2
".*.2 @ardware %gnored ;its................................................................................................................................. *2
".*.3 @ardware Write&2nl( ;its............................................................................................................................ *3
".*." Cross -evice -ependencies......................................................................................................................... *3
(- ACPI Hardware 6eatures A#
(. ACPI "egister Model AA
".9.4 AC'% 3egister !ummar(.............................................................................................................................. *8
".9.2 5i/ed @ardware 5eatures............................................................................................................................. +
".9.3 5i/ed @ardware 3egisters............................................................................................................................ +6
".9." $eneric @ardware 3egisters......................................................................................................................... 99
A ACPI S36T:A"1 P"3;"AMMI0; M351L/#
A+ 3verview of the S)ste% 5escription Ta!le Architecture/#
*.4.4 Address !pace Translation............................................................................................................................ 8*
A& ACPI S)ste% 5escription Ta!les/-
*.2.4 3eserved ;its and 5ields.............................................................................................................................. 8+
*.2.2 Compati0ilit(............................................................................................................................................... 89
*.2.3 Address 5ormat............................................................................................................................................ 89
*.2." ,niversal ,niform %dentifiers =,,%->......................................................................................................... 88
*.2.* 3oot !(stem -escription 'ointer =3!-'>....................................................................................................88
*.2.+ !(stem -escription Ta0le @eader................................................................................................................6
*.2.9 3oot !(stem -escription Ta0le =3!-T>.......................................................................................................62
*.2.8 ./tended !(stem -escription Ta0le =A!-T>...............................................................................................6"
*.2.6 5i/ed AC'% -escription Ta0le =5A-T>........................................................................................................6*
*.2.4 5irmware AC'% Control !tructure =5AC!>...............................................................................................4*
*.2.44 -efinition ;locks..................................................................................................................................... 46
*.2.42 $lo0al !(stem %nterrupts..........................................................................................................................42
*.2.43 !mart ;atter( Ta0le =!;!T>..................................................................................................................... 422
*.2.4" .m0edded Controller ;oot 3esources Ta0le =.C-T>..............................................................................422
*.2.4* !(stem 3esource Affinit( Ta0le =!3AT>..................................................................................................42"
*.2.4+ !(stem 1ocalit( -istance %nformation Ta0le =!1%T>................................................................................429
A# ACPI 0a%espace +&,
*.3.4 'redefined 3oot Namespaces..................................................................................................................... 434
*.3.2 20#ects....................................................................................................................................................... 434
A( 5efinition <lock 1ncoding +#+
AA 2sing the ACPI Control Method Source Language+##
*.*.4 A!1 !tatements.......................................................................................................................................... 433
*.*.2 Control Method ./ecution.........................................................................................................................43"
A- ACPI 1vent Progra%%ing Model+#A
*.+.4 AC'% .vent 'rogramming Model Components..........................................................................................43+
*.+.2 T(pes of AC'% .vents................................................................................................................................ 43+
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*.+.3 -evice 20#ect Notifications....................................................................................................................... 4"4
*.+." -evice Class&!pecific 20#ects................................................................................................................... 4""
*.+.* -efined $eneric 20#ects and Control Methods..........................................................................................4"+
A. Predefined 3!Cects +A#
*.9.4 BC$1 =$lo0al 1ock Mute/>........................................................................................................................4*"
*.9.2 BC2!% =2perating !(stem %nterfaces>.......................................................................................................... 4*"
*.9.3 BC2! =2! Name 20#ect>............................................................................................................................. 4*9
*.9." BC3.D =3evision -ata 20#ect>................................................................................................................... 4*9
A/ S)ste% Configuration 3!Cects +A/
*.8.4 C'%C Method.............................................................................................................................................. 4*8
- C306I;2"ATI30+A,
-+ 5evice Identification 3!Cects +A,
+.4.4 CA-3 =Address>........................................................................................................................................ 4*6
+.4.2 CC%- =Compati0le %->............................................................................................................................... 4+
+.4.3 C--N =-2! -evice Name>....................................................................................................................... 4+4
+.4." C@%- =@ardware %->.................................................................................................................................. 4+4
+.4.* CM1! =Multiple 1anguage !tring>............................................................................................................. 4+2
+.4.+ C'1- ='h(sical -evice 1ocation>..............................................................................................................4+2
+.4.9 C!T3 =!tring>............................................................................................................................................. 4+"
+.4.8 C!,N =!lot ,ser Num0er>......................................................................................................................... 4+"
+.4.6 C,%- =,ni:ue %->...................................................................................................................................... 4+*
-& 5evice Configuration 3!Cects +-A
+.2.4 CC3! =Current 3esource !ettings>............................................................................................................. 4++
+.2.2 C-%! =-isa0le>........................................................................................................................................... 4++
+.2.3 C-MA =-irect Memor( Access>.................................................................................................................4+9
+.2." C5%A =5i/ed 3egister 3esource 'rovider>..................................................................................................4+6
+.2.* C$!; =$lo0al !(stem %nterrupt ;ase>.......................................................................................................49
+.2.+ C@'' =@ot 'lug 'arameters>...................................................................................................................... 494
+.2.9 C@'A =@ot 'lug 'arameter ./tensions>.....................................................................................................493
+.2.8 CMAT =Multiple A'%C Ta0le .ntr(>...........................................................................................................49*
+.2.6 C2!C =2perating !(stem Capa0ilities>......................................................................................................49+
+.2.4 C'3! ='ossi0le 3esource !ettings>.......................................................................................................... 48"
+.2.44 C'3T ='C% 3outing Ta0le>........................................................................................................................48"
+.2.42 C'AM ='ro/imit(>................................................................................................................................... 48+
+.2.43 C!1% =!(stem 1ocalit( %nformation>........................................................................................................48+
+.2.4" C!3! =!et 3esource !ettings>.................................................................................................................. 486
-# 5evice Insertion' "e%oval' and Status 3!Cects+/,
+.3.4 C.-1 =.#ect -evice 1ist>...........................................................................................................................464
+.3.2 C.7- =.#ection -ependent -evice>............................................................................................................464
+.3.3 C.7/ =.#ect>................................................................................................................................................ 463
+.3." C1CE =1ock>.............................................................................................................................................. 463
+.3.* C2!T =2!'M !tatus %ndication>................................................................................................................463
+.3.+ C3MD =3emove>........................................................................................................................................ 468
+.3.9 C!TA =!tatus>............................................................................................................................................. 468
-( "esource 5ata T)pes for ACPI +,,
+.".4 A!1 Macros for 3esource -escriptors....................................................................................................... 466
+.".2 !mall 3esource -ata T(pe.........................................................................................................................466
+.".3 1arge 3esource -ata T(pe.........................................................................................................................2"
-A 3ther 3!Cects and Control Methods&&.
+.*.4 C%N% =%nit>................................................................................................................................................... 229
+.*.2 C-CE =-ock>............................................................................................................................................. 229
+.*.3 C;-N =;%2! -ock Name>......................................................................................................................... 228
+.*." C3.$ =3egion>.......................................................................................................................................... 228
+.*.* C;;N =;ase ;us Num0er>......................................................................................................................... 226
+.*.+ C!.$ =!egment>........................................................................................................................................ 226
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+.*.9 C$1E =$lo0al 1ock>.................................................................................................................................. 234
. P3:1" A05 P1"63"MA0C1 MA0A;1M10T&##
.+ 5eclaring a Power "esource 3!Cect &##
9.4.4 -efined Child 20#ects for a 'ower 3esource.............................................................................................23"
9.4.2 C255.......................................................................................................................................................... 23"
9.4.3 C2N........................................................................................................................................................... 23*
9.4." C!TA =!tatus>............................................................................................................................................. 23*
.& 5evice Power Manage%ent 3!Cects&#A
9.2.4 C-!W =-evice !leep Wake>...................................................................................................................... 239
9.2.2 C'! ='ower !tate >................................................................................................................................. 239
9.2.3 C'!4 ='ower !tate 4>................................................................................................................................. 238
9.2." C'!2 ='ower !tate 2>................................................................................................................................. 238
9.2.* C'!3 ='ower !tate 3>................................................................................................................................. 238
9.2.+ C'!C ='ower !tate Current>....................................................................................................................... 238
9.2.9 C'3 ='ower 3esources for ->................................................................................................................236
9.2.8 C'34 ='ower 3esources for -4>................................................................................................................236
9.2.6 C'32 ='ower 3esources for -2>................................................................................................................236
9.2.4 C'3W ='ower 3esources for Wake>......................................................................................................... 236
9.2.44 C'!W ='ower !tate Wake>....................................................................................................................... 2"
9.2.42 C%3C =%n 3ush Current>............................................................................................................................ 2"4
9.2.43 C!4- =!4 -evice !tate>............................................................................................................................ 2"4
9.2.4" C!2- =!2 -evice !tate>............................................................................................................................ 2"4
9.2.4* C!3- =!3 -evice !tate>............................................................................................................................ 2"2
9.2.4+ C!"- =!" -evice !tate>............................................................................................................................ 2"2
9.2.49 C!W =! -evice Wake !tate>.................................................................................................................2"3
9.2.48 C!4W =!4 -evice Wake !tate>.................................................................................................................2"3
9.2.46 C!2W =!2 -evice Wake !tate>.................................................................................................................2"3
9.2.2 C!3W =!3 -evice Wake !tate>.................................................................................................................2"3
9.2.24 C!"W =!" -evice Wake !tate>.................................................................................................................2"3
.# 31M-Supplied S)ste%-Level Control Methods&(#
9.3.4 BC;5! =;ack 5rom !leep>.......................................................................................................................... 2""
9.3.2 BC'T! ='repare To !leep>........................................................................................................................... 2""
9.3.3 BC$T! =$oing To !leep>............................................................................................................................. 2"*
9.3." !(stem BC!/ states...................................................................................................................................... 2"*
9.3.* C!W! =!(stem Wake !ource>....................................................................................................................2"6
9.3.+ BCTT! =Transition To !tate>........................................................................................................................2*
9.3.9 BCWAE =!(stem Wake>.............................................................................................................................. 2*
.( 3SPM usage of D;TS' DPTS' DTTS' D:AE' and D<6S&A+
/ P"3C1SS3" P3:1" A05 P1"63"MA0C1 STAT1 C306I;2"ATI30 A05 C30T"3L&A#
/+ Processor Power States &A#
8.4.4 'rocessor 'ower !tate C........................................................................................................................... 2**
8.4.2 'rocessor 'ower !tate C4........................................................................................................................... 2*9
8.4.3 'rocessor 'ower !tate C2........................................................................................................................... 2*9
8.4." 'rocessor 'ower !tate C3........................................................................................................................... 2*9
8.4.* Additional 'rocessor 'ower !tates............................................................................................................. 2*8
/& 6lushing Caches &A/
/# Power' Perfor%ance' and Throttling State 5ependencies&A,
/( 5eclaring Processors &A,
8.".4 C'-C ='rocessor -river Capa0ilities>........................................................................................................2+
8.".2 'rocessor 'ower !tate Control................................................................................................................... 2+4
8.".3 'rocessor Throttling Controls.....................................................................................................................2+"
8."." 'rocessor 'erformance Control..................................................................................................................2+6
, ACPI-517IC1S A05 517IC1 SP1CI6IC 3<F1CTS&.A
,+ GDSI S)ste% Indicators &.A
6.4.4 C!!T =!(stem !tatus>................................................................................................................................. 29*
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6.4.2 CM!$ =Message>....................................................................................................................................... 29*
6.4.3 ;1T =;atter( 1evel Threshold>.................................................................................................................. 29*
,& Control Method A%!ient Light Sensor 5evice&.-
6.2.4 2verview.................................................................................................................................................... 29+
6.2.2 CA1% =Am0ient 1ight %lluminance>............................................................................................................ 299
6.2.3 CA1T =Am0ient 1ight Temperature>...........................................................................................................299
6.2." CA1C =Am0ient 1ight Color Chromacit(>.................................................................................................299
6.2.* CA13 =Am0ient 1ight 3esponse>............................................................................................................... 298
6.2.+ CA1' =Am0ient 1ight 'olling>................................................................................................................... 284
6.2.9 Am0ient 1ight !ensor .vents..................................................................................................................... 284
6.2.8 3elationship to ;acklight Control Methods...............................................................................................282
,# <atter) 5evice &/&
,( Control Method Lid 5evice &/&
6.".4 C1%-........................................................................................................................................................... 282
,A Control Method Power and Sleep <utton 5evices&/&
,- 1%!edded Controller 5evice&/#
,. 6an 5evice &/#
,/ ;eneric Container 5evice &/#
,, ATA Controller 5evices &/#
6.6.4 20#ects for ;oth ATA and !ATA Controllers..............................................................................................28"
6.6.2 %-. Controller -evice............................................................................................................................... 28*
6.6.3 !erial ATA =!ATA> Controller -evice........................................................................................................289
,+$ 6lopp) Controller 5evice 3!Cects &/,
6.4.4 C5-. =5lopp( -isk .numerate>............................................................................................................... 286
6.4.2 C5-% =5lopp( -isk %nformation>..............................................................................................................286
6.4.3 C5-M =5lopp( -isk -rive Mode>............................................................................................................26
,++ ;P1 <lock 5evice &,+
6.44.4 Matching Control Methods for $eneral&'urpose .vents in a $'. ;lock -evice.....................................264
,+& Module 5evice &,&
,+# Me%or) 5evices &,(
6.43.4 Address -ecoding.................................................................................................................................... 26"
6.43.2 ./ample< Memor( -evice........................................................................................................................26*
,+( D2PC >2S< Port Capa!ilities?&,A
6.4".4 ,!; 2. @ost Controllers and C,'C and C'1-.......................................................................................268
,+A 5evice 3!Cect 0a%e Collision #$$
6.4*.4 C-!M =-evice !pecific Method>.............................................................................................................3
,+- PC@AT "TC@CM3S 5evices#$&
6.4+.4 'CFAT&compati0le 3TCFCM2! -evices ='N';>...............................................................................32
6.4+.2 %ntel '%%A"&compati0le 3TCFCM2! -evices ='N';4>.......................................................................33
6.4+.3 -allas !emiconductor&compati0le 3TCFCM2! -evices ='N';2>......................................................33
,+. Control Method 2ser Presence 5etection 5evice#$(
6.49.4 C,'- =,ser 'resence -etect>..................................................................................................................3"
6.49.2 C,'' =,ser 'resence 'olling>..................................................................................................................3"
6.49.3 ,ser 'resence !ensor .vents....................................................................................................................3*
,+/ I@3 APIC 5evice #$A
+$ P3:1" S32"C1 517IC1S#$.
+$+ S%art <atter) Su!s)ste%s #$.
4.4.4 AC'% !mart ;atter( !tatus Change Notification 3e:uirements................................................................36
4.4.2 !mart ;atter( 20#ects.............................................................................................................................. 34
4.4.3 !mart ;atter( !u0s(stem Control Methods..............................................................................................344
+$& Control Method <atteries #+#
4.2.4 ;atter( .vents.......................................................................................................................................... 343
4.2.2 ;atter( Control Methods..........................................................................................................................34"
+$# AC Adapters and Power Source 3!Cects#&&
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4.3.4 C'!3 ='ower !ource>............................................................................................................................... 322
4.3.2 C'C1 ='ower Consumer 1ist>.................................................................................................................. 322
+$( 1xa%pleH Power Source 0a%e Space #&#
++ TH1"MAL MA0A;1M10T#&A
+++ Ther%al Control #&A
44.4.4 Active, 'assive, and Critical 'olicies........................................................................................................32+
44.4.2 -(namicall( Changing Cooling Temperature Trip 'oints........................................................................329
44.4.3 -etecting Temperature Changes...............................................................................................................328
44.4." Active Cooling......................................................................................................................................... 33
44.4.* 'assive Cooling........................................................................................................................................ 33
44.4.+ Critical !hutdown..................................................................................................................................... 332
++& Cooling Preferences ###
44.2.4 .valuating Thermal -evice 1ists.............................................................................................................33"
44.2.2 .valuating -evice Thermal 3elationship %nformation..............................................................................33*
++# Ther%al 3!Cects ##A
44.3.4 CACx =Active Cooling>............................................................................................................................. 33+
44.3.2 CA1x =Active 1ist>................................................................................................................................... 33+
44.3.3 CC3T =Critical Temperature>....................................................................................................................33+
44.3." C@2T =@ot Temperature>......................................................................................................................... 339
44.3.* C'!1 ='assive 1ist>.................................................................................................................................. 339
44.3.+ C'!D ='assive>......................................................................................................................................... 339
44.3.9 C3TD =3elative Temperature Dalues>....................................................................................................... 338
44.3.8 C!C' =!et Cooling 'olic(>.......................................................................................................................338
44.3.6 CTC4 =Thermal Constant 4>......................................................................................................................3"4
44.3.4 CTC2 =Thermal Constant 2>....................................................................................................................3"4
44.3.44 CTM' =Temperature>.............................................................................................................................. 3"4
44.3.42 CT'T =Trip 'oint Temperature>..............................................................................................................3"4
44.3.43 CT3T =Thermal 3elationship Ta0le>.......................................................................................................3"4
44.3.4" CT!' =Thermal !ampling 'eriod>...........................................................................................................3"2
44.3.4* CT!T =Temperature !ensor Threshold>...................................................................................................3"3
44.3.4+ CT?- =Thermal ?one -evices>.............................................................................................................. 3"3
44.3.49 CT?M =Thermal ?one Mem0er>.............................................................................................................3"3
44.3.48 CT?' =Thermal ?one 'olling>................................................................................................................ 3"3
++( 0ative 3S 5evice 5river Ther%al Interfaces#((
++A Ther%al Ione Interface "eJuire%ents #((
++- Ther%al Ione 1xa%ples #(A
44.+.4 ./ample< The ;asic Thermal ?one.......................................................................................................... 3"*
44.+.2 ./ample< Multiple&!peed 5ans................................................................................................................. 3"+
44.+.3 ./ample< Thermal ?one with Multiple -evices.......................................................................................3"8
+& ACPI 1M<15515 C30T"3LL1" I0T1"6AC1 SP1CI6ICATI30#A#
+&+ 1%!edded Controller Interface 5escription#A#
+&& 1%!edded Controller "egister 5escriptions#A-
42.2.4 .m0edded Controller !tatus, .CC!C =3>.................................................................................................3*9
42.2.2 .m0edded Controller Command, .CC!C =W>.........................................................................................3*8
42.2.3 .m0edded Controller -ata, .CC-ATA =3FW>.........................................................................................3*8
+&# 1%!edded Controller Co%%and Set#A/
42.3.4 3ead .m0edded Controller, 3-C.C =/8>.............................................................................................3*8
42.3.2 Write .m0edded Controller, W3C.C =/84>...........................................................................................3*8
42.3.3 ;urst .na0le .m0edded Controller, ;.C.C =/82>.................................................................................3*6
42.3." ;urst -isa0le .m0edded Controller, ;-C.C =/83>...............................................................................3*6
42.3.* Guer( .m0edded Controller, G3C.C =/8">...........................................................................................3*6
+&( SM<us Host Controller 0otification Header >3ptional?' 3SDSM<D17T#-$
+&A 1%!edded Controller 6ir%ware #-$
+&- Interrupt Model #-$
42.+.4 .vent %nterrupt Model.............................................................................................................................. 3+4
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42.+.2 Command %nterrupt Model.......................................................................................................................3+4
+&. 1%!edded Controller Interfacing Algorith%s#-+
+&/ 1%!edded Controller 5escription Infor%ation#-&
+&, SM<us Host Controller Interface via 1%!edded Controller#-&
42.6.4 3egister -escription................................................................................................................................. 3+2
42.6.2 'rotocol -escription................................................................................................................................. 3++
42.6.3 !M;us 3egister !et................................................................................................................................. 39
+&+$ SM<us 5evices #.+
42.4.4 !M;us -evice Access 3estrictions........................................................................................................392
42.4.2 !M;us -evice Command Access 3estriction........................................................................................392
+&++ 5efining an 1%!edded Controller 5evice in ACPI 0a%espace#.&
42.44.4 ./ample< .C -efinition A!1 Code........................................................................................................ 393
+&+& 5efining an 1C SM<us Host Controller in ACPI 0a%espace#.#
42.42.4 ./ample< .C !M;us @ost Controller A!1&Code..................................................................................393
+# ACPI S4ST1M MA0A;1M10T <2S I0T1"6AC1 SP1CI6ICATI30#.A
+#+ SM<us 3verview #.A
43.4.4 !M;us !lave Addresses...........................................................................................................................39*
43.4.2 !M;us 'rotocols...................................................................................................................................... 39*
43.4.3 !M;us !tatus Codes................................................................................................................................ 39+
43.4." !M;us Command Dalues......................................................................................................................... 39+
+#& 5eclaring SM<us Host Controller 3!Cects#..
+## 5eclaring SM<us 5evices #..
+#( 5eclaring SM<us 3peration "egions#./
+#A 5eclaring SM<us 6ields #.,
+#- 5eclaring and 2sing an SM<us 5ata <uffer#/+
+#. 2sing the SM<us Protocols #/&
43.9.4 3eadFWrite Guick =!M;Guick>...............................................................................................................382
43.9.2 !endF3eceive ;(te =!M;!end3eceive>...................................................................................................382
43.9.3 3eadFWrite ;(te =!M;;(te>....................................................................................................................383
43.9." 3eadFWrite Word =!M;Word>.................................................................................................................383
43.9.* 3eadFWrite ;lock =!M;;lock>................................................................................................................38"
43.9.+ Word 'rocess Call =!M;'rocessCall>......................................................................................................38*
43.9.9 ;lock 'rocess Call =!M;;lock'rocessCall>............................................................................................38*
+( S4ST1M A55"1SS MAP I0T1"6AC1S#/.
+(+ I0T +AH' 1/&$H - Kuer) S)ste% Address Map#/.
+(& 1/&$ Assu%ptions and Li%itations #/,
+(# 16I ;etMe%or)Map>? <oot Services 6unction#/,
+(( 16I Assu%ptions and Li%itations #,+
+(A 1xa%ple Address Map #,+
+(- 1xa%pleH 3perating S)ste% 2sage#,#
+A :AEI0; A05 SL11PI0;#,A
+A+ Sleeping States #,-
4*.4.4 !4 !leeping !tate..................................................................................................................................... 368
4*.4.2 !2 !leeping !tate..................................................................................................................................... 368
4*.4.3 !3 !leeping !tate..................................................................................................................................... 366
4*.4." !" !leeping !tate..................................................................................................................................... 366
4*.4.* !* !oft 2ff !tate...................................................................................................................................... "
4*.4.+ Transitioning from the Working to the !leeping !tate.............................................................................."4
4*.4.9 Transitioning from the Working to the !oft 2ff !tate..............................................................................."4
+A& 6lushing Caches ($+
+A# InitialiBation ($&
4*.3.4 'lacing the !(stem in AC'% Mode........................................................................................................... ""
4*.3.2 ;%2! %nitialiHation of Memor(................................................................................................................. "*
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4*.3.3 2! 1oading.............................................................................................................................................. "9
4*.3." ./iting AC'% Mode.................................................................................................................................. "8
+- 030-20I63"M M1M3"4 ACC1SS >02MA? A"CHIT1CT2"1 PLAT63"MS($,
+-+ 02MA 0ode ($,
+-& S)ste% Localit) ($,
4+.2.4 !(stem 3esource Affinit( Ta0le -efinition.............................................................................................."6
+-# S)ste% Localit) 5istance Infor%ation(+$
+. ACPI S32"C1 LA0;2A;1 >ASL? "161"10C1(++
+.+ ASL Language ;ra%%ar (++
49.4.4 A!1 $rammar Notation........................................................................................................................... "42
49.4.2 A!1 Name and 'athname Terms.............................................................................................................. "43
49.4.3 A!1 3oot and !econdar( Terms............................................................................................................... "43
49.4." A!1 -ata and Constant Terms.................................................................................................................. "4"
49.4.* A!1 2pcode Terms.................................................................................................................................. "4+
49.4.+ A!1 'rimar( =Terminal> Terms................................................................................................................"49
49.4.9 A!1 'arameter Ee(word Terms..............................................................................................................."2+
49.4.8 A!1 3esource Template Terms................................................................................................................. "29
+.& ASL Concepts (##
49.2.4 A!1 Names.............................................................................................................................................. "33
49.2.2 A!1 1iteral Constants.............................................................................................................................. "33
49.2.3 A!1 3esource Templates.......................................................................................................................... "3*
49.2." A!1 Macros............................................................................................................................................. "3+
49.2.* A!1 -ata T(pes........................................................................................................................................ "3+
+.# ASL 3perator Su%%ar) ((.
+.( ASL 3perator Su%%ar) <) T)pe ((,
+.A ASL 3perator "eference (A&
49.*.4 Ac:uire =Ac:uire a Mute/>......................................................................................................................."*2
49.*.2 Add =%nteger Add>.................................................................................................................................... "*2
49.*.3 Alias =-eclare Name Alias>......................................................................................................................"*3
49.*." And =%nteger ;itwise And>....................................................................................................................... "*3
49.*.* Argx =Method Argument -ata 20#ects>...................................................................................................."*3
49.*.+ ;ank5ield =-eclare ;ankF-ata 5ield>......................................................................................................"*3
49.*.9 ;reak =;reak from While>........................................................................................................................ "*"
49.*.8 ;reak'oint =./ecution ;reak 'oint>........................................................................................................"**
49.*.6 ;uffer =-eclare ;uffer 20#ect>................................................................................................................."**
49.*.4 Case =./pression for Conditional ./ecution>........................................................................................."**
49.*.44 Concatenate =Concatenate -ata>............................................................................................................. "*+
49.*.42 Concatenate3esTemplate =Concatenate 3esource Templates>................................................................"*+
49.*.43 Cond3ef2f =Create 20#ect 3eference Conditionall(>............................................................................"*+
49.*.4" Continue =Continue %nnermost .nclosing While>..................................................................................."*9
49.*.4* Cop(20#ect =Cop( and !tore 20#ect>....................................................................................................."*9
49.*.4+ Create;it5ield =Create 4&;it ;uffer 5ield>............................................................................................."*9
49.*.49 Create;(te5ield =Create 8&;it ;uffer 5ield>..........................................................................................."*8
49.*.48 Create-Word5ield =Create 32&;it ;uffer 5ield>....................................................................................."*8
49.*.46 Create5ield =Create Ar0itrar( 1ength ;uffer 5ield>................................................................................"*8
49.*.2 CreateGWord5ield =Create +"&;it ;uffer 5ield>....................................................................................."*8
49.*.24 CreateWord5ield =Create 4+&;it ;uffer 5ield>......................................................................................."*6
49.*.22 -ataTa0le3egion =Create -ata Ta0le 2peration 3egion>......................................................................."*6
49.*.23 -e0ug =-e0ugger 2utput>......................................................................................................................"*6
49.*.2" -ecrement =%nteger -ecrement>............................................................................................................. "+
49.*.2* -efault =-efault ./ecution 'ath in !witch>..........................................................................................."+
49.*.2+ -efinition;lock =-eclare -efinition ;lock>..........................................................................................."+
49.*.29 -eref2f =-ereference an 20#ect 3eference>.........................................................................................."+4
49.*.28 -evice =-eclare ;usF-evice 'ackage>..................................................................................................."+4
49.*.26 -ivide =%nteger -ivide>.......................................................................................................................... "+2
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49.*.3 -MA =-MA 3esource -escriptor Macro>.............................................................................................."+3
49.*.34 -Word%2 =-Word %2 3esource -escriptor Macro>..............................................................................."+3
49.*.32 -WordMemor( =-Word Memor( 3esource -escriptor Macro>............................................................."+*
49.*.33 -Word!pace =-Word !pace 3esource -escriptor Macro>....................................................................."++
49.*.3" .%!A%- =.%!A %- !tring To %nteger Conversion Macro>......................................................................."+9
49.*.3* .lse =Alternate ./ecution>..................................................................................................................... "+8
49.*.3+ .lse%f =AlternateFConditional ./ecution>..............................................................................................."+8
49.*.39 .nd-ependent5n =.nd -ependent 5unction 3esource -escriptor Macro>............................................."+6
49.*.38 .vent =-eclare .vent !(nchroniHation 20#ect>......................................................................................"+6
49.*.36 ./tended%2 =./tended %2 3esource -escriptor Macro>........................................................................."9
49.*." ./tendedMemor( =./tended Memor( 3esource -escriptor Macro>......................................................"94
49.*."4 ./tended!pace =./tended Address !pace 3esource -escriptor Macro>................................................."93
49.*."2 ./ternal =-eclare ./ternal 20#ects>......................................................................................................."9"
49.*."3 5atal =5atal .rror Check>........................................................................................................................"9"
49.*."" 5ield =-eclare 5ield 20#ects>................................................................................................................."9*
49.*."* 5ind!et1eft;it =5ind 5irst !et 1eft ;it>................................................................................................."99
49.*."+ 5ind!et3ight;it =5ind 5irst !et 3ight ;it>............................................................................................."99
49.*."9 5i/ed%2 =5i/ed %2 3esource -escriptor Macro>...................................................................................."99
49.*."8 5rom;C- =Convert ;C- To %nteger>...................................................................................................."98
49.*."6 5unction =-eclare Control Method>......................................................................................................."98
49.*.* %f =Conditional ./ecution>......................................................................................................................"96
49.*.*4 %nclude =%nclude Additional A!1 5ile>...................................................................................................."96
49.*.*2 %ncrement =%nteger %ncrement>................................................................................................................ "8
49.*.*3 %nde/ =%nde/ed 3eference To Mem0er 20#ect>......................................................................................."8
49.*.*" %nde/5ield =-eclare %nde/F-ata 5ields>.................................................................................................."82
49.*.** %nterrupt =%nterrupt 3esource -escriptor Macro>...................................................................................."83
49.*.*+ %2 =%2 3esource -escriptor Macro>......................................................................................................."8"
49.*.*9 %3G =%nterrupt 3esource -escriptor Macro>..........................................................................................."8*
49.*.*8 %3GNo5lags =%nterrupt 3esource -escriptor Macro>.............................................................................."8*
49.*.*6 1And =1ogical And>............................................................................................................................... "8+
49.*.+ 1.:ual =1ogical .:ual>.......................................................................................................................... "8+
49.*.+4 1$reater =1ogical $reater>..................................................................................................................... "8+
49.*.+2 1$reater.:ual =1ogical $reater Than 2r .:ual>..................................................................................."89
49.*.+3 11ess =1ogical 1ess>.............................................................................................................................. "89
49.*.+" 11ess.:ual =1ogical 1ess Than 2r .:ual>............................................................................................."89
49.*.+* 1Not =1ogical Not>................................................................................................................................ "88
49.*.++ 1Not.:ual =1ogical Not .:ual> >........................................................................................................... "88
49.*.+9 1oad =1oad -efinition ;lock>................................................................................................................ "88
49.*.+8 1oadTa0le =1oad -efinition ;lock 5rom A!-T>..................................................................................."86
49.*.+6 1ocalx =Method 1ocal -ata 20#ects>......................................................................................................"6
49.*.9 12r =1ogical 2r>.................................................................................................................................... "6
49.*.94 Match =5ind 20#ect Match>...................................................................................................................."6
49.*.92 Memor(2" =Memor( 3esource -escriptor Macro>................................................................................"64
49.*.93 Memor(32 =Memor( 3esource -escriptor Macro>................................................................................"62
49.*.9" Memor(325i/ed =Memor( 3esource -escriptor Macro>........................................................................"63
49.*.9* Method =-eclare Control Method>........................................................................................................."63
49.*.9+ Mid =./tract 'ortion of ;uffer or !tring>..............................................................................................."6"
49.*.99 Mod =%nteger Modulo>............................................................................................................................"6"
49.*.98 Multipl( =%nteger Multipl(>...................................................................................................................."6*
49.*.96 Mute/ =-eclare !(nchroniHationFMute/ 20#ect>...................................................................................."6*
49.*.8 Name =-eclare Named 20#ect>.............................................................................................................."6*
49.*.84 NAnd =%nteger ;itwise Nand>................................................................................................................."6+
49.*.82 No2p Code =No 2peration>................................................................................................................... "6+
49.*.83 N2r =%nteger ;itwise Nor>...................................................................................................................... "6+
49.*.8" Not =%nteger ;itwise Not>....................................................................................................................... "69
49.*.8* Notif( =Notif( 20#ect of .vent>............................................................................................................. "69
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49.*.8+ 20#ectT(pe =$et 20#ect T(pe>................................................................................................................"69
49.*.89 2ne =Constant 2ne 20#ect>...................................................................................................................."68
49.*.88 2nes =Constant 2nes 20#ect>................................................................................................................."68
49.*.86 2peration3egion =-eclare 2peration 3egion>........................................................................................"68
49.*.6 2r =%nteger ;itwise 2r>.......................................................................................................................... *
49.*.64 'ackage =-eclare 'ackage 20#ect>......................................................................................................... *
49.*.62 'ower3esource =-eclare 'ower 3esource>............................................................................................*4
49.*.63 'rocessor =-eclare 'rocessor>................................................................................................................ *4
49.*.6" GWord%2 =GWord %2 3esource -escriptor Macro>...............................................................................*2
49.*.6* GWordMemor( =GWord Memor( 3esource -escriptor Macro>.............................................................*3
49.*.6+ GWord!pace =GWord !pace 3esource -escriptor Macro>.....................................................................**
49.*.69 3ef2f =Create 20#ect 3eference>...........................................................................................................*+
49.*.68 3egister =$eneric 3egister 3esource -escriptor Macro>........................................................................*9
49.*.66 3elease =3elease a Mute/ !(nchroniHation 20#ect>...............................................................................*9
49.*.4 3eset =3eset an .vent !(nchroniHation 20#ect>...................................................................................*8
49.*.44 3esourceTemplate =3esource To ;uffer Conversion Macro>................................................................*8
49.*.42 3eturn =3eturn from Method ./ecution>..............................................................................................*8
49.*.43 3evision =Constant 3evision 20#ect>...................................................................................................*8
49.*.4" !cope =2pen Named !cope>.................................................................................................................*6
49.*.4* !hift1eft =%nteger !hift 1eft>................................................................................................................ *6
49.*.4+ !hift3ight =%nteger !hift 3ight>............................................................................................................ *4
49.*.49 !ignal =!ignal a !(nchroniHation .vent>..............................................................................................*4
49.*.48 !iHe2f =$et -ata 20#ect !iHe>.............................................................................................................. *4
49.*.46 !leep =Milliseconds !leep>................................................................................................................... *4
49.*.44 !tall =!tall for a !hort Time>................................................................................................................. *44
49.*.444 !tart-ependent5n =!tart -ependent 5unction 3esource -escriptor Macro>.........................................*44
49.*.442 !tart-ependent5nNo'ri =!tart -ependent 5unction 3esource -escriptor Macro>...............................*42
49.*.443 !tore =!tore an 20#ect>.........................................................................................................................*42
49.*.44" !u0tract =%nteger !u0tract>.................................................................................................................... *42
49.*.44* !witch =!elect Code To ./ecute ;ased 2n ./pression>.......................................................................*43
49.*.44+ Thermal?one =-eclare Thermal ?one>.................................................................................................*4"
49.*.449 Timer =$et +"&;it Timer Dalue>............................................................................................................*4*
49.*.448 To;C- =Convert %nteger to ;C->........................................................................................................ *4*
49.*.446 To;uffer =Convert -ata to ;uffer>.......................................................................................................*4+
49.*.42 To-ecimal!tring =Convert -ata to -ecimal !tring>.............................................................................*4+
49.*.424 To@e/!tring =Convert -ata to @e/adecimal !tring>............................................................................*4+
49.*.422 To%nteger =Convert -ata to %nteger>.....................................................................................................*4+
49.*.423 To!tring =Convert ;uffer To !tring>.....................................................................................................*49
49.*.42" To,,%- =Convert !tring to ,,%- Macro>...........................................................................................*49
49.*.42* ,nicode =!tring To ,nicode Conversion Macro>.................................................................................*48
49.*.42+ ,nload =,nload -efinition ;lock>.......................................................................................................*48
49.*.429 Dendor1ong =1ong Dendor 3esource -escriptor>.................................................................................*48
49.*.428 Dendor!hort =!hort Dendor 3esource -escriptor>................................................................................*46
49.*.426 Wait =Wait for a !(nchroniHation .vent>..............................................................................................*46
49.*.43 While =Conditional 1oop>....................................................................................................................*2
49.*.434 Word;usNum0er =Word ;us Num0er 3esource -escriptor Macro>....................................................*2
49.*.432 Word%2 =Word %2 3esource -escriptor Macro>...................................................................................*24
49.*.433 Word!pace =Word !pace 3esource -escriptor Macro> >......................................................................*23
49.*.43" A2r =%nteger ;itwise Aor>.................................................................................................................... *2"
49.*.43* ?ero =Constant ?ero 20#ect>.................................................................................................................*2"
+/ ACPI MACHI01 LA0;2A;1 >AML? SP1CI6ICATI30A&A
+/+ 0otation Conventions A&A
+/& AML ;ra%%ar 5efinition A&-
48.2.4 Ta0le and Ta0le @eader .ncoding............................................................................................................*2+
48.2.2 Name 20#ects .ncoding...........................................................................................................................*2+
48.2.3 -ata 20#ects .ncoding............................................................................................................................. *29
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48.2." 'ackage 1ength .ncoding........................................................................................................................ *28
48.2.* Term 20#ects .ncoding............................................................................................................................ *28
48.2.+ Miscellaneous 20#ects .ncoding.............................................................................................................. *3"
+/# AML <)te Strea% <)te 7alues A#A
+/( AML 1ncoding of 0a%es in the 0a%espaceA#,
A 517IC1 CLASS PM SP1CI6ICATI30SA(+
A+ 3verview A(+
A& 5evice Power States A(+
A.2.4 ;us 'ower Management..........................................................................................................................*"2
A.2.2 -ispla( 'ower Management....................................................................................................................*"2
A.2.3 'CMC%AF'CCA3-FCard;us 'ower Management.................................................................................*"2
A.2." 'C% 'ower Management..........................................................................................................................*"2
A.2.* ,!; 'ower Management........................................................................................................................*"2
A.2.+ -evice Classes........................................................................................................................................ *"3
A# 5efault 5evice Class A(#
A.3.4 -efault 'ower !tate -efinitions.............................................................................................................. *"3
A.3.2 -efault 'ower Management 'olic(......................................................................................................... *"3
A.3.3 -efault Wake .vents............................................................................................................................... *""
A.3." Minimum 'ower Capa0ilities..................................................................................................................*""
A( Audio 5evice Class A((
A.".4 'ower !tate -efinitions...........................................................................................................................*""
A.".2 'ower Management 'olic(......................................................................................................................*""
A.".3 Wake .vents............................................................................................................................................ *"*
A."." Minimum 'ower Capa0ilities..................................................................................................................*"*
AA C3M Port 5evice Class A(A
A.*.4 'ower !tate -efinitions...........................................................................................................................*"+
A.*.2 'ower Management 'olic(......................................................................................................................*"+
A.*.3 Wake .vents............................................................................................................................................ *"+
A.*." Minimum 'ower Capa0ilities..................................................................................................................*"+
A- 5ispla) 5evice Class A(-
A.+.4 'ower !tate -efinitions...........................................................................................................................*"9
A.+.2 'ower Management 'olic( for the -ispla( Class....................................................................................**2
A.+.3 Wake .vents............................................................................................................................................ **3
A.+." Minimum 'ower Capa0ilities..................................................................................................................**3
A.+.* 'erformance !tates for -ispla( Class -evices.....................................................................................**3
A. Input 5evice Class AAA
A.9.4 'ower !tate -efinitions...........................................................................................................................***
A.9.2 'ower Management 'olic(......................................................................................................................***
A.9.3 Wake .vents............................................................................................................................................ **+
A.9." Minimum 'ower Capa0ilities..................................................................................................................**+
A/ Mode% 5evice Class AA-
A.8.4 Technolog( 2verview............................................................................................................................. **+
A.8.2 'ower !tate -efinitions...........................................................................................................................**9
A.8.3 'ower Management 'olic(......................................................................................................................**8
A.8." Wake .vents............................................................................................................................................ **8
A.8.* Minimum 'ower Capa0ilities..................................................................................................................**8
A, 0etwork 5evice Class AA,
A.6.4 'ower !tate -efinitions...........................................................................................................................**6
A.6.2 'ower Management 'olic(......................................................................................................................*+
A.6.3 Wake .vents............................................................................................................................................ *+
A.6." Minimum 'ower Capa0ilities..................................................................................................................*+
A+$ PC Card Controller 5evice ClassA-$
A.4.4 'ower !tate -efinitions.........................................................................................................................*+4
A.4.2 'ower Management 'olic(....................................................................................................................*+2
A.4.3 Wake .vents.......................................................................................................................................... *+2
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A.4." Minimum 'ower Capa0ilities................................................................................................................*+2
A++ Storage 5evice Class A-#
A.44.4 'ower !tate -efinitions......................................................................................................................... *+3
A.44.2 'ower Management 'olic(.................................................................................................................... *+"
A.44.3 Wake .vents.......................................................................................................................................... *+"
A.44." Minimum 'ower Capa0ilities................................................................................................................ *+"
< ACPI 1=T10SI30S 63" 5ISPLA4 A5APT1"SA-A
<+ Introduction A-A
<& 5efinitions A--
<# ACPI 0a%espace A--
<( 5ispla)-specific Methods A-.
;.".4 C-2! =.na0leF-isa0le 2utput !witching>..............................................................................................*+9
;.".2 C-2- =.numerate All -evices Attached to the -ispla( Adapter>...........................................................*+8
;.".3 C32M =$et 32M -ata>.......................................................................................................................... *94
;."." C$'- =$et '2!T -evice>....................................................................................................................... *92
;.".* C!'- =!et '2!T -evice>........................................................................................................................*92
;.".+ CD'2 =Dideo '2!T 2ptions>.................................................................................................................. *93
<A 0otifications for 5ispla) 5evices A.#
<- 3utput 5evice-specific Methods A.(
;.+.4 CA-3 =3eturn the ,ni:ue %- for this -evice>........................................................................................*9"
;.+.2 C;C1 =Guer( 1ist of ;rightness Control 1evels !upported>...................................................................*9"
;.+.3 C;CM =!et the ;rightness 1evel>............................................................................................................ *9*
;.+." C;GC =;rightness Guer( Current level>..................................................................................................*9*
;.+.* C--C =3eturn the .-%- for this -evice>................................................................................................*9*
;.+.+ C-C! =3eturn the !tatus of 2utput -evice>............................................................................................*9+
;.+.9 C-$! =Guer( $raphics !tate>................................................................................................................. *9+
;.+.8 C-!! I -evice !et !tate..........................................................................................................................*99
<. 0otifications Specific to 3utput 5evicesA./
</ 0otes on State Changes A./
I051=A/$
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1 Introduction
The Advanced Configuration and 'ower %nterface =AC'%> specification was developed to esta0lish industr(
common interfaces ena0ling ro0ust operating s(stem =2!>&directed mother0oard device configuration and
power management of 0oth devices and entire s(stems. AC'% is the ke( element in 2perating !(stem&
directed configuration and 'ower Management =2!'M>.
AC'% evolves the e/isting collection of power management ;%2! code, Advanced 'ower Management
=A'M> application programming interfaces =A'%s, 'N';%2! A'%s, Multiprocessor !pecification =M'!>
ta0les and so on into a well&defined power management and configuration interface specification. AC'%
provides the means for an orderl( transition from e/isting =legac(> hardware to AC'% hardware, and it
allows for 0oth AC'% and legac( mechanisms to e/ist in a single machine and to 0e used as needed.
5urther, new s(stem architectures are 0eing 0uilt that stretch the limits of current 'lug and 'la( interfaces.
AC'% evolves the e/isting mother0oard configuration interfaces to support these advanced architectures in
a more ro0ust, and potentiall( more efficient manner.
The interfaces and 2!'M concepts defined within this specification are suita0le to all classes of computers
including =0ut not limited to> desktop, mo0ile, workstation, and server machines. 5rom a power
management perspective, 2!'MFAC'% promotes the concept that s(stems should conserve energ( 0(
transitioning unused devices into lower power states including placing the entire s(stem in a low&power
state =sleeping state> when possi0le.
This document descri0es AC'% hardware interfaces, AC'% software interfaces and AC'% data structures
that, when implemented, ena0le support for ro0ust 2!&directed configuration and power management
=2!'M>.
1.1 Principal Goals
AC'% is the ke( element in implementing 2!'M. AC'%&defined interfaces are intended for wide adoption
to encourage hardware and software vendors to 0uild AC'%&compati0le =and, thus, 2!'M&compati0le>
implementations.
The principal goals of AC'% and 2!'M are to<
4. .na0le all computer s(stems to implement mother0oard configuration and power management
functions, using appropriate costFfunction tradeoffs.
Computer s(stems include =0ut are not limited to> desktop, mo0ile, workstation, and server
machines.
Machine implementers have the freedom to implement a wide range of solutions, from the ver(
simple to the ver( aggressive, while still maintaining full 2! support.
Wide implementation of power management will make it practical and compelling for applications
to support and e/ploit it. %t will make new uses of 'Cs practical and e/isting uses of 'Cs more
economical.
2. .nhance power management functionalit( and ro0ustness.
'ower management policies too complicated to implement in a 32M ;%2! can 0e implemented
and supported in the 2!, allowing ine/pensive power managed hardware to support ver( ela0orate
power management policies.
$athering power management information from users, applications, and the hardware together
into the 2! will ena0le 0etter power management decisions and e/ecution.
,nification of power management algorithms in the 2! will reduce conflicts 0etween the
firmware and 2! and will enhance relia0ilit(.
3. 5acilitate and accelerate industr(&wide implementation of power management.
2!'M and AC'% will reduce the amount of redundant investment in power management
throughout the industr(, as this investment and function will 0e gathered into the 2!. This will
allow industr( participants to focus their efforts and investments on innovation rather than simple
parit(.
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2 Advanced Configuration and 'ower %nterface !pecification
The 2! can evolve independentl( of the hardware, allowing all AC'%&compati0le machines to
gain the 0enefits of 2! improvements and innovations.
". Create a ro0ust interface for configuring mother0oard devices.
.na0le new advanced designs not possi0le with e/isting interfaces.
1.2 Power Management Rationale
%t is necessar( to move power management into the 2! and to use an a0stract interface =AC'%> 0etween the
2! and the hardware to achieve the principal goals set forth a0ove.
Minimal support for power management inhi0its application vendors from supporting or
e/ploiting it.
o Moving power management functionalit( into the 2! makes it availa0le on ever(
machine on which the 2! is installed. The level of functionalit( =power savings, and so
on> varies from machine to machine, 0ut users and applications will see the same power
interfaces and semantics on all 2!'M machines.
o This will ena0le application vendors to invest in adding power management functionalit(
to their products.
1egac( power management algorithms were restricted 0( the information availa0le to the ;%2!
that implemented them. This limited the functionalit( that could 0e implemented.
o CentraliHing power management information and directives from the user, applications,
and hardware in the 2! allows the implementation of more powerful functionalit(. 5or
e/ample, an 2! can have a polic( of dividing %F2 operations into normal and laH(. 1aH(
%F2 operations =such as a word processor saving files in the 0ackground> would 0e
gathered up into clumps and done onl( when the re:uired %F2 device is powered up for
some other reason. A non&laH( %F2 re:uest made when the re:uired device was powered
down would cause the device to 0e powered up immediatel(, the non&laH( %F2 re:uest to
0e carried out, and an( pending laH( %F2 operations to 0e done. !uch a polic( re:uires
knowing when %F2 devices are powered up, knowing which application %F2 re:uests are
laH(, and 0eing a0le to assure that such laH( %F2 operations do not starve.
o Appliance functions, such as answering machines, re:uire glo0all( coherent power
decisions. 5or e/ample, a telephone&answering application could call the 2! and assert,
J% am waiting for incoming phone callsK an( sleep state the s(stem enters must allow me
to wake and answer the telephone in 4 second.L Then, when the user presses the JoffL
0utton, the s(stem would pick the deepest sleep state consistent with the needs of the
phone answering service.
;%2! code has 0ecome ver( comple/ to deal with power management. %t is difficult to make work
with an 2! and is limited to static configurations of the hardware.
o There is much less state information for the ;%2! to retain and manage =0ecause the 2!
manages it>.
o 'ower management algorithms are unified in the 2!, (ielding much 0etter integration
0etween the 2! and the hardware.
o ;ecause additional AC'% ta0les =-efinition ;locks> can 0e loaded, for e/ample, when a
mo0ile s(stem docks, the 2! can deal with d(namic machine configurations.
o ;ecause the ;%2! has fewer functions and the( are simpler, it is much easier =and
therefore cheaper> to implement and support.
The e/isting structure of the 'C platform constrains 2! and hardware designs.
;ecause AC'% is a0stract, the 2! can evolve separatel( from the hardware and, likewise, the
hardware from the 2!.
AC'% is 0( nature more porta0le across operating s(stems and processors. AC'% control methods
allow for ver( fle/i0le implementations of particular features.
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1.3 Legacy Support
AC'% provides support for an orderl( transition from legac( hardware to AC'% hardware, and allows for
0oth mechanisms to e/ist in a single machine and 0e used as needed.
Ta!le +-+ Hardware T)pe vs 3S T)pe Interaction
HardwareG3S Legac) 3S ACPI 3S with 3SPM
1egac( hardware A legac( 2! on legac( hardware
does what it alwa(s did.
%f the 2! lacks legac( support, legac(
support is completel( contained within
the hardware functions.
1egac( and AC'%
hardware support in
machine
%t works #ust like a legac( 2! on
legac( hardware.
-uring 0oot, the 2! tells the hardware to
switch from legac( to 2!'MFAC'%
mode and from then on, the s(stem has
full 2!'MFAC'% support.
AC'%&onl( hardware There is no power management. There is full 2!'MFAC'% support.
1.4 OEM Implementation Strategy
An( 2.M is, as alwa(s, free to 0uild hardware as the( see fit. $iven the e/istence of the AC'%
specification, two general implementation strategies are possi0le<
An original e:uipment manufacturer =2.M> can adopt the 2! vendor&provided AC'% 2!'M
software and implement the hardware part of the AC'% specification =for a given platform> in one of
man( possi0le wa(s.
An 2.M can develop a driver and hardware that are not AC'%&compati0le. This strateg( opens up
even more hardware implementation possi0ilities. @owever, 2.Ms who implement hardware that is
2!'M&compati0le 0ut not AC'%&compati0le will 0ear the cost of developing, testing, and distri0uting
drivers for their implementation.
1.5 Power and Sleep Buttons
2!'M provides a new appliance interface to consumers. %n particular, it provides for a sleep 0utton that is a
JsoftL 0utton that does not turn the machine ph(sicall( off 0ut signals the 2! to put the machine in a soft
off or sleeping state. AC'% defines two t(pes of these JsoftL 0uttons< one for putting the machine to sleep
and one for putting the machine in soft off.
This gives the 2.M two different wa(s to implement machines< A one&0utton model or a two&0utton
model. The one&0utton model has a single 0utton that can 0e used as a power 0utton or a sleep 0utton as
determined 0( user settings. The two&0utton model has an easil( accessi0le sleep 0utton and a separate
power 0utton. %n either model, an override feature that forces the machine to the soft&off state without
2!'M interaction is also needed to deal with various rare, 0ut pro0lematic, situations.
1.6 ACPI Specifcation and the Structure Of ACPI
This specification defines AC'% hardware interfaces, AC'% software interfaces and AC'% data structures.
This specification also defines the semantics of these interfaces.
5igure 4&4 la(s out the software and hardware components relevant to 2!'MFAC'% and how the( relate to
each other. This specification descri0es the interfaces between components, the contents of the AC'%
!(stem -escription Ta0les, and the related semantics of the other AC'% components. Notice that the AC'%
!(stem -escription Ta0les, which descri0e a particular platformMs hardware, are at heart of the AC'%
implementation and the role of the AC'% !(stem 5irmware is primaril( to suppl( the AC'% Ta0les =rather
than a native instruction A'%>.
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AC'% is not a software specificationK it is not a hardware specification, although it addresses 0oth software
and hardware and how the( must 0ehave. AC'% is, instead, an interface specification comprised of 0oth
software and hardware elements.
ACPI Tables ACPI BIOS ACPI Registers
Kernel
Device
Driver
ACPI
Register
Interface
ACPI Table
Interface
ACPI BIOS
Interface
- ACPI Spec Covers this area.
- OS specific technology not part of ACPI.
- !ar"#are$Platfor% specific technology not part of ACPI.
Platfor% !ar"#are
&'isting
in"(stry
stan"ar"
register
interfaces to)
C*OS PIC
PITs ...
ACPI Driver$
A*+ Interpreter
Applications
OS
Dependent
Application
APIs
OS Specific
technologies,
interfaces, and code.
OS
Independent
technologies,
interfaces,
code, and
hardware.
BIOS
OSP* Syste% Co"e
6igure +-+ 3SPM@ACPI ;lo!al S)ste%
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There are three run&time components to AC'%<
ACPI S)ste% 5escription Ta!les -escri0e the interfaces to the hardware. !ome descriptions
limit what can 0e 0uilt =for e/ample, some controls are em0edded in fi/ed 0locks of registers and the
ta0le specifies the address of the register 0lock>. Most descriptions allow the hardware to 0e 0uilt in
ar0itrar( wa(s and can descri0e ar0itrar( operation se:uences needed to make the hardware function.
AC'% Ta0les containing J-efinition ;locksL can make use of a pseudo&code t(pe of language, the
interpretation of which is performed 0( the 2!. That is, 2!'M contains and uses an interpreter that
e/ecutes procedures encoded in the pseudo&code language and stored in the AC'% ta0les containing
J-efinition ;locks.L The pseudo&code language, known as AC'% Machine 1anguage =AM1>, is a
compact, tokeniHed, a0stract t(pe of machine language.
ACPI "egisters The constrained part of the hardware interface, descri0ed =at least in location> 0(
the AC'% !(stem -escription Ta0les.
ACPI S)ste% 6ir%ware 3efers to the portion of the firmware that is compati0le with the AC'%
specifications. T(picall(, this is the code that 0oots the machine =as legac( ;%2!s have done> and
implements interfaces for sleep, wake, and some restart operations. %t is called rarel(, compared to a
legac( ;%2!. The AC'% -escription Ta0les are also provided 0( the AC'% !(stem 5irmware.
1.7 OS and Platform Compliance
The AC'% specification contains onl( interface specifications. AC'% does not contain an( platform
compliance re:uirements. The following sections provide guidelines for class specific platform
implementations that reference AC'%&defined interfaces and guidelines for enhancements that operating
s(stems ma( re:uire to completel( support 2!'MFAC'%. The minimum feature implementation
re:uirements of an AC'%&compati0le 2! are also provided.
1.7.1 Platform Implementations of ACPI-defned Interfaces
!(stem platforms implement AC'%&defined hardware interfaces via the platform hardware and AC'%&
defined software interfaces and s(stem description ta0les via the AC'% s(stem firmware. !pecific AC'%&
defined interfaces and 2!'M concepts while appropriate for one class of machine =for e/ample, a mo0ile
s(stem>, ma( not 0e appropriate for another class of machine =for e/ample, a multi&domain enterprise
server>. %t is 0e(ond the capa0ilit( and scope of this specification to specif( all platform classes and the
appropriate AC'%&defined interfaces that should 0e re:uired for the platform class.
'latform design guide authors are encouraged to re:uire the appropriate AC'%&defined interfaces and
hardware re:uirements suita0le to the particular s(stem platform class addressed in a particular design
guide. 'latform design guides should not define alternative interfaces that provide similar functionalit( to
those defined in the AC'% specification.
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1.7.1.1
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Recommended Features and Interface Descriptions for Design Guides
Common description te/t and categor( names should 0e used in design guides to descri0e all features,
concepts, and interfaces defined 0( the AC'% specification as re:uirements for a platform class. 1isted
0elow is the recommended set of high&level te/t and categor( names to 0e used to descri0e the features,
concepts, and interfaces defined 0( AC'%.
0oteH Where definitions or relational re:uirements of interfaces are localiHed to a specific section, the
section num0er is provided. The interface definitions and relational re:uirements of the interfaces specified
0elow are generall( spread throughout the AC'% specification. The AC'% specification defines<
System address map reporting interfaces (Section 14)
ACPI System Description Tables (Section !")#
$oot System Description Pointer ($SDP)
System Description Table %eader
$oot System Description Table ($SDT)
&ixed ACPI Description Table (&ADT)
&irmware ACPI Control Str'ct're (&ACS)
Differentiated System Description Table (DSDT)
Secondary System Description Table (SSDT)
('ltiple APIC Description Table ((ADT)
Smart )attery Table (S)ST)
*xtended System Description Table (+SDT)
*mbedded Controller )oot $eso'rces Table
System $eso'rce Affinity Table (S$AT)
System ,ocality Information Table (S,IT)
ACPI-defined &ixed $egisters Interfaces (Section 4. Section !"!/)#
Power management timer control0stat's
Power or sleep b'tton wit1 S o2erride (also possible in generic space)
$eal time cloc3 wa3e'p alarm control0stat's
SCI 0S(I ro'ting control0stat's for Power (anagement and 4eneral-p'rpose e2ents
System power state controls (sleeping0wa3e control) (Section 15)
Processor power state control (c states) (Section 6)
Processor t1rottling control0stat's (Section 6)
Processor performance state control0stat's (Section 6)
4eneral-p'rpose e2ent control0stat's
4lobal ,oc3 control0stat's
System $eset control (Section 4!7!8!9)
*mbedded Controller control0stat's (Section 1")
S()'s %ost Controller (%C) control0stat's (Section 18)
Smart )attery S'bsystem (Section 15!1)
ACPI-defined 4eneric $egister Interfaces and ob:ect definitions in t1e ACPI ;amespace (Section 4!".
Section !9!)#
4eneral-p'rpose e2ent processing
(ot1erboard de2ice identification. config'ration. and insertion0remo2al (Section 9)
T1ermal <ones (Section 11)
Power reso'rce control (Section 7!1)
De2ice power state control (Section 7!")
System power state control (Section 7!8)
System indicators (Section /!1)
De2ices and de2ice controls (Section /)#
Processor (Section 6)
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Control (et1od )attery (Section 15)
Smart )attery S'bsystem (Section 15)
(obile ,id
Power or sleep b'tton wit1 S o2erride (also possible in fixed space)
*mbedded controller (Section 1")
&an
4eneric )'s )ridge
ATA Controller
&loppy Controller
4P* )loc3
(od'le
(emory
4lobal ,oc3 related interfaces
ACPI *2ent programming model (Section !9)
ACPI-defined System )I=S $esponsibilities (Section 1)
ACPI-defined State Definitions (Section ")#
4lobal system power states (4-states. S5. S)
System sleeping states (S-states S1-S4) (Section 1)
De2ice power states (D-states (Appendix )))
Processor power states (C-states) (Section 6)
De2ice and processor performance states (P-states) (Section 8. Section 6)
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1.7.1.2
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Terminology Examples for Design Guides
The following provides an e/ample of how a client platform design guide, whose goal is to re:uire ro0ust
configuration and power management for the s(stem class, could use the recommended terminolog( to
define AC'% re:uirements.
I%portantH This e/ample is provided as a guideline for how AC'% terminolog( can 0e used. %t should not
0e interpreted as a statement of AC'% re:uirements.
Platforms compliant wit1 t1is platform design g'ide m'st implement t1e following ACPI defined system
feat'res. concepts. and interfaces. along wit1 t1eir associated e2ent models#
System address map reporting interfaces
ACPI System Description Tables pro2ided in t1e system firmware
ACPI-defined &ixed $egisters Interfaces#
Power management timer control0stat's
Power or sleep b'tton wit1 S o2erride (may also be implemented in generic register space)
$eal time cloc3 wa3e'p alarm control0stat's
4eneral-p'rpose e2ent control0stat's
SCI 0S(I ro'ting control0stat's for Power (anagement and 4eneral-p'rpose e2ents
(control re>'ired only if system s'pports legacy mode)
System power state controls (sleeping0wa3e control)
Processor power state control (for C1)
4lobal ,oc3 control0stat's (if 4lobal ,oc3 interfaces are re>'ired by t1e system)
ACPI-defined 4eneric $egister Interfaces and ob:ect definitions in t1e ACPI ;amespace#
4eneral-p'rpose e2ent processing
(ot1erboard de2ice identification. config'ration. and insertion0remo2al (Section 9)
System power state control ( Section 7!8)
De2ices and de2ice controls#
Processor
Control (et1od )attery (or Smart )attery S'bsystem on a mobile system)
Smart )attery S'bsystem (or Control (et1od )attery on a mobile system)
Power or sleep b'tton wit1 S o2erride (may also be implemented in fixed register space)
4lobal ,oc3 related interfaces w1en a logical register in t1e 1ardware is s1ared between =S
and firmware en2ironments
ACPI *2ent programming model (Section !9)
ACPI-defined System )I=S $esponsibilities (Section 1)
ACPI-defined State Definitions#
System sleeping states (At least one system sleeping state. S1-S4. m'st be implemented)
De2ice power states (D-states m'st be implemented in accordance wit1 de2ice class
specifications)
Processor power states (All processors m'st s'pport t1e C1 Power State)
The following provides an e/ample of how a design guide for s(stems that e/ecute multiple 2! instances,
whose goal is to re:uire ro0ust configuration and continuous availa0ilit( for the s(stem class, could use the
recommended terminolog( to define AC'% related re:uirements.
I%portantH This e/ample is provided as a guideline for how AC'% terminolog( can 0e used. %t should not
0e interpreted as a statement of AC'% re:uirements.
Platforms compliant wit1 t1is platform design g'ide m'st implement t1e following ACPI defined system
feat'res and interfaces. along wit1 t1eir associated e2ent models#
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System address map reporting interfaces
ACPI System Description Tables pro2ided in t1e system firmware
ACPI-defined &ixed $egisters Interfaces#
Power management timer control0stat's
4eneral-p'rpose e2ent control0stat's
SCI 0S(I ro'ting control0stat's for Power (anagement and 4eneral-p'rpose e2ents
(control re>'ired only if system s'pports legacy mode)
System power state controls (sleeping0wa3e control)
Processor power state control (for C1)
4lobal ,oc3 control0stat's (if 4lobal ,oc3 interfaces are re>'ired by t1e system)
ACPI-defined 4eneric $egister Interfaces and ob:ect definitions in t1e ACPI ;amespace#
4eneral-p'rpose e2ent processing
(ot1erboard de2ice identification. config'ration. and insertion0remo2al (Section 9)
System power state control (Section 7!8)
System indicators
De2ices and de2ice controls#
Processor
4lobal ,oc3 related interfaces w1en a logical register in t1e 1ardware is s1ared between =S
and firmware en2ironments
ACPI *2ent programming model ( Section !9)
ACPI-defined System )I=S $esponsibilities (Section 1)
ACPI-defined State Definitions#
Processor power states (All processors m'st s'pport t1e C1 Power State)
1.7.2 OSPM Implementations
2! enhancements are needed to support AC'%&defined features, concepts, and interfaces, along with their
associated event models appropriate to the s(stem platform class upon which the 2! e/ecutes. This is the
implementation of 2!'M. The following outlines the 2! enhancements and elements necessar( to support
all AC'%&defined interfaces. To support AC'% through the implementation of 2!'M, the 2! needs to 0e
modified to<
,se s(stem address map reporting interfaces.
5ind and consume the AC'% !(stem -escription Ta0les.
%nterpret AC'% machine language =AM1>.
.numerate and configure mother0oard devices descri0ed in the AC'% Namespace.
%nterface with the power management timer.
%nterface with the real&time clock wake alarm.
.nter AC'% mode =on legac( hardware s(stems>.
%mplement device power management polic(.
%mplement power resource management.
%mplement processor power states in the scheduler idle handlers.
Control processor and device performance states.
%mplement the AC'% thermal model.
!upport the AC'% .vent programming model including handling !C% interrupts, managing fi/ed
events, general&purpose events, em0edded controller interrupts, and d(namic device support.
!upport ac:uisition and release of the $lo0al 1ock.
,se the reset register to reset the s(stem.
'rovide A'%s to influence power management polic(.
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42 Advanced Configuration and 'ower %nterface !pecification
%mplement driver support for AC'%&defined devices.
%mplement A'%s supporting the s(stem indicators.
!upport all s(stem states !4I!*.
1.7.3 OS Requirements
The following list descri0es the minimum re:uirements for an 2!'MFAC'%&compati0le 2!<
,se s(stem address map reporting interfaces to get the s(stem address map on %ntel Architecture
=%A> platforms<
%NT 4*@, .82@ & Guer( !(stem Address Map interface =see section 4", J!(stem Address Map
%nterfacesL>
.5% $etMemor(Map=> ;oot !ervices 5unction =see section 4", J!(stem Address Map %nterfacesL>
5ind and consume the AC'% !(stem -escription Ta0les =see section *, JAC'% !oftware
'rogramming ModelL>.
%mplementation of an AM1 interpreter supporting all defined AM1 grammar elements =see section
48, AC'% Machine 1anguage !pecificationL>.
!upport for the AC'% .vent programming model including handling !C% interrupts, managing
fi/ed events, general&purpose events, em0edded controller interrupts, and d(namic device support.
.numerate and configure mother0oard devices descri0ed in the AC'% Namespace.
%mplement support for the following AC'% devices defined within this specification<
.m0edded Controller -evice =see section 42, JAC'% .m0edded Controller %nterface
!pecificationL>
$'. ;lock -evice =see section 6.44, J$'. ;lock -eviceL>
Module -evice =see section 6.42, JModule -eviceL>
%mplementation of the AC'% thermal model =see section 44, JThermal ManagementL>.
!upport ac:uisition and release of the $lo0al 1ock.
2!&directed power management support =device drivers are responsi0le for maintaining device
conte/t as descri0ed 0( the -evice 'ower Management Class !pecifications descri0ed in Appendi/ A>.
1.8 Target Audience
This specification is intended for the following users<
2.Ms 0uilding hardware containing AC'%&compati0le interfaces
2perating s(stem and device driver developers
;%2! and AC'% s(stem firmware developers
C', and chip set vendors
'eripheral vendors
1.9 Document Organization
The AC'% specification document is organiHed into the following four parts<
The first part of the specification =sections 4 through 3> introduces AC'% and provides an
e/ecutive overview.
The second part =sections " and *> defines the AC'% hardware and software programming models.
The third part =sections + through 4+> specifies the AC'% implementation detailsK this part of the
specification is primaril( for developers.
The fourth part =sections 49 and 48> is technical reference materialK section 49 is the AC'% !ource
1anguage =A!1> reference, parts of which are referred to 0( most of the other sections in the
document.
Appendices contain device class specifications, descri0ing power management characteristics of
specific classes of devices, and device class&specific AC'% interfaces.
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1.9.1 ACPI Introduction and Overview
The first three sections of the specification provide an e/ecutive overview of AC'%.
Section +H Introduction -iscusses the purpose and goals of the specification, presents an overview of the
AC'%&compati0le s(stem architecture, specifies the minimum re:uirements for an AC'%&compati0le
s(stem, and provides references to related specifications.
Section &H 5efinition of Ter%s -efines the ke( terminolog( used in this specification. %n particular, the
glo0al s(stem states =Mechanical 2ff, !oft 2ff, !leeping, Working, and Non&Dolatile !leep> are defined in
this section, along with the device power state definitions< 2ff =-3>, -2, -4, and 5ull(&2n =->. -evice
and processor performance states =', '4, N'n> are also discussed.
Section #H ACPI 3verview $ives an overview of the AC'% specification in terms of the functional areas
covered 0( the specification< s(stem power management, device power management, processor power
management, 'lug and 'la(, handling of s(stem events, 0atter( management, and thermal management.
1.9.2 Programming Models
!ections " and * define the AC'% hardware and software programming models. This part of the
specification is primaril( for s(stem designers, developers, and pro#ect managers.
All of the implementation&oriented, reference, and platform e/ample sections of the specification that
follow =all the rest of the sections of the specification> are 0ased on the models defined in sections " and *.
These sections are the heart of the AC'% specification. There are e/tensive cross&references 0etween the
two sections.
Section (H ACPI Hardware Specification -efines a set of hardware interfaces that meet the goals of this
specification.
Section AH ACPI Software Progra%%ing Model -efines a set of software interfaces that meet the goals
of this specification.
1.9.3 Implementation Details
The third part of the specification defines the implementation details necessar( to actuall( 0uild
components that work on an AC'%&compati0le platform. This part of the specification is primaril( for
developers.
Section -H Configuration -efines the reserved 'lug and 'la( o0#ects used to configure and assign
resources to devices, and share resources and the reserved o0#ects used to track device insertion and
removal. Also defines the format of AC'%&compati0le resource descriptors.
Section .H Power and Perfor%ance Manage%ent -efines the reserved device power&management
o0#ects and the reserved&s(stem power&management o0#ects.
Section /H Processor Control -efines how the 2! manages the processorsM power consumption and other
controls while the s(stem is in the working state.
Section ,H ACPI-Specific 5evice 3!Cects 1ists the integrated devices that need support for some device&
specific AC'% controls, along with the device&specific AC'% controls that can 0e provided. Most device
o0#ects are controlled through generic o0#ects and control methods and have generic device %-sK this
section discusses the e/ceptions.
Section +$H Power Source 5evices -efines the reserved 0atter( device and AC adapter o0#ects.
Section ++H Ther%al Manage%ent -efines the reserved thermal management o0#ects.
Section +&H ACPI 1%!edded Controller Interface Specification -efines the interfaces 0etween an
AC'%&compati0le 2! and an em0edded controller.
Section +#H ACPI S)ste% Manage%ent <us Interface Specification -efines the interfaces 0etween an
AC'%&compati0le 2! and a !(stem Management ;us =!M;us> host controller.
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4" Advanced Configuration and 'ower %nterface !pecification
Section +(H S)ste% Address Map Interfaces ./plains the special %NT 4* call for use in %!AF.%!AF'C%
0us&0ased s(stems. This call supplies the 2! with a clean memor( map indicating address ranges that are
reserved and ranges that are availa0le on the mother0oard. .5%&0ased memor( address map reporting
interfaces are also descri0ed. Also descri0es memor( devices.
Section +AH :aking and Sleeping -efines in detail the transitions 0etween s(stem working and sleeping
states and their relationship to wake events. 3efers to the reserved o0#ects defined in sections +, 9, and 8.
Section +-H 0on-2nifor% Me%or) Access >02MA? Architecture Platfor%s -iscusses in detail how
AC'% define interfaces can 0e used to descri0e a N,MA architecture platform. 3efers to the reserved
o0#ects defined in sections *, +, 8, and 6.
2 Technical Reference
The fourth part of the specification contains reference material for developers.
Section +.H ACPI Source Language "eference -efines the s(nta/ of all the A!1 statements that can 0e
used to write AC'% control methods, along with e/ample s(nta/ usage.
Section +/H ACPI Machine Language Specification -efines the grammar of the language of the AC'%
virtual machine language. An A!1 translator =compiler> outputs AM1.
Appendix AH 5evice class specifications -escri0es device&specific power management 0ehavior on a per
device&class 0asis.
Appendix <H 7ideo 1xtensions Contains video device class&specific AC'% interfaces.
2.1 Related Documents
'ower management and 'lug and 'la( specifications for legac( hardware platforms are the following,
availa0le from http<FFwww.microsoft.comFwhdcFresourcesFrespecFspecsFdefault.msp/<
Ad2anced Power (anagement (AP() )I=S Specification, 3evision 4.2.
Pl'g and Play )I=S Specification, Dersion 4.a.
%ntel Architecture specifications are availa0le from http<FFdeveloper.intel.com<
Intel? Itani'm
TM
Arc1itect're Software De2eloper@s (an'al, Dolumes 4I", 3evision 2.4, %ntel Corporation,
2cto0er 22.
Itani'm
TM
Processor &amily System Abstraction ,ayer Specification, %ntel Corporation, -ecem0er 23
=7une 2" ,pdate>.
*xtensible &irmware Interface Specification. Aersion 1!15. December "55"(;o2ember "558 Bpdate).
-ocumentation and specifications for the !mart ;atter( !(stem components and the !M;us are availa0le
from http<FFwww.s0s&forum.org<
Smart )attery C1arger Specification, 3evision 4.4, !mart ;atter( !(stem %mplementers 5orum,
-ecem0er, 4668.
Smart )attery Data Specification, 3evision 4.4, !mart ;atter( !(stem %mplementers 5orum,
-ecem0er, 4668.
Smart )attery Selector Specification, 3evision 4.4, !mart ;atter( !(stem %mplementers 5orum,
-ecem0er, 4668.
Smart )attery System (anager Specification, 3evision 4., !mart ;atter( !(stem %mplementers
5orum, -ecem0er, 4668.
System (anagement )'s Specification, 3evision 4.4, !mart ;atter( !(stem %mplementers 5orum,
-ecem0er, 4668.
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3
Defnition of Terms
This specification uses a particular set of terminolog(, defined in this section. This section has three parts<
$eneral AC'% terms are defined and presented alpha0eticall(.
The AC'% glo0al s(stem states =working, sleeping, soft off, and mechanical off> are defined. $lo0al s(stem
states appl( to the entire s(stem, and are visi0le to the user.
The AC'% device power states are defined. -evice power states are states of particular devicesK as such,
the( are generall( not visi0le to the user. 5or e/ample, some devices ma( 0e in the off state even though the
s(stem as a whole is in the working state. -evice states appl( to an( device on an( 0us.
3.1 General ACPI Terminology
Advanced Configuration and Power Interface =ACPI)
As defined in this document, AC'% is a method for descri0ing hardware interfaces in terms a0stract
enough to allow fle/i0le and innovative hardware implementations and concrete enough to allow
shrink&wrap 2! code to use such hardware interfaces.
ACPI Hardware
Computer hardware with the features necessar( to support 2!'M and with the interfaces to those
features descri0ed using the -escription Ta0les as specified 0( this document.
ACPI Namespace
A hierarchical tree structure in 2!&controlled memor( that contains named o0#ects. These o0#ects ma(
0e data o0#ects, control method o0#ects, 0usFdevice package o0#ects, and so on. The 2! d(namicall(
changes the contents of the namespace at run&time 0( loading andFor unloading definition 0locks from
the AC'% Ta0les that reside in the AC'% ;%2!. All the information in the AC'% Namespace comes
from the -ifferentiated !(stem -escription Ta0le =-!-T>, which contains the -ifferentiated
-efinition ;lock, and one or more other definition 0locks.
ACPI Machine Language (AML)
'seudo&code for a virtual machine supported 0( an AC'%&compati0le 2! and in which AC'% control
methods and o0#ects are written. The AM1 encoding definition is provided in section 48, JAC'%
Machine 1anguage =AM1> !pecification.L
Advanced Programmable Interrupt Controller (APIC)
An interrupt controller architecture commonl( found on %ntel Architecture&0ased 32&0it 'C s(stems.
The A'%C architecture supports multiprocessor interrupt management =with s(mmetric interrupt
distri0ution across all processors>, multiple %F2 su0s(stem support, 82*6A compati0ilit(, and inter&
processor interrupt support. The architecture consists of local A'%Cs commonl( attached directl( to
processors and %F2 A'%Cs commonl( in chip sets.
ACPI ource Language (AL)
The programming language e:uivalent for AM1. A!1 is compiled into AM1 images. The A!1
statements are defined in section 49, JAC'% !ource 1anguage =A!1> 3eference.L
Control Method
A control method is a definition of how the 2! can perform a simple hardware task. 5or e/ample, the
2! invokes control methods to read the temperature of a thermal Hone. Control methods are written in
an encoded language called AM1 that can 0e interpreted and e/ecuted 0( the AC'%&compati0le 2!. An
AC'%&compati0le s(stem must provide a minimal set of control methods in the AC'% ta0les. The 2!
provides a set of well&defined control methods that AC'% ta0le developers can reference in their
control methods. 2.Ms can support different revisions of chip sets with one ;%2! 0( either including
control methods in the ;%2! that test configurations and respond as needed or including a different set
of control methods for each chip set revision.
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Central Processing !nit (CP!) or Processor
The part of a platform that e/ecutes the instructions that do the work. An AC'%&compati0le 2! can
0alance processor performance against power consumption and thermal states 0( manipulating the
processor performance controls. The AC'% specification defines a working state, la0eled $ =!>, in
which the processor e/ecutes instructions. 'rocessor sleeping states, la0eled C4 through C3, are also
defined. %n the sleeping states, the processor e/ecutes no instructions, thus reducing power
consumption and, potentiall(, operating temperatures. The AC'% specification also defines processor
performance states, where the processor =while in C> e/ecutes instructions, 0ut with lower
performance and =potentiall(> lower power consumption and operating temperature. 5or more
information, see section 8, J'rocessor 'ower and 'erformance !tate Configuration and Control.L
"efinition #loc$
A definition 0lock contains information a0out hardware implementation and configuration details in
the form of data and control methods, encoded in AM1. An 2.M can provide one or more definition
0locks in the AC'% Ta0les. 2ne definition 0lock must 0e provided< the -ifferentiated -efinition ;lock,
which descri0es the 0ase s(stem. ,pon loading the -ifferentiated -efinition ;lock, the 2! inserts the
contents of the -ifferentiated -efinition ;lock into the AC'% Namespace. 2ther definition 0locks,
which the 2! can d(namicall( insert and remove from the active AC'% Namespace, can contain
references to the -ifferentiated -efinition ;lock. 5or more information, see section *.2.44, J-efinition
;locks.L
"evice
@ardware component outside the core chip set of a platform. ./amples of devices are li:uid cr(stal
displa( =1C-> panels, video adapters, %ntegrated -rive .lectronics =%-.> C-&32M and hard disk
controllers, C2M ports, and so on. %n the AC'% scheme of power management, 0uses are devices. 5or
more information, see section 3.3.2, J-evice 'ower !tates.L
"evice Conte%t
The varia0le data held 0( the deviceK it is usuall( volatile. The device might forget this information
when entering or leaving certain states =for more information, see section 2.3, J-evice 'ower !tate
-efinitions.L>, in which case the 2! software is responsi0le for saving and restoring the information.
-evice Conte/t refers to small amounts of information held in device peripherals. !ee System Context!
"ifferentiated &stem "escription 'able (""')
An 2.M must suppl( a -!-T to an AC'%&compati0le 2!. The -!-T contains the -ifferentiated
-efinition ;lock, which supplies the implementation and configuration information a0out the 0ase
s(stem. The 2! alwa(s inserts the -!-T information into the AC'% Namespace at s(stem 0oot time
and never removes it.
(%tensible )irmware Interface (()I)
An interface 0etween the 2! and the platform firmware. The interface is in the form of data ta0les that
contain platform related information, and 0oot and run&time service calls that are availa0le to the 2!
and loader. Together, these provide a standard environment for 0ooting an 2!.
(mbedded Controller
The general class of microcontrollers used to support 2.M&specific implementations, mainl( in
mo0ile environments. The AC'% specification supports em0edded controllers in an( platform design,
as long as the microcontroller conforms to one of the models descri0ed in this section. The em0edded
controller performs comple/ low&level functions through a simple interface to the host
microprocessor=s>.
(mbedded Controller Interface
A standard hardware and software communications interface 0etween an 2! driver and an em0edded
controller. This allows an( 2! to provide a standard driver that can directl( communicate with an
em0edded controller in the s(stem, thus allowing other drivers within the s(stem to communicate with
and use the resources of s(stem em0edded controllers =for e/ample, !mart ;atter( and AM1 code>.
This in turn ena0les the 2.M to provide platform features that the 2! and applications can use.
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)irmware ACPI Control tructure ()AC)
A structure in readFwrite memor( that the ;%2! uses for handshaking 0etween the firmware and the
2!. The 5AC! is passed to an AC'%&compati0le 2! via the 5i/ed AC'% -escription Ta0le =5A-T>.
The 5AC! contains the s(stemMs hardware signature at last 0oot, the firmware waking vector, and the
$lo0al 1ock.
)i%ed ACPI "escription 'able ()A"')
A ta0le that contains the AC'% @ardware 3egister ;lock implementation and configuration details that
the 2! needs to directl( manage the AC'% @ardware 3egister ;locks, as well as the ph(sical address
of the -!-T, which contains other platform implementation and configuration details. An 2.M must
provide an 5A-T to an AC'%&compati0le 2! in the 3!-TFA!-T. The 2! alwa(s inserts the
namespace information defined in the -ifferentiated -efinition ;lock in the -!-T into the AC'%
Namespace at s(stem 0oot time, and the 2! never removes it.
)i%ed )eatures
A set of features offered 0( an AC'% interface. The AC'% specification places restrictions on where and
how the hardware programming model is generated. All fi/ed features, if used, are implemented as
descri0ed in this specification so that 2!'M can directl( access the fi/ed feature registers.
)i%ed )eature (vents
A set of events that occur at the AC'% interface when a paired set of status and event 0its in the fi/ed
feature registers are set at the same time. When a fi/ed feature event occurs, a s(stem control interrupt
=!C% is raised. 5or AC'% fi/ed feature events, 2!'M =or an AC'%&aware driver> acts as the event
handler.
)i%ed )eature *egisters
A set of hardware registers in fi/ed feature register space at specific address locations in s(stem %F2
address space. AC'% defines register 0locks for fi/ed features =each register 0lock gets a separate
pointer from the 5A-T>. 5or more information, see section ".+, JAC'% @ardware 5eatures.L
+eneral,Purpose (vent *egisters
The general&purpose event registers contain the event programming model for generic features. All
general&purpose events generate !C%s.
+eneric )eature
A generic feature of a platform is value&added hardware implemented through control methods and
general&purpose events.
+lobal &stem tates
$lo0al s(stem states appl( to the entire s(stem, and are visi0le to the user. The various glo0al s(stem
states are la0eled $ through $3 in the AC'% specification. 5or more information, see section 2.2,
J$lo0al !(stem !tate -efinitions.L
Ignored #its
!ome unused 0its in AC'% hardware registers are designated as JignoredL in the AC'% specification.
%gnored 0its are undefined and can return Hero or one =in contrast to reserved 0its, which alwa(s return
Hero>. !oftware ignores ignored 0its in AC'% hardware registers on reads and preserves ignored 0its on
writes.
Intel Architecture,Personal Computer (IA,PC)
A general descriptive term for computers 0uilt with processors conforming to the architecture defined
0( the %ntel processor famil( 0ased on the %ntel Architecture instruction set and having an industr(&
standard 'C architecture.
I-. APIC
An %nputF2utput Advanced 'rogramma0le %nterrupt Controller routes interrupts from devices to the
processorMs local A'%C.
I-. APIC
An %nputF2utput !treamlined Advanced 'rogramma0le %nterrupt Controller routes interrupts from
devices to the processorMs local A'%C.
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Legac&
A computer state where power management polic( decisions are made 0( the platform
hardwareFfirmware shipped with the s(stem. The legac( power management features found in toda(Ms
s(stems are used to support power management in a s(stem that uses a legac( 2! that does not support
the 2!&directed power management architecture.
Legac& Hardware
A computer s(stem that has no AC'% or 2!'M power management support.
Legac& .
An 2! that is not aware of and does not direct the power management functions of the s(stem.
%ncluded in this categor( are operating s(stems with A'M 4.x support.
Local APIC
A local Advanced 'rogramma0le %nterrupt Controller receives interrupts from the %F2 A'%C.
Local APIC
A local !treamlined Advanced 'rogramma0le %nterrupt Controller receives interrupts from the %F2
!A'%C.
Multiple APIC "escription 'able (MA"')
The Multiple A'%C -escription Ta0le =MA-T> is used on s(stems supporting the A'%C and !A'%C to
descri0e the A'%C implementation. 5ollowing the MA-T is a list of A'%CF!A'%C structures that
declare the A'%CF!A'%C features of the machine.
.b/ect
The nodes of the AC'% Namespace are o0#ects inserted in the tree 0( the 2! using the information in
the s(stem definition ta0les. These o0#ects can 0e data o0#ects, package o0#ects, control method
o0#ects, and so on. 'ackage o0#ects refer to other o0#ects. 20#ects also have t(pe, siHe, and relative
name.
.b/ect name
'art of the AC'% Namespace. There is a set of rules for naming o0#ects.
.perating &stem,directed Power Management (.PM)
A model of power =and s(stem> management in which the 2! pla(s a central role and uses glo0al
information to optimiHe s(stem 0ehavior for the task at hand.
Pac$age
An arra( of o0#ects.
Power #utton
A user push 0utton or other switch contact device that switches the s(stem from the sleepingFsoft off
state to the working state, and signals the 2! to transition to a sleepingFsoft off state from the working
state.
Power Management
Mechanisms in software and hardware to minimiHe s(stem power consumption, manage s(stem
thermal limits, and ma/imiHe s(stem 0atter( life. 'ower management involves trade&offs among
s(stem speed, noise, 0atter( life, processing speed, and alternating current =AC> power consumption.
'ower management is re:uired for some s(stem functions, such as appliance =for e/ample, answering
machine, furnace control> operations.
Power *esources
3esources =for e/ample, power planes and clock sources> that a device re:uires to operate in a given
power state.
Power ources
The 0atter( =including a ,'! 0atter(> and AC line powered adapters or power supplies that suppl(
power to a platform.
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*egister +rouping
Consists of two register 0locks =it has two pointers to two different 0locks of registers>. The fi/ed&
position 0its within a register grouping can 0e split 0etween the two register 0locks. This allows the
0its within a register grouping to 0e split 0etween two chips.
*eserved #its
!ome unused 0its in AC'% hardware registers are designated as J3eservedL in the AC'% specification.
5or future e/tensi0ilit(, hardware&register reserved 0its alwa(s return Hero, and data writes to them
have no side effects. 2!'M implementations must write Heros to all reserved 0its in ena0le and status
registers and preserve 0its in control registers.
*oot &stem "escription Pointer (*"P)
An AC'%&compati0le s(stem must provide an 3!-' in the s(stemMs low address space. This structureMs
onl( purpose is to provide the ph(sical address of the 3!-T and A!-T.
*oot &stem "escription 'able (*"')
A ta0le with the signature O3!-T,M followed 0( an arra( of ph(sical pointers to other s(stem
description ta0les. The 2! locates that 3!-T 0( following the pointer in the 3!-' structure.
econdar& &stem "escription 'able ("')
!!-Ts are a continuation of the -!-T. Multiple !!-Ts can 0e used as part of a platform description.
After the -!-T is loaded into the AC'% Namespace, each secondar( description ta0le listed in the
3!-TFA!-T with a uni:ue 2.M Ta0le %- is loaded. This allows the 2.M to provide the 0ase support
in one ta0le, while adding smaller s(stem options in other ta0les.
0oteH Additional ta0les can onl( add dataK the( cannot overwrite data from previous ta0les.
leep #utton
A user push 0utton that switches the s(stem from the sleepingFsoft off state to the working state, and
signals the 2! to transition to a sleeping state from the working state.
mart #atter& ubs&stem
A 0atter( su0s(stem that conforms to the following specifications< !mart ;atter( and either !mart
;atter( !(stem Manager or !mart ;atter( Charger and !electorPand the additional AC'%
re:uirements.
mart #atter& 'able
An AC'% ta0le used on platforms that have a !mart ;atter( su0s(stem. This ta0le indicates the energ(&
level trip points that the platform re:uires for placing the s(stem into different sleeping states and
suggested energ( levels for warning the user to transition the platform into a sleeping state.
&stem Management #us (M#us)
A two&wire interface 0ased upon the %QC protocol. The !M;us is a low&speed 0us that provides
positive addressing for devices, as well as 0us ar0itration.
M#us Interface
A standard hardware and software communications interface 0etween an 2! 0us driver and an !M;us
controller.
treamlined Advanced Programmable Interrupt Controller (APIC)
An advanced A'%C commonl( found on %ntel %tanium 'rocessor 5amil(&0ased +"&0it s(stems.
&stem Conte%t
The volatile data in the s(stem that is not saved 0( a device driver.
&stem Control Interrupt (CI)
A s(stem interrupt used 0( hardware to notif( the 2! of AC'% events. The !C% is an active, low,
sharea0le, level interrupt.
&stem Management Interrupt (MI)
An 2!&transparent interrupt generated 0( interrupt events on legac( s(stems. ;( contrast, on AC'%
s(stems, interrupt events generate an 2!&visi0le interrupt that is sharea0le =edge&st(le interrupts will
not work>. @ardware platforms that want to support 0oth legac( operating s(stems and AC'% s(stems
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2 Advanced Configuration and 'ower %nterface !pecification
must support a wa( of re&mapping the interrupt events 0etween !M%s and !C%s when switching
0etween AC'% and legac( models.
'hermal tates
Thermal states represent different operating environment temperatures within thermal Hones of a
s(stem. A s(stem can have one or more thermal HonesK each thermal Hone is the volume of space
around a particular temperature&sensing device. The transitions from one thermal state to another are
marked 0( trip points, which are implemented to generate an !C% when the temperature in a thermal
Hone moves a0ove or 0elow the trip point temperature.
(%tended *oot &stem "escription 'able (0"')
The A!-T provides identical functionalit( to the 3!-T 0ut accommodates ph(sical addresses of
-.!C3%'T%2N @.A-.3s that are larger than 32&0its. Notice that 0oth the A!-T and the 3!-T can
0e pointed to 0( the 3!-' structure.
3.2 Global System State Defnitions
$lo0al s(stem states =$x states> appl( to the entire s(stem and are visi0le to the user.
$lo0al s(stem states are defined 0( si/ principal criteria<
4. -oes application software runR
2. What is the latenc( from e/ternal events to application responseR
3. What is the power consumptionR
". %s an 2! re0oot re:uired to return to a working stateR
*. %s it safe to disassem0le the computerR
+. Can the state 0e entered and e/ited electronicall(R
5ollowing is a list of the s(stem states<
+1 Mechanical .ff
A computer state that is entered and left 0( a mechanical means =for e/ample, turning off the s(stemMs
power through the movement of a large red switch>. Darious government agencies and countries
re:uire this operating mode. %t is implied 0( the entr( of this off state through a mechanical means that
no electrical current is running through the circuitr( and that it can 0e worked on without damaging the
hardware or endangering service personnel. The 2! must 0e restarted to return to the Working state.
No hardware conte/t is retained. ./cept for the real&time clock, power consumption is Hero.
+2-3 oft .ff
A computer state where the computer consumes a minimal amount of power. No user mode or s(stem
mode code is run. This state re:uires a large latenc( in order to return to the Working state. The
s(stemMs conte/t will not 0e preserved 0( the hardware. The s(stem must 0e restarted to return to the
Working state. %t is not safe to disassem0le the machine in this state.
+4 leeping
A computer state where the computer consumes a small amount of power, user mode threads are not
0eing e/ecuted, and the s(stem JappearsL to 0e off =from an end userMs perspective, the displa( is off,
and so on>. 1atenc( for returning to the Working state varies on the wake environment selected prior to
entr( of this state =for e/ample, whether the s(stem should answer phone calls>. Work can 0e resumed
without re0ooting the 2! 0ecause large elements of s(stem conte/t are saved 0( the hardware and the
rest 0( s(stem software. %t is not safe to disassem0le the machine in this state.
+5 6or$ing
A computer state where the s(stem dispatches user mode =application> threads and the( e/ecute. %n this
state, peripheral devices =peripherals> are having their power state changed d(namicall(. The user can
select, through some ,%, various performanceFpower characteristics of the s(stem to have the software
optimiHe for performance or 0atter( life. The s(stem responds to e/ternal events in real time. %t is not
safe to disassem0le the machine in this state.
7 Non,8olatile leep
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A special glo0al s(stem state that allows s(stem conte/t to 0e saved and restored =relativel( slowl(>
when power is lost to the mother0oard. %f the s(stem has 0een commanded to enter !", the 2! will
write all s(stem conte/t to a file on non&volatile storage media and leave appropriate conte/t markers.
The machine will then enter the !" state. When the s(stem leaves the !oft 2ff or Mechanical 2ff state,
transitioning to Working =$> and restarting the 2!, a restore from a ND! file can occur. This will
onl( happen if a valid non&volatile sleep data set is found, certain aspects of the configuration of the
machine have not changed, and the user has not manuall( a0orted the restore. %f all these conditions are
met, as part of the 2! restarting, it will reload the s(stem conte/t and activate it. The net effect for the
user is what looks like a resume from a !leeping =$4> state =al0eit slower>. The aspects of the machine
configuration that must not change include, 0ut are not limited to, disk la(out and memor( siHe. %t
might 0e possi0le for the user to swap a 'C Card or a -evice ;a( device, however.
Notice that for the machine to transition directl( from the !oft 2ff or !leeping states to !", the s(stem
conte/t must 0e written to non&volatile storage 0( the hardwareK entering the Working state first so that
the 2! or ;%2! can save the s(stem conte/t takes too long from the userMs point of view. The
transition from Mechanical 2ff to !" is likel( to 0e done when the user is not there to see it.
;ecause the !" state relies onl( on non&volatile storage, a machine can save its s(stem conte/t for an
ar0itrar( period of time =on the order of man( (ears>.
Ta!le &-+ Su%%ar) of ;lo!al Power States
;lo!al
s)ste% state
Software
runs Latenc)
Power
consu%ption
3S restart
reJuired
Safe to
disasse%!le
co%puter
1xit state
electronicall)
$ Working Ses 1arge No No Ses
$4 !leeping No ), varies with
sleep state
!maller No No Ses
$2F!* !oft
2ff
No 1ong Der( near Ses No Ses
$3
Mechanical
2ff
No 1ong 3TC 0atter( Ses Ses No
Notice that the entries for $2F!* and $3 in the 1atenc( column of the a0ove ta0le are J1ong.L This implies
that a platform designed to give the user the appearance of Jinstant&on,L similar to a home appliance device,
will use the $ and $4 states almost e/clusivel( =the $3 state ma( 0e used for moving the machine or
repairing it>.
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22 Advanced Configuration and 'ower %nterface !pecification
3.3 Device Power State Defnitions
-evice power states are states of particular devicesK as such, the( are generall( not visi0le to the user. 5or
e/ample, some devices ma( 0e in the 2ff state even though the s(stem as a whole is in the Working state.
-evice states appl( to an( device on an( 0us. The( are generall( defined in terms of four principal criteria<
Power consu%ption @ow much power the device uses.
5evice context @ow much of the conte/t of the device is retained 0( the hardware. The 2! is
responsi0le for restoring an( lost device conte/t =this ma( 0e done 0( resetting the device>.
5evice driver What the device driver must do to restore the device to full on.
"estore ti%e @ow long it takes to restore the device to full on.
The device power states are defined 0elow, although ver( genericall(. Man( devices do not have all four
power states defined. -evices ma( 0e capa0le of several different low&power modes, 0ut if there is no user&
percepti0le difference 0etween the modes, onl( the lowest power mode will 0e used. The -evice Class
'ower Management !pecifications, included in Appendi/ A of this specification, descri0e which of these
power states are defined for a given t(pe =class> of device and define the specific details of each power state
for that device class. 5or a list of the availa0le De2ice Class Power (anagement Specifications, see
JAppendi/ A< -evice Class !pecifications.L
"1 .ff
'ower has 0een full( removed from the device. The device conte/t is lost when this state is entered, so
the 2! software will reinitialiHe the device when powering it 0ack on. !ince device conte/t and power
are lost, devices in this state do not decode their address lines. -evices in this state have the longest
restore times. All classes of devices define this state.
"2
The meaning of the -2 -evice !tate is defined 0( each device class. Man( device classes ma( not
define -2. %n general, -2 is e/pected to save more power and preserve less device conte/t than -4 or
-. ;uses in -2 ma( cause the device to lose some conte/t =for e/ample, 0( reducing power on the
0us, thus forcing the device to turn off some of its functions>.
"4
The meaning of the -4 -evice !tate is defined 0( each device class. Man( device classes ma( not
define -4. %n general, -4 is e/pected to save less power and preserve more device conte/t than -2.
"5 )ull&,.n
This state is assumed to 0e the highest level of power consumption. The device is completel( active
and responsive, and is e/pected to remem0er all relevant conte/t continuousl(.
Ta!le &-& Su%%ar) of 5evice Power States
5evice State Power Consu%ption 5evice Context "etained 5river "estoration
- & 5ull(&2n As needed for
operation
All None
-4 -)-4)-2)-3 )-2 T-2
-2 -)-4)-2)-3 T-4 )-4
-3 & 2ff None 5ull initialiHation and load
0oteH -evices often have different power modes within a given state. -evices can use these modes as long
as the( can automaticall( transparentl( switch 0etween these modes from the software, without violating
the rules for the current -x state the device is in. 1ow&power modes that adversel( affect performance =in
other words, low speed modes> or that are not transparent to software cannot 0e done automaticall( in
hardwareK the device driver must issue commands to use these modes.
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3.4 Sleeping State Defnitions
!leeping states =!x states> are t(pes of sleeping states within the glo0al sleeping state, $4. The !x states are
0riefl( defined 0elow. 5or a detailed definition of the s(stem 0ehavior within each !x state, see section
9.3.", J!(stem BC!x !tates.L 5or a detailed definition of the transitions 0etween each of the !x states, see
section 4*.4, J!leeping !tates.L
4 leeping tate
The !4 sleeping state is a low wake latenc( sleeping state. %n this state, no s(stem conte/t is lost =C',
or chip set> and hardware maintains all s(stem conte/t.
2 leeping tate
The !2 sleeping state is a low wake latenc( sleeping state. This state is similar to the !4 sleeping state
e/cept that the C', and s(stem cache conte/t is lost =the 2! is responsi0le for maintaining the caches
and C', conte/t>. Control starts from the processorMs reset vector after the wake event.
1 leeping tate
The !3 sleeping state is a low wake latenc( sleeping state where all s(stem conte/t is lost e/cept
s(stem memor(. C',, cache, and chip set conte/t are lost in this state. @ardware maintains memor(
conte/t and restores some C', and 12 configuration conte/t. Control starts from the processorMs reset
vector after the wake event.
7 leeping tate
The !" sleeping state is the lowest power, longest wake latenc( sleeping state supported 0( AC'%. %n
order to reduce power to a minimum, it is assumed that the hardware platform has powered off all
devices. 'latform conte/t is maintained.
3 oft .ff tate
The !* state is similar to the !" state e/cept that the 2! does not save an( conte/t. The s(stem is in the
JsoftL off state and re:uires a complete 0oot when it wakes. !oftware uses a different state value to
distinguish 0etween the !* state and the !" state to allow for initial 0oot operations within the ;%2! to
distinguish whether or not the 0oot is going to wake from a saved memor( image.
3.5 Processor Power State Defnitions
'rocessor power states =Cx states> are processor power consumption and thermal management states within
the glo0al working state, $. The Cx states possess specific entr( and e/it semantics and are 0riefl( defined
0elow. 5or a more detailed definition of each Cx state, see section 8.4, J'rocessor 'ower !tates.L
C5 Processor Power tate
While the processor is in this state, it e/ecutes instructions.
C4 Processor Power tate
This processor power state has the lowest latenc(. The hardware latenc( in this state must 0e low
enough that the operating software does not consider the latenc( aspect of the state when deciding
whether to use it. Aside from putting the processor in a non&e/ecuting power state, this state has no
other software&visi0le effects.
C2 Processor Power tate
The C2 state offers improved power savings over the C4 state. The worst&case hardware latenc( for
this state is provided via the AC'% s(stem firmware and the operating software can use this information
to determine when the C4 state should 0e used instead of the C2 state. Aside from putting the processor
in a non&e/ecuting power state, this state has no other software&visi0le effects.
C1 Processor Power tate
The C3 state offers improved power savings over the C4 and C2 states. The worst&case hardware
latenc( for this state is provided via the AC'% s(stem firmware and the operating software can use this
information to determine when the C2 state should 0e used instead of the C3 state. While in the C3
state, the processorMs caches maintain state 0ut ignore an( snoops. The operating software is
responsi0le for ensuring that the caches maintain coherenc(.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
2" Advanced Configuration and 'ower %nterface !pecification
3.6 Device and Processor Performance State Defnitions
-evice and 'rocessor performance states ='x states> are power consumption and capa0ilit( states within the
activeFe/ecuting states, C for processors and - for devices. The '/ states are 0riefl( defined 0elow. 5or a
more detailed definition of each '/ state from a processor perspective, see section 8.".", J'rocessor
'erformance Control.L 5or a more detailed definition of each '/ state from a device perspective see section
3.+, J-evice and 'rocessor 'erformance !tates,L and the device class specifications in Appendi/ A.
P5 Performance tate
While a device or processor is in this state, it uses its ma/imum performance capa0ilit( and ma(
consume ma/imum power.
P4 Performance tate
%n this performance power state, the performance capa0ilit( of a device or processor is limited 0elow
its ma/imum and consumes less than ma/imum power.
Pn Performance tate
%n this performance state, the performance capa0ilit( of a device or processor is at its minimum level
and consumes minimal power while remaining in an active state. !tate n is a ma/imum num0er and is
processor or device dependent. 'rocessors and devices ma( define support for an ar0itrar( num0er of
performance states not to e/ceed 4+.
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2+ Advanced Configuration and 'ower %nterface !pecification
4 ACPI Overview
'latforms compliant with the AC'% specification provide 2!'M with direct and exclusive control over the
power management and mother0oard device configuration functions of a computer. -uring 2!
initialiHation, 2!'M takes over these functions from legac( implementations such as the A'M ;%2!,
!MM&0ased firmware, legac( applications, and the 'N';%2!. @aving done this, 2!'M is responsi0le for
handling mother0oard device configuration events as well as for controlling the power, performance, and
thermal status of the s(stem 0ased on user preference, application re:uests and 2! imposed Gualit( of
!ervice =G2!> F usa0ilit( goals. AC'% provides low&level interfaces that allow 2!'M to perform these
functions. The functional areas covered 0( the AC'% specification are<
S)ste% power %anage%ent AC'% defines mechanisms for putting the computer as a whole in
and out of s(stem sleeping states. %t also provides a general mechanism for an( device to wake the
computer.
5evice power %anage%ent AC'% ta0les descri0e mother0oard devices, their power states, the
power planes the devices are connected to, and controls for putting devices into different power states.
This ena0les the 2! to put devices into low&power states 0ased on application usage.
Processor power %anage%ent While the 2! is idle 0ut not sleeping, it will use commands
descri0ed 0( AC'% to put processors in low&power states.
5evice and processor perfor%ance %anage%ent While the s(stem is active, 2!'M will
transition devices and processors into different performance states, defined 0( AC'%, to achieve a
desira0le 0alance 0etween performance and energ( conservation goals as well as other environmental
re:uirements =for e/ample, visi0ilit( and acoustics>.
Configuration @ Plug and Pla) AC'% specifies information used to enumerate and configure
mother0oard devices. This information is arranged hierarchicall( so when events such as docking and
undocking take place, the 2! has precise, a priori knowledge of which devices are affected 0( the
event.
S)ste% 1vents AC'% provides a general event mechanism that can 0e used for s(stem events
such as thermal events, power management events, docking, device insertion and removal, and so on.
This mechanism is ver( fle/i0le in that it does not define specificall( how events are routed to the core
logic chip set.
<atter) %anage%ent ;atter( management polic( moves from the A'M ;%2! to the AC'% 2!.
An AC'%&compati0le 0atter( device needs either a !mart ;atter( su0s(stem interface, which is
controlled 0( the 2! directl( through the em0edded controller interface, or a Control Method ;atter(
interface. A Control Method ;atter( interface is completel( defined 0( AM1 control methods,
allowing an 2.M to choose an( t(pe of the 0atter( and an( kind of communication interface supported
0( AC'%. The 0atter( must compl( with the re:uirements of its interface, as descri0ed either herein or
in other applica0le standards. The 2! ma( choose to alter the 0ehavior of the 0atter(, for e/ample, 0(
ad#usting the 1ow ;atter( or ;atter( Warning trip point. When there are multiple 0atteries present, the
0atter( su0s(stem is not re:uired to perform an( s(nthesis of a Jcomposite 0atter(L from the data of
the separate 0atteries. %n cases where the 0atter( su0s(stem does not s(nthesiHe a Jcomposite 0atter(L
from the separate 0atter(Ms data, the 2! must provide that s(nthesis.
Ther%al %anage%ent !ince the 2! controls the power and performance states of devices and
processors, AC'% also addresses s(stem thermal management. %t provides a simple, scalea0le model
that allows 2.Ms to define thermal Hones, thermal indicators, and methods for cooling thermal Hones.
1%!edded Controller AC'% defines a standard hardware and software communications interface
0etween an 2! 0us enumerator and an em0edded controller. This allows an( 2! to provide a standard
0us enumerator that can directl( communicate with an em0edded controller in the s(stem, thus
allowing other drivers within the s(stem to communicate with and use the resources of s(stem
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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em0edded controllers. This in turn ena0les the 2.M to provide platform features that the 2! and
applications can use.
SM<us Controller AC'% defines a standard hardware and software communications interface
0etween an 2! 0us driver and an !M;us Controller. This allows an( 2! to provide a standard 0us
driver that can directl( communicate with !M;us devices in the s(stem. This in turn ena0les the 2.M
to provide platform features that the 2! and applications can use.
2!'MMs mission is to optimall( configure the platform and to optimall( manage the s(stemMs power,
performance, and thermal status given the userMs preferences and while supporting 2! imposed Gualit( of
!ervice =G2!> F usa0ilit( goals. To achieve these goals, AC'% re:uires that once an AC'% compliant
platform is in AC'% mode, the platformMs hardware, firmware, or other non&2! software %ust not
manipulate the platformMs configuration, power, performance, and thermal control interfaces independentl(
of 2!'M. 2!'M alone is responsi0le for coordinating the configuration, power management, performance
management, and thermal control polic( of the s(stem. Manipulation of these interfaces independentl( of
2!'M undermines the purpose of 2!'MFAC'% and ma( adversel( impact the s(stemMs configuration,
power, performance, and thermal polic( goals. There are two e/ceptions to this re:uirement. The first is in
the case of the possi0ilit( of damage to a s(stem from an e/cessive thermal conditions where an AC'%
compati0le 2! is present and 2!'M latenc( is insufficient to remed( an adverse thermal condition. %n this
case, the platform ma( e/ercise a failsafe thermal control mechanism that reduces the performance of a
s(stem component to avoid damage. %f this occurs, the platform must notif( 2!'M of the performance
reduction if the reduction is of significant duration =in other words, if the duration of reduced performance
could adversel( impact 2!'MMs power or performance control polic( & operating s(stem vendors can
provide guidance in this area>. The second e/ception is the case where the platform contains Active cooling
devices 0ut does not contain 'assive cooling temperature trip points or controls,. %n this case, a hardware
0ased Active cooling mechanism ma( 0e implemented without impacting 2!'MMs goals. An( platform that
re:uires !oth active and passive cooling must allow 2!'M to manage the platform thermals via AC'%
defined active and passive cooling interfaces.
4.1 System Power Management
,nder 2!'M, the 2! directs all s(stem and device power state transitions. .mplo(ing user preferences and
knowledge of how devices are 0eing used 0( applications, the 2! puts devices in and out of low&power
states. -evices that are not 0eing used can 0e turned off. !imilarl(, the 2! uses information from
applications and user settings to put the s(stem as a whole into a low& power state. The 2! uses AC'% to
control power state transitions in hardware.
4.2 Power States
5rom a user&visi0le level, the s(stem can 0e thought of as 0eing in one of the states in the following
diagram<
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
28 Advanced Configuration and 'ower %nterface !pecification
,- -*ech
Off
+egacy
.a/e
&vent
,0 1S02 -
.or/ing
,3 -
Sleeping
S4
S-
S5
S3
Po#er
6ail(re$
Po#er Off
,5 1S72 -
Soft Off
BIOS
Routine
C0
D0
D3
D5
D-
*o"e%
D0
D3
D5
D-
!DD
D0
D3
D5
D-
CDRO*
C5
C3
Cn
Performance
State Px
Throttling
C0
CP8
6igure #-+ ;lo!al S)ste% Power States and Transitions
!ee section 2.2, J$lo0al !(stem !tate -efinitions,L for detailed definitions of these states.
%n general use, computers alternate 0etween the Working and !leeping states. %n the Working state, the
computer is used to do work. ,ser&mode application threads are dispatched and running. %ndividual devices
can 0e in low&power =-x> states and processors can 0e in low&power =Cx> states if the( are not 0eing used.
An( device the s(stem turns off 0ecause it is not activel( in use can 0e turned on with short latenc(. =What
JshortL means depends on the device. An 1C- displa( needs to come on in su0&second times, while it is
generall( accepta0le to wait a few seconds for a printer to wake.>
The net effect of this is that the entire machine is functional in the Working state. Darious Working su0&
states differ in speed of computation, power used, heat produced, and noise produced. Tuning within the
Working state is largel( a0out trade&offs among speed, power, heat, and noise.
When the computer is idle or the user has pressed the power 0utton, the 2! will put the computer into one
of the sleeping =!x> states. No user&visi0le computation occurs in a sleeping state. The sleeping su0&states
differ in what events can arouse the s(stem to a Working state, and how long this takes. When the machine
must awaken to all possi0le events or do so ver( :uickl(, it can enter onl( the su0&states that achieve a
partial reduction of s(stem power consumption. @owever, if the onl( event of interest is a user pushing on a
switch and a latenc( of minutes is allowed, the 2! could save all s(stem conte/t into an ND! file and
transition the hardware into the !" sleeping state. %n this state, the machine draws almost Hero power and
retains s(stem conte/t for an ar0itrar( period of time =(ears or decades if needed>.
The other states are used less often. Computers that support legac( ;%2! power management interfaces
0oot in the 1egac( state and transition to the Working state when an AC'% 2! loads. A s(stem without
legac( support =for e/ample, a 3%!C s(stem> transitions directl( from the Mechanical 2ff state to the
Working state. ,sers t(picall( put computers into the Mechanical 2ff state 0( flipping the computerMs
mechanical switch or 0( unplugging the computer.
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4.2.1 Power Button
%n legac( s(stems, the power 0utton t(picall( either forces the machine into !oft 2ff or Mechanical 2ff or,
on a laptop, forces it to some sleeping state. No allowance is made for user polic( =such as the user wants
the machine to Jcome onL in less than 4 second with all conte/t as it was when the user turned the machine
JoffL>, s(stem alert functions =such as the s(stem 0eing used as an answering machine or fa/ machine>, or
application function =such as saving a user file>.
%n an 2!'M s(stem, there are two switches. 2ne is to transition the s(stem to the Mechanical 2ff state. A
mechanism to stop current flow is re:uired for legal reasons in some #urisdictions =for e/ample, in some
.uropean countries>. The other is the JmainL power 0utton. This is in some o0vious place =for e/ample,
0eside the ke(0oard on a laptop>. ,nlike legac( onFoff 0uttons, all it does is send a re:uest to the s(stem.
What the s(stem does with this re:uest depends on polic( issues derived from user preferences, user
function re:uests, and application data.
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3 Advanced Configuration and 'ower %nterface !pecification
4.2.2 Platform Power Management Characteristics
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4.2.2.1
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32 Advanced Configuration and 'ower %nterface !pecification
Mobile PC
Mo0ile 'Cs will continue to have aggressive power management functionalit(. $oing to 2!'MFAC'% will
allow enhanced power savings techni:ues and more refined user policies.
Aspects of mo0ile 'C power management in the AC'% specification are thermal management =see section
44, JThermal ManagementL> and the em0edded controller interface =see section 42, JAC'% .m0edded
Controller %nterface !pecificationL>.
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4.2.2.2
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3" Advanced Configuration and 'ower %nterface !pecification
4.2.2.2
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%nde/ 3*
Desktop PCs
'ower&managed desktops will 0e of two t(pes, though the first t(pe will migrate to the second over time.
3rdinar) 8;reen PC.L @ere, new appliance functions are not the issue. The machine is reall(
onl( used for productivit( computations. At least initiall(, such machines can get 0( with ver( minimal
function. %n particular, the( need the normal AC'% timers and controls, 0ut donMt need to support
ela0orate sleeping states, and so on. The(, however, do need to allow the 2! to put as man( of their
devicesFresources as possi0le into device stand0( and device off states, as independentl( as possi0le =to
allow for ma/imum compute speed with minimum power wasted on unused devices>. !uch 'Cs will
also need to support wake from the sleeping state 0( means of a timer, 0ecause this allows
administrators to force them to turn on #ust 0efore people are to show up for work.
Ho%e PC. Computers are moving into home environments where the( are used in entertainment
centers and to perform tasks like answering the phone. A home 'C needs all of the functionalit( of the
ordinar( green 'C. %n fact, it has all of the AC'% power functionalit( of a laptop e/cept for docking
and lid events =and need not have an( legac( power management>. Note that there is also a thermal
management aspect to a home 'C, as a home 'C user wants the s(stem to run as :uietl( as possi0le,
often in a thermall( constrained environment.
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3+ Advanced Configuration and 'ower %nterface !pecification
4.2.2.3
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Multiprocessor and Server PCs
'erhaps surprisingl(, server machines often get the largest a0solute power savings. Wh(R ;ecause the(
have the largest hardware configurations and 0ecause itMs not practical for some0od( to hit the off switch
when the( leave at night.
5a) Mode. %n da( mode, servers are power&managed much like a corporate ordinar( green 'C,
sta(ing in the Working state all the time, 0ut putting unused devices into low&power states whenever
possi0le. ;ecause servers can 0e ver( large and have, for e/ample, man( disk spindles, power
management can result in large savings. 2!'M allows careful tuning of when to do this, thus making it
worka0le.
0ight Mode. %n night mode, servers look like home 'Cs. The( sleep as deepl( as the( can and are
still a0le to wake and answer service re:uests coming in over the network, phone links, and so on,
within specified latencies. !o, for e/ample, a print server might go into deep sleep until it receives a
print #o0 at 3 A.M., at which point it wakes in perhaps less than 3 seconds, prints the #o0, and then
goes 0ack to sleep. %f the print re:uest comes over the 1AN, then this scenario depends on an
intelligent 1AN adapter that can wake the s(stem in response to an interesting received packet.
4.3 Device Power Management
This section descri0es AC'%&compati0le device power management. The AC'% device power states are
introduced, the controls and information an AC'%&compati0le 2! needs to perform device power
management are discussed, the wake operation devices use to wake the computer from a sleeping state is
descri0ed, and an e/ample of AC'%&compati0le device management using a modem is given.
4.3.1 Power Management Standards
To manage power of all the devices in the s(stem, the 2! needs standard methods for sending commands to
a device. These standards define the operations used to manage power of devices on a particular %F2
interconnect and the power states that devices can 0e put into. -efining these standards for each %F2
interconnect creates a 0aseline level of power management support the 2! can utiliHe. %ndependent
@ardware Dendors =%@Ds> do not have to spend e/tra time writing software to manage power of their
hardware, 0ecause simpl( adhering to the standard gains them direct 2! support. 5or 2! vendors, the %F2
interconnect standards allow the power management code to 0e centraliHed in the driver for each %F2
interconnect. 5inall(, %F2 interconnect&driven power management allows the 2! to track the states of all
devices on a given %F2 interconnect. When all the devices are in a given state =or e/ample, -3 & off>, the 2!
can put the entire %F2 interconnect into the power suppl( mode appropriate for that state =for e/ample, -3 &
off>.
%F2 interconnect&level power management specifications are written for a num0er of 0uses including<
'C%
'C% ./press
Card;us
,!;
%... 436"
4.3.2 Device Power States
To unif( nomenclature and provide consistent 0ehavior across devices, standard definitions are used for the
power states of devices. $enerall(, these states are defined in terms of the following criteria<
Power consu%ption. @ow much power the device uses.
5evice context @ow much of the conte/t of the device is retained 0( the hardware.
5evice driver. What the device driver must do to restore the device to full( on.
"estore latenc). @ow long it takes to restore the device to full( on.
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38 Advanced Configuration and 'ower %nterface !pecification
More specificall(, power management specifications for each class of device =for e/ample, modem,
network adapter, hard disk, and so on> more precisel( define the power states and power polic( for the
class. !ee section 2.3, J-evice 'ower !tate -efinitions,L for the detailed description of the four general
device power states =-&-3>.
4.3.3 Device Power State Defnitions
The device power state definitions are device&independent, 0ut classes of devices on a 0us must support
some consistent set of power&related characteristics. 5or e/ample, when the 0us&specific mechanism to set
the device power state to a given level is invoked, the actions a device might take and the specific sorts of
0ehaviors the 2! can assume while the device is in that state will var( from device t(pe to device t(pe. 5or
a full( integrated device power management s(stem, these class&specific power characteristics must also 0e
standardiHed<
5evice Power State Characteristics .ach class of device has a standard definition of target
power consumption levels, state&change latencies, and conte/t loss.
Mini%u% 5evice Power Capa!ilities .ach class of device has a minimum standard set of power
capa0ilities.
5evice 6unctional Characteristics .ach class of device has a standard definition of what su0set
of device functionalit( or features is availa0le in each power state =for e/ample, the net card can
receive, 0ut cannot transmitK the sound card is full( functional e/cept that the power amps are off, and
so on>.
5evice :akeup Characteristics .ach class of device has a standard definition of its wake
polic(.
The Microsoft -evice Class 'ower Management specifications define these power state characteristics for
each class of device.
4.4 Controlling Device Power
AC'% interfaces provides control and information needed to perform device power management. AC'%
interfaces descri0e to 2!'M the capa0ilities of all the devices it controls. %t also gives the 2! the control
methods used to set the power state or get the power status for each device. 5inall(, it has a general scheme
for devices to wake the machine.
0oteH 2ther 0uses enumerate some devices on the main 0oard. 5or e/ample, 'C% devices are reported
through the standard 'C% enumeration mechanisms. 'ower management of these devices is handled
through their own 0us specification =in this case, 'C%>. All other devices on the main 0oard are handled
through AC'% !pecificall(, the AC'% ta0le lists legac( devices that cannot 0e reported through their own
0us specification, the root of each 0us in the s(stem, and devices that have additional power management or
configuration options not covered 0( their own 0us specification.
5or more detailed information see section 9, J'ower and 'erformance Management.L
4.4.1 Getting Device Power Capabilities
As the 2! enumerates devices in the s(stem, it gets information a0out the power management features that
the device supports. The -ifferentiated -efinition ;lock given to the 2! 0( the ;%2! descri0es ever(
device handled 0( AC'%. This description contains the following information<
A description of what power resources =power planes and clock sources> the device needs in each
power state that the device supports. 5or e/ample, a device might need a high power 0us and a clock in
the - state 0ut onl( a low&power 0us and no clock in the -2 state.
A description of what power resources a device needs in order to wake the machine =or none to
indicate that the device does not support wake>. The 2! can use this information to infer what device
and s(stem power states from which the device can support wake.
The optional control method the 2! can use to set the power state of the device and to get and set
resources.
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%n addition to descri0ing the devices handled 0( AC'%, the ta0le lists the power planes and clock sources
themselves and the control methods for turning them on and off. 5or detailed information, see section 9,
J'ower and 'erformance Management.L
4.4.2 Setting Device Power States
2!'M uses the !et 'ower !tate operation to put a device into one of the four power states.
When a device is put in a lower power state, it configures itself to draw as little power from the 0us as
possi0le. The 2! tracks the state of all devices on the 0us, and will put the 0us in the 0est power state 0ased
on the current device re:uirements on that 0us. 5or e/ample, if all devices on a 0us are in the -3 state, the
2! will send a command to the 0us control chip set to remove power from the 0us =thus putting the 0us in
the -3 state>. %f a particular 0us supports a low&power suppl( state, the 2! puts the 0us in that state if all
devices are in the -4 or -2 state. Whatever power state a device is in, the 2! must 0e a0le to issue a !et
'ower !tate command to resume the device.
0oteH The device does not need to have power to do this. The 2! must turn on power to the device 0efore
it can send commands to the device.
2!'M also uses the !et 'ower !tate operation to ena0le power management features such as wake
=descri0ed in section 9, J'ower and 'erformance Management.L>.
When a device is to 0e set in a particular power state using the AC'% interface, the 2! first decides which
power resources will 0e used and which can 0e turned off. The 2! tracks all the devices on a given power
resource. When all the devices on a resource have 0een turned off, the 2! turns off that power resource 0(
running a control method. %f a power resource is turned off and one of the devices on that resource needs to
0e turned on, the 2! first turns on the power resource using a control method and then signals the device to
turn on. The time that the 2! must wait for the power resource to sta0iliHe after turning it on or off is
descri0ed in the description ta0le. The 2! uses the time 0ase provided 0( the 'ower Management Timer to
measure these time intervals.
2nce the power resources have 0een switched, the 2! e/ecutes the appropriate control method to put the
device in that power state. Notice that this might not mean that power is removed from the device. %f other
active devices are sharing a power resource, the power resources will remain on.
4.4.3 Getting Device Power Status
2!'M uses the $et 'ower !tatus operation to determine the current power configuration =states and
features>, as well as the status of an( 0atteries supported 0( the device. The device can signal an !C% to
inform the 2! of changes in power status. 5or e/ample, a device can trigger an interrupt to inform the 2!
that the 0atter( has reached low power level.
-evices use the AC'% event model to signal power status changes =for e/ample, 0atter( status changes> to
2!'M. The platform signals events to the 2! via the !C% interrupt. An !C% interrupt status 0it is set to
indicate the event to the 2!. The 2! runs the control method associated with the event. This control
method signals to the 2! which device has changed.
AC'% supports two t(pes of 0atteries< 0atteries that report onl( 0asic 0atter( status information and
0atteries that support the !mart ;atter( !(stem %mplementers 5orum !mart ;atter( !pecification. 5or
0atteries that report onl( 0asic 0atter( status information =such as total capacit( and remaining capacit(>,
the 2! uses control methods from the 0atter(Ms description ta0le to read this information. To read status
information for !mart ;atteries, the 2! can use a standard !mart ;atter( driver that directl( interfaces to
!mart ;atteries through the appropriate 0us enumerator.
4.4.4 Waking the Computer
The wake operation ena0les devices to wake the computer from a sleeping power state. This operation must
not depend on the C', 0ecause the C', will not 0e e/ecuting instructions.
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" Advanced Configuration and 'ower %nterface !pecification
The 2! ensures an( 0ridges 0etween the device and the core logic are in the lowest power state in which
the( can still forward the wake signal. When a device with wake ena0led decides to wake the machine, it
sends the defined signal on its 0us. ;us 0ridges must forward this signal to upstream 0ridges using the
appropriate signal for that 0us. Thus, the signal eventuall( reaches the core chip set =for e/ample, an AC'%
chip set>, which in turn wakes the machine.
;efore putting the machine in a sleeping power state, the 2! determines which devices are needed to wake
the machine 0ased on application re:uests, and then ena0les wake on those devices in a device and 0us
specific manner.
The 2! ena0les the wake feature on devices 0( setting that deviceMs !C% .na0le 0it. The location of this 0it
is listed in the deviceMs entr( in the description ta0le. 2nl( devices that have their wake feature ena0led can
wake the machine. The 2! keeps track of the power states that the wake devices support, and keeps the
machine in a power state in which the wake can still wake the machine
4
=0ased on capa0ilities reported in
the description ta0le>.
When the computer is in the !leeping state and a wake device decides to wake the machine, it signals to the
AC'% chip set. The !C% status 0it corresponding to the device waking the machine is set, and the AC'% chip
set resumes the machine. After the 2! is running again, it clears the 0it and handles the event that caused
the wake. The control method for this event then uses the Notif( command to tell the 2! which device
caused the wake.
Note< ;esides using AC'% mechanism to ena0le a particular device to wake the s(stem, an AC'% platform
must also 0e a0le to record and report the wake source to 2!'M. When a s(stem is woken from certain
states =such as the !" state>, it ma( start out in non&AC'% mode. %n this case, the !C% status 0it ma( 0e
cleared when AC'% mode is re&entered. @owever the platform must still attempt to record the wake source
for retrieval 0( 2!'M at a later point.
Note< Although the a0ove description e/plains how a device can wake the s(stem, note that a device can
also 0e put into a low power state during the ! s(stem state, and that this device ma( generate a wake
signal in the ! state as the following e/ample illustrates.
4
!ome 2! policies ma( re:uire the 2! to put the machine into a glo0al s(stem state for which the device
can no longer wake the s(stem. !uch as when a s(stem has ver( low 0atter( power.
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4.4.5 Example: Modem Device Power Management
To illustrate how these power management methods function in AC'%, consider an integrated modem. =This
e/ample is greatl( simplified for the purposes of this discussion.> The power states of a modem are defined
as follows =this is an e/cerpt from the Modem -evice Class 'ower Management !pecification><
5$ Modem controller on
'hone interface on
!peaker on
Can 0e on hook or off hook
Can 0e waiting for answer
5+ Modem controller in low&power mode =conte/t retained 0( device>
'hone interface powered 0( phone line or in low&power mode
!peaker off
Must 0e on hook
5& !ame as 5#
5# Modem controller off =conte/t lost>
'hone interface powered 0( phone line or off
!peaker off
2n hook
The power polic( for the modem is defined as follows<
5# 5$ C2M port opened
5$' 5+ 5# C2M port closed
5$ 5+ Modem put in answer mode
5+ 5$ Application re:uests dial or the phone rings while the modem is in answer mode
The wake polic( for the modem is ver( simple< When the phone rings and wake is ena0led, wake the
machine.
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"2 Advanced Configuration and 'ower %nterface !pecification
;ased on that polic(, the modem and the C2M port to which it is attached can 0e implemented in hardware
as shown in 5igure 3&2. This is #ust an e/ample for illustrating features of AC'%. This e/ample is not
intended to descri0e how 2.Ms should 0uild hardware.
S
w
itc
h
e
d
p
o
w
e
r
S
w
itc
h
e
d
p
o
w
e
r
ACPI core
chip set Phone
interface
Modem
controller
I/O
Control
Phone
line
PR! PR"
RI
A#$
PR!%$&
PR"%$&
M'M%'!
M'M%'(
I/O
COM port
)*ART+
I/O
COM%'(
6igure #-& 1xa%ple Mode% and C3M Port Hardware
0oteH Although not shown a0ove, each discrete part has some isolation logic so that the part is isolated
when power is removed from it. %solation logic controls are implemented as power resources in the AC'%
-ifferentiated -escription ;lock so that devices are isolated as power planes are se:uenced off.
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4.4.5.1
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"" Advanced Configuration and 'ower %nterface !pecification
Obtaining the Modem Capabilities
The 2! determines the capa0ilities of this modem when it enumerates the modem 0( reading the modemMs
entr( in the -ifferentiated -efinition ;lock. %n this case, the entr( for the modem would report<
The device supports 5$, 5+, and 5#<
5$ re:uires 'W34 and 'W32 as power resources
5+ re:uires 'W34 as a power resource
=5# implicitl( re:uires no power resources>
To wake the machine, the modem needs no power resources =impl(ing it can wake the machine from 5$,
5+, and 5#>
Control methods for setting power state and resources
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4.4.5.2
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"+ Advanced Configuration and 'ower %nterface !pecification
Setting the Modem Power State
While the 2! is running =$ state>, it switches the modem to different power states according to the power
polic( defined for modems.
When an application opens the C2M port, the 2! turns on the modem 0( putting it in the - state. Then if
the application puts the modem in answer mode, the 2! puts the modem in the -4 state to wait for the call.
To make this state transition, the AC'% first checks to see what power resources are no longer needed. %n
this case, 'W32 is not needed. Then it checks to make sure no other device in the s(stem re:uires the use
of the 'W32 power resource. %f the resource is no longer needed, the 2!'M uses the C255 control method
associated with that power resource in the -ifferentiated -efinition ;lock to turn off the 'W32 power
plane. This control method sends the appropriate commands to the core chip set to stop asserting the
'W32C.N line. Then, 2!'M runs a control method =C'!4> provided in the modemMs entr( to put the
device in the -4 state. This control method asserts the M-MC-4 signal that tells the modem controller to
go into a low&power mode.
2!'M does not alwa(s turn off power resources when a given device is put in a lower power state. 5or
e/ample, assume that the 'W34 power plane also powers an active line printer =1'T> port. !uppose the
user terminates the modem application, causing the C2M port to 0e closed, and therefore causing the
modem to 0e shut off =state -3>. As alwa(s, 2!'M checks to see which power resources are no longer
needed. ;ecause the 1'T port is still active, 'W34 is in use. 2!'M does not turn off the 'W34 resource.
%t continues the state transition process 0( running the modemMs control method to switch the device to the
-3 power state. The control method causes the M-MC-3 line to 0e asserted. The modem controller now
turns off all its ma#or functions so that it draws little power, if an(, from the 'W34 line. ;ecause the C2M
port is closed, the same se:uence of events will take place to put it in the -3 state. Notice that these
registers might not 0e in the device itself. 5or e/ample, the control method could read the register that
controls M-MC-3.
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4.4.5.3
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"8 Advanced Configuration and 'ower %nterface !pecification
Obtaining the Modem Power Status
%ntegrated modems have no 0atteriesK the onl( power status information for the device is the power state of
the modem. To determine the modemMs current power state =-&-3>, 2!'M runs a control method =C'!C>
supplied in the modemMs entr( in the -ifferentiated -efinition ;lock. This control method reads from the
necessar( registers to determine the modemMs power state.
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4.4.5.4
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* Advanced Configuration and 'ower %nterface !pecification
Waking the Computer
As indicated in the modem capa0ilities, this modem can wake the machine from an( device power state.
;efore putting the computer in a sleep state, the 2! ena0les wake on an( devices that applications have
re:uested to 0e a0le to wake the machine. Then, it chooses the lowest sleeping state that can still provide
the power resources necessar( to allow all ena0led wake devices to wake the machine. Ne/t, the 2! puts
each of those devices in the appropriate power state, and puts all other devices in the -3 state. %n this case,
the 2! puts the modem in the -3 state 0ecause it supports wake from that state. 5inall(, the 2! saves a
resume vector and puts the machine into a sleep state through an AC'% register.
Waking the computer via modem starts with the modemMs phone interface asserting its ring indicate =3%>
line when it detects a ring on the phone line. This line is routed to the core chip set to generate a wake
event. The chip set then wakes the s(stem and the hardware will eventuall( passes control 0ack to the 2!
=the wake mechanism differs depending on the sleeping state>. After the 2! is running, it puts the device in
the - state and 0egins handling interrupts from the modem to process the event.
4.5 Processor Power Management
To further save power in the Working state, the 2! puts the C', into low&power states =C4, C2, and C3>
when the 2! is idle. %n these low&power states, the C', does not run an( instructions, and wakes when an
interrupt, such as the 2! schedulerMs timer interrupt, occurs.
The 2! determines how much time is 0eing spent in its idle loop 0( reading the AC'% 'ower Management
Timer. This timer runs at a known, fi/ed fre:uenc( and allows the 2! to precisel( determine idle time.
-epending on this idle time estimate, the 2! will put the C', into different :ualit( low&power states
=which var( in power and latenc(> when it enters its idle loop.
The C', states are defined in detail in section 8, J'rocessor 'ower and 'erformance !tate Configuration
and Control.L
4.6 Device and Processor Performance States
This section descri0es the concept of device and processor performance states. -evice and processor
performance states ='/ states> are power consumption and capa0ilit( states within the activeFe/ecuting
states, C for processors and - for devices. 'erformance states allow 2!'M to make tradeoffs 0etween
performance and energ( conservation. -evice and processor performance states have the greatest impact
when the states invoke different device and processor efficienc( levels as opposed to a linear scaling of
performance and energ( consumption. !ince performance state transitions occur in the activeFe/ecuting
device states, care must 0e taken to ensure that performance state transitions do not adversel( impact the
s(stem.
./amples of device performance states include<
A hard drive that provides levels of ma/imum throughput that correspond to levels of power
consumption.
An 1C- panel that supports multiple 0rightness levels that correspond to levels of power
consumption.
A graphics component that scales performance 0etween 2- and 3- drawing modes that
corresponds to levels of power consumption.
An audio su0s(stem that provides multiple levels of ma/imum volume that correspond to levels of
ma/imum power consumption.
A -irect&3-3AM
TM
controller that provides multiple levels of memor( throughput performance,
corresponding to multiple levels of power consumption, 0( ad#usting the ma/imum 0andwidth
throttles.
'rocessor performance states are descri0ed in !ection 8, J'rocessor 'ower and 'erformance !tate
Configuration and Control.L
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4.7 Confguration and Plug and Play
%n addition to power management, AC'% interfaces provide controls and information that ena0le 2!'M to
configure the re:uired resources of mother0oard devices along with their d(namic insertion and removal.
AC'% -efinition ;locks, including the -ifferentiated !(stem -escription Ta0le =-!-T> and !econdar(
!(stem -escription Ta0les =!!-Ts>, descri0e mother0oard devices in a hierarchical format called the AC'%
namespace. The 2! enumerates mother0oard devices simpl( 0( reading through the AC'% Namespace
looking for devices with hardware %-s.
.ach device enumerated 0( AC'% includes AC'%&defined o0#ects in the AC'% Namespace that report the
hardware resources that the device could occup(, an o0#ect that reports the resources that are currentl(
used 0( the device, and o0#ects for configuring those resources. The information is used 0( the 'lug and
'la( 2! =2!'M> to configure the devices.
AC'% is used primaril( to enumerate and configure mother0oard devices that do not have other hardware
standards for enumeration and configuration. 5or e/ample, 'C% devices on the mother0oard need not 0e
enumerated 0( AC'%K 'lug and 'la( information for these devices need not 0e included in the A'C%
Namespace. @owever, power management information and insertionFremoval control for these devices can
still appear in the namespace if the devicesM power management andFor insertionFremoval is to 0e controlled
0( 2!'M via AC'%&defined interfaces.
0oteH When preparing to 0oot a computer, the ;%2! onl( needs to configure 0oot devices. This includes
0oot devices descri0ed in the AC'% s(stem description ta0les as well as devices that are controlled through
other standards.
4.7.1 Device Confguration Example: Confguring the Modem
3eturning to the modem device e/ample a0ove, the 2! will find the modem and load a driver for it when
the 2! finds it in the -!-T. This ta0le will have control methods that give the 2! the following
information<
The device can use %3G 3, %F2 358&355 or %3G ", %F2 2.8&2.5
The device is currentl( using %3G 3, %F2 358&355
The 2! configures the modemMs hardware resources using 'lug and 'la( algorithms. %t chooses one of the
supported configurations that does not conflict with an( other devices. Then, 2!'M configures the device
for those resources 0( running a control method supplied in the modemMs section of the -ifferentiated
-efinition ;lock. This control method will write to an( %F2 ports or memor( addresses necessar( to
configure the device to the given resources.
4.7.2 NUMA Nodes
!(stems emplo(ing a Non ,niform Memor( Access =N,MA> architecture contain collections of hardware
resources including processors, memor(, and %F2 0uses, that comprise what is commonl( known as a
JN,MA nodeL. 'rocessor accesses to memor( or %F2 resources within the local N,MA node is generall(
faster than processor accesses to memor( or %F2 resources outside of the local N,MA node. AC'% defines
interfaces that allow the platform to conve( N,MA node topolog( information to 2!'M 0oth staticall( at
0oot time and d(namicall( at run time as resources are added or removed from the s(stem.
4.8 System Events
AC'% includes a general event model used for 'lug and 'la(, Thermal, and 'ower Management events.
There are two registers that make up the event model< an event status register and an event ena0le register.
When an event occurs, the core logic sets a 0it in the status register to indicate the event. %f the
corresponding 0it in the ena0le register is set, the core logic will assert the !C% to signal the 2!. When the
2! receives this interrupt, it will run the control methods corresponding to an( 0its set in the event status
register. These control methods use AM1 commands to tell the 2! what event occurred.
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5or e/ample, assume a machine has all of its 'lug and 'la(, Thermal, and 'ower Management events
connected to the same pin in the core logic. The event status and event ena0le registers would onl( have
one 0it each< the 0it corresponding to the event pin.
When the computer is docked, the core logic sets the status 0it and signals the !C%. The 2!, seeing the
status 0it set, runs the control method for that 0it. The control method checks the hardware and determines
the event was a docking event =for e/ample>. %t then signals to the 2! that a docking event has occurred,
and can tell the 2! specificall( where in the device hierarch( the new devices will appear.
!ince the event model registers are generaliHed, the( can descri0e man( different platform
implementations. The single pin model a0ove is #ust one e/ample. Another design might have 'lug and
'la(, Thermal, and 'ower Management events wired to three different pins so there would 0e three status
0its =and three ena0le 0its>. Set another design might have ever( individual event wired to its own pin and
status 0it. This design, at the opposite e/treme from the single pin design, allows ver( comple/ hardware,
(et ver( simple control methods. Countless variations in wiring up events are possi0le. @owever, note that
care must 0e taken to ensure that if events share a signal that the event that generated the signal can 0e
determined in the corresponding event handling control method allowing the proper device notification to
0e sent.
4.9 Battery Management
;atter( management polic( moves from the A'M ;%2! to the AC'%&compati0le 2!. ;atteries must
compl( with the re:uirements of their associated interfaces, as descri0ed either herein or in other applica0le
standards. The 2! ma( choose to alter the 0ehavior of the 0atter(, for e/ample, 0( ad#usting the 1ow
;atter( or ;atter( Warning trip point. When there are multiple 0atteries present, the 0atter( su0s(stem is
not re:uired to perform an( s(nthesis of a Jcomposite 0atter(L from the data of the separate 0atteries. %n
cases where the 0atter( su0s(stem does not s(nthesiHe a Jcomposite 0atter(L from the separate 0atter(Us
data, the 2! must provide that s(nthesis.
An AC'%&compati0le 0atter( device needs either a !mart ;atter( su0s(stem interface or a Control Method
;atter( interface.
Smart )attery is controlled 0( the 2! directl( through the em0edded controller =.C>. 5or more
information a0out the AC'% .m0edded Controller !M;us interface, see section 42.6, J!M;us @ost
Controller %nterface via .m0edded Controller.L 5or additional information a0out the !mart ;atter(
su0s(stem interface, see section 4.4, J!mart ;atter( !u0s(stems.L
Control (et1od )attery is completel( accessed 0( AM1 code control methods, allowing the 2.M
to choose an( t(pe of 0atter( and an( kind of communication interface supported 0( AC'%. 5or more
information a0out the Control Method ;atter( %nterface, see section 4.2, JControl Method ;atteries.L
This section descri0es concepts common to all 0atter( t(pes.
4.9.1 Battery Communications
;oth the !mart ;atter( and Control Method ;atter( interfaces provide a mechanism for the 2! to :uer(
information from the platformMs 0atter( s(stem. This information ma( include full charged capacit(, present
0atter( capacit(, rate of discharge, and other measures of the 0atter(Ms condition. All 0atter( s(stem t(pes
must provide notification to the 2! when there is a change such as inserting or removing a 0atter(, or when
a 0atter( starts or stops discharging. !mart ;atteries and some Control Method ;atteries are also a0le to
give notifications 0ased on changes in capacit(. !mart 0atteries provide e/tra information such as estimated
run&time, information a0out how much power the 0atter( is a0le to provide, and what the run&time would
0e at a predetermined rate of consumption.
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4.9.2 Battery Capacity
.ach 0atter( must report its designed capacit(, latest full&charged capacit(, and present remaining capacit(.
3emaining capacit( decreases during usage, and it also changes depending on the environment. Therefore,
the 2! must use latest full&charged capacit( to calculate the 0atter( percentage. %n addition the 0atter(
s(stem must report warning and low 0atter( levels at which the user must 0e notified and the s(stem
transitioned to a sleeping state. !ee 5igure 3&3 for the relation of these five values.
A s(stem ma( use either rate and capacit( VmAFmAhW or power and energ( VmWFmWhW for the unit of
0atter( information calculation and reporting. Mi/ing VmAW and VmWW is not allowed on a s(stem.
O$M designed initial capacit, for warning
O$M designed initial capacit, for low
-ast full charged capacit,
'esigned capacit,
Present remaining capacit,
6igure #-# "eporting <atter) Capacit)
4.9.3 Battery Gas Gauge
At the most 0asic level, the 2! calculates 3emaining ;atter( 'ercentage VXW using the following formula<
Re%aining Battery Percentage9:; <
Battery Re%aining Capacity 9%Ah$%.h;
+ast 6(ll Charge" Capacity 9%Ah$%.h;
= 300
Control Method ;atter( also reports the 'resent -rain 3ate VmA or mWW for calculating the remaining
0atter( life. At the most 0asic level, 3emaining ;atter( life is calculated 0( following formula<
Re%aining Battery +ife 9h;<
Battery Re%aining Capacity 9%Ah$%.h;
Battery Present Drain Rate 9%A$%.;

!mart ;atteries also report the present rate of drain, 0ut since the( can directl( report the estimated run&
time, this function should 0e used instead as it can more accuratel( account for variations specific to the
0atter(.
4.9.4 Low Battery Levels
A s(stem has an 2.M&designed initial capacit( for warning, initial capacit( for low, and a critical 0atter(
level or flag. The values for warning and low represent the amount of energ( or 0atter( capacit( needed 0(
the s(stem to take certain actions. The critical 0atter( level or flag is used to indicate when the 0atteries in
the s(stem are completel( drained. 2!'M can determine independent warning and low 0atter( capacit(
values 0ased on the 2.M&designed levels, 0ut cannot set these values lower than the 2.M&designed
values, as shown in the figure 0elow
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
*" Advanced Configuration and 'ower %nterface !pecification

arning
-ow
.ull
Critical
O$M/designed initial capacit, for warning )minimum+
O$M/designed initial capacit, for low )minimum+
-ast full charged capacit,
OSPM/selected low 0atter,
capacit,
OSPM/selected low 0atter, warning capacit,
O$M/defined Batter, Critical flag
.
$
6igure #-( Low <atter) and :arning
.ach Control Method ;atter( in a s(stem reports the 2.M&designed initial warning capacit( and 2.M&
designed initial low capacit( as well as a flag to report when that 0atter( has reached or is 0elow its critical
energ( level. ,nlike Control Method ;atteries, !mart ;atteries are not necessaril( specific to one particular
machine t(pe, so the 2.M&designed warning, low, and critical levels are reported separatel( in a !mart
;atter( Ta0le descri0ed in section *.2.43.
The ta0le 0elow descri0es how these values should 0e set 0( the 2.M and interpreted 0( the 2!.
Ta!le #-+ Low <atter) Levels
Level 5escription
:arning When the total availa0le energ( =mWh> or capacit( =mAh> in the 0atteries falls 0elow this
level, the 2! will notif( the user through the ,%. This value should allow for a few minutes
of run&time 0efore the J1owL level is encountered so the user has time to wrap up an(
important work, change the 0atter(, or find a power outlet to plug the s(stem in.
Low This value is an estimation of the amount of energ( or 0atter( capacit( re:uired 0( the
s(stem to transition to an( supported sleeping state. When the 2! detects that the total
availa0le 0atter( capacit( is less than this value, it will transition the s(stem to a user
defined s(stem state =!4&!*>. %n most situations this should 0e !" so that s(stem state is not
lost if the 0atter( eventuall( 0ecomes completel( empt(. The design of the 2! should
consider that users of a multiple 0atter( s(stem ma( remove one or more of the 0atteries in
an attempt replace or charge it. This might result in the remaining capacit( falling 0elow the
J1owL level not leaving sufficient 0atter( capacit( for the 2! to safel( transition the s(stem
into the sleeping state. Therefore, if the 0atteries are discharging simultaneousl(, the action
might need to 0e initiated at the point when 0oth 0atteries reach this level.
Critical The Critical 0atter( state indicates that all availa0le 0atteries are discharged and do not
appear to 0e a0le to suppl( power to run the s(stem an( longer. When this occurs, the 2!
must attempt to perform an emergenc( shutdown as descri0ed 0elow.
5or a smart 0atter( s(stem, this would t(picall( occur when all 0atteries reach a capacit( of
, 0ut an 2.M ma( choose to put a larger value in the !mart ;atter( Ta0le to provide an
e/tra margin of safel(.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ **
Level 5escription
5or a Control Method ;atter( s(stem with multiple 0atteries, the flag is reported per
0atter(. %f an( 0atter( in the s(stem is in a criticall( low state and is still providing power to
the s(stem =in other words, the 0atter( is discharging>, the s(stem is considered to 0e in a
critical energ( state. The C;!T control method is re:uired to return the Critical flag on a
discharging 0atter( onl( when all 0atteries have reached a critical stateK the AC'% ;%2! is
otherwise re:uired to switch to a non&critical 0atter(.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
*+ Advanced Configuration and 'ower %nterface !pecification
4.9.4.1
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ *9
Emergency Shutdown
3unning until all 0atteries in a s(stem are critical is not a situation that should 0e encountered normall(,
since the s(stem should 0e put into a sleeping state when the 0atter( 0ecomes low. %n the case that this does
occur, the 2! should take steps to minimiHe an( damage to s(stem integrit(. The emergenc( shutdown
procedure should 0e designed to minimiHe 0ad effects 0ased on the assumption that power ma( 0e lost at
an( time. 5or e/ample, if a hard disk is spun down, the 2! should not tr( to spin it up to write an( data,
since spinning up the disk and attempting to write data could potentiall( corrupt files if the write were not
completed. .ven if a disk is spun up, the decision to attempt to save even s(stem settings data 0efore
shutting down would have to 0e evaluated since reverting to previous settings might 0e less harmful than
having the potential to corrupt the settings if power was lost halfwa( through the write operation.
4.9.5 Battery Calibration
The reported capacit( of man( 0atteries generall( degrade over time, providing less run time for the user.
@owever, it is possi0le with man( 0atter( s(stems to provide more usea0le runtime on an old 0atter( if a
cali0ration or conditioning c(cle is run occasionall(. The user has t(picall( 0een a0le to perform a
cali0ration c(cle either 0( going into the ;%2! setup menu, or 0( running a custom driver and cali0ration
application provided 0( the 2.M. The cali0ration process t(picall( takes several hours, and the laptop
must 0e plugged in during this time. %deall( the application that controls this should make this as good of a
user e/perience as possi0le, for e/ample allowing the user to schedule the s(stem to wake up and perform
the cali0ration at some time when the s(stem will not 0e in use. !ince the cali0ration user e/perience does
not need to 0e different from s(stem to s(stem it makes sense for this service to 0e provided 0( the 2!'M.
.%n this wa( 2!'M can provide a common e/perience for end users and eliminate the need for 2.Ms to
develop custom 0atter( cali0ration software.
%n order for 2!'M to perform generic 0atter( cali0ration, generic interfaces to control the two 0asic
cali0ration functions are re:uired. These functions are defined in section 4.2.2.* and 4.2.2.+. 5irst, there
is a means to detect when it would 0e 0eneficial to cali0rate the 0atter(. !econd there is a means to
perform that cali0ration c(cle. ;oth of those functions ma( 0e implemented 0( dedicated hardware such as
a 0atter( controller chip, 0( firmware in the em0edded controller, 0( the ;%2!, or 0( 2!'M. 5rom here on
an( function implemented through AM1, whether or not the AM1 code relies on hardware, will 0e referred
to as JAM1 controlledL since the interface is the same whether the AM1 passes control to the hardware or
not.
-etection of when cali0ration is necessar( can 0e implemented 0( hardware or AM1 code and 0e reported
through the C;M- method. Alternatel(, the C;M- method ma( simpl( report the num0er of c(cles 0efore
cali0ration should 0e performed and let the 2! attempt to count the c(cles. A counter implemented 0( the
hardware or the ;%2! will generall( 0e more accurate since the 0atteries can 0e used without the 2!
running, 0ut in some cases, a s(stem designer ma( opt to simplif( the hardware or ;%2! implementation.
When cali0ration is desira0le and the user has scheduled the cali0ration to occur, the cali0ration c(cle can
0e AM1 controlled or 2!'M controlled. 2!'M can onl( implement a ver( simple algorithm since it
doesnMt have knowledge of the specifics of the 0atter( s(stem. %t will simpl( discharge the 0atter( until it
:uits discharging, then charge it until it :uits charging. %n the case where the AC adapter cannot 0e
controlled through the C;MC, it will prompt the user to unplug the AC adapter and reattach it after the
s(stem powers off. %f the cali0ration c(cle is controlled 0( AM1, the 2! will initiate the cali0ration c(cle
0( calling C;MC. That method will either give control to the hardware, or will control the cali0ration c(cle
itself. %f the control of the cali0ration c(cle is implemented entirel( in AM1 code, the ;%2! ma( avoid
continuousl( running AM1 code 0( having the initial call to C;MC start the c(cle, set some state flags, and
then e/it. Control of later parts of the c(cle can 0e accomplished 0( putting code that checks these state
flags in the 0atter( event handler =CG//, C1//, or C.//>.
-etails of the control methods for this interface are defined in section 4.2.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
*8 Advanced Configuration and 'ower %nterface !pecification
4.10
Thermal Management
AC'% allows the 2! to pla( a role in the thermal management of the s(stem while maintaining the
platformMs a0ilit( to mandate cooling actions as necessar(. %n the passive cooling mode, 2!'M can make
cooling decisions 0ased on application load on the C', as well as the thermal heuristics of the s(stem.
2!'M can also gracefull( shutdown the computer in case of high temperature emergencies.
The AC'% thermal design is 0ased around regions called thermal Hones. $enerall(, the entire 'C is one
large thermal Hone, 0ut an 2.M can partition the s(stem into several logical thermal Hones if necessar(.
5igure 3&* is an e/ample mo0ile 'C diagram that depicts a single thermal Hone with a central processor as
the thermal&coupled device. %n this e/ample, the whole note0ook is covered as one large thermal Hone. This
note0ook uses one fan for active cooling and the C', for passive cooling.
.12 PIC3 PITs3
'MA3 RTC3 $IO3 444
CP8
CP8$
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PCI Bri"ge
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SIO2
COMs3
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-
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'
R
A
M
PCI/PCI
Bridge
-
A
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M
P
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5
&6RAM
+CD
-PT
COM
7''
!
*SB
Port !
CRT
#e,0oard
PS/"
Ports
Mouse
Docking
7''
1
.''
Momentar,
Thermal
Zone
'PR1
'PR!
P
-
-
Fan
(Actie !ooling"
(Passie !ooling"
6igure #-A Ther%al Ione
The following sections are an overview of the thermal control and cooling characteristics of a computer.
5or some thermal implementation e/amples on an AC'% platform, see section 44.*, JThermal ?one
%nterface 3e:uirements.L
4.10.1 Active and Passive Cooling Modes
AC'% defines two cooling modes, Active and 'assive<
Passive cooling. 2! reduces the power consumption of devices at the cost of s(stem performance
to reduce the temperature of the machine.
Active cooling. 2! increases the power consumption of the s(stem =for e/ample, 0( turning on a
fan> to reduce the temperature of the machine.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ *6
These two cooling modes are inversel( related to each other. Active cooling re:uires increased power to
reduce the heat within the s(stem while 'assive cooling re:uires reduced power to decrease the
temperature. The effect of this relationship is that Active cooling allows ma/imum s(stem performance, 0ut
it ma( create undesira0le fan noise, while 'assive cooling reduces s(stem performance, 0ut is inherentl(
:uiet.
4.10.2 Performance vs. Energy Conservation
A ro0ust 2!'M implementation provides the means for the end user to conve( to 2!'M a preference =or a
level of preference> for either performance or energ( conservation. Allowing the end user to choose this
preference is most critical to mo0ile s(stem users where ma/imiHing s(stem run&time on a 0atter( charge
often has higher priorit( over realiHing ma/imum s(stem performance.
A userMs preference for performance corresponds to the Active cooling mode while a userMs preference for
energ( conservation corresponds to the 'assive cooling mode. AC'% defines an interface to conve( the
cooling mode to the platform. Active cooling can 0e performed with minimal 2!'M thermal polic(
intervention. 5or e/ample, the platform indicates through thermal Hone parameters that crossing a thermal
trip point re:uires a fan to 0e turned on. 'assive cooling re:uires 2!'M thermal polic( to manipulate
device interfaces that reduce performance to reduce thermal Hone temperature.
4.10.3 Acoustics (Noise)
Active cooling mode generall( implies that fans will 0e used to cool the s(stem and fans var( in their
audi0le output. 5an noise can 0e :uite undesira0le given the loudness of the fan and the am0ient noise
environment. %n this case, the end userMs ph(sical re:uirement for fan silence ma( override the preference
for either performance or energ( conservation.
A userMs desire for fan silence corresponds to the 'assive cooling mode. Accordingl(, a userMs desire for fan
silence also means a preference for energ( conservation.
5or more information on thermal management and e/amples of platform settings for active and passive
cooling, see section 44, JThermal Management.L
4.10.4 Multiple Thermal Zones
The 0asic thermal management model defines one thermal Hone, 0ut in order to provide e/tended thermal
control in a comple/ s(stem, AC'% specifies a multiple thermal Hone implementation. ,nder a multiple
thermal Hone model, 2!'M will independentl( manage several thermal&coupled devices and a designated
thermal Hone for each thermal&coupled device, using Active andFor 'assive cooling methods availa0le to
each thermal Hone. .ach thermal Hone can have more than one 'assive and Active cooling device.
5urthermore, each Hone might have uni:ue or shared cooling resources. %n a multiple thermal Hone
configuration, if one Hone reaches a critical state then 2!'M must shut down the entire s(stem.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
+ Advanced Configuration and 'ower %nterface !pecification
5 ACPI Hardware Specifcation
AC'% defines standard interface mechanisms that allow an AC'%&compati0le 2! to control and
communicate with an AC'%&compati0le hardware platform. This section descri0es the hardware aspects of
AC'%.
AC'% defines JhardwareL as a programming model and its 0ehavior. AC'% strives to keep much of the
e/isting legac( programming model the sameK however, to meet certain feature goals, designated features
conform to a specific addressing and programming scheme. @ardware that falls within this categor( is
referred to as Jfi/ed.L
Although AC'% strives to minimiHe these changes, hardware engineers should read this section carefull( to
understand the changes needed to convert a legac(&onl( hardware model to an AC'%F1egac( hardware
model or an AC'%&onl( hardware model.
AC'% classifies hardware into two categories< 5i/ed or $eneric. @ardware that falls within the fi/ed
categor( meets the programming and 0ehavior specifications of AC'%. @ardware that falls within the
generic categor( has a wide degree of fle/i0ilit( in its implementation.
5.1 Fixed Hardware Programming Model
;ecause of the changes needed for migrating legac( hardware to the fi/ed categor(, AC'% limits the
features specified 0( fi/ed hardware. 5i/ed hardware features are defined 0( the following criteria<
'erformance sensitive features
5eatures that drivers re:uire during wake
5eatures that ena0le catastrophic 2! software failure recover(
AC'% defines register&0ased interfaces to fi/ed hardware. C', clock control and the power management
timer are defined as fi/ed hardware to reduce the performance impact of accessing this hardware, which
will result in more :uickl( reducing a thermal condition or e/tending 0atter( life. %f this logic were allowed
to reside in 'C% configuration space, for e/ample, several la(ers of drivers would 0e called to access this
address space. This takes a long time and will either adversel( affect the power of the s(stem =when tr(ing
to enter a low&power state> or the accurac( of the event =when tr(ing to get a time stamp value>.
Access to fi/ed hardware 0( 2!'M allows 2!'M to control the wake process without having to load the
entire 2!. 5or e/ample, if 'C% configuration space access is needed, the 0us enumerator is loaded with all
drivers used 0( the enumerator. -efining these interfaces in fi/ed hardware at addresses with which 2!'M
can communicate without an( other driverMs assistance, allows 2!'M to gather information prior to
making a decision as to whether it continues loading the entire 2! or puts it 0ack to sleep.
%f elements of the 2! fail, it ma( 0e possi0le for 2!'M to access address spaces that need no driver
support. %n such a situation, 2!'M will attempt to honor fi/ed power 0utton re:uests to transition the
s(stem to the $2 state. %n the case where 2!'M event handler is no longer a0le to respond to power 0utton
events, the power 0utton override feature provides a 0ack&up mechanism to unconditionall( transition the
s(stem to the soft&off state.
5.1.1 Functional Fixed Hardware
AC'% defines the fi/ed hardware low&level interfaces as a means to conve( to the s(stem 2.M the
minimum interfaces necessar( to achieve a level of capa0ilit( and :ualit( for mother0oard configuration
and s(stem power management. Additionall(, the definition of these interfaces, as well as others defined in
this specification, conve(s to 2! Dendors =2!Ds> developing AC'%&compati0le operating s(stems, the
necessar( interfaces that operating s(stems must manipulate to provide ro0ust support for s(stem
configuration and power management.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ +4
While the definition of low&level hardware interfaces defined 0( AC'% 4. afforded 2!'M
implementations a certain level of sta0ilit(, controls for e/isting and emerging diverse C', architectures
cannot 0e accommodated 0( this model as the( can re:uire a se:uence of hardware manipulations
intermi/ed with native C', instructions to provide the AC'%&defined interface function. %n this case, an
AC'%&defined fi/ed hardware interface can 0e functionall( implemented 0( the C', manufacturer through
an e:uivalent com0ination of 0oth hardware and software and is defined 0( AC'% as 5unctional 5i/ed
@ardware.
%n %A&32&0ased s(stems, functional fi/ed hardware can 0e accommodated in an 2! independent manner 0(
using !(stem Management Mode =!MM> 0ased s(stem firmware. ,nfortunatel(, the nature of !MM&0ased
code makes this t(pe of 2! independent implementation difficult if not impossi0le to de0ug. As such, this
implementation approach is not recommended. %n some cases, 5unctional 5i/ed @ardware implementations
ma( re:uire coordination with other 2! components. As such, an 2! independent implementation ma( not
0e via0le.
2!&specific implementations of functional fi/ed hardware can 0e implemented using technical information
supplied 0( the C', manufacturer. The downside of this approach is that functional fi/ed hardware support
must 0e developed for each 2!. %n some cases, the C', manufacturer ma( provide a software component
providing this support. %n other cases support for the functional fi/ed hardware ma( 0e developed directl(
0( the 2! vendor.
The hardware register definition was e/panded, in AC'% 2., to allow registers to e/ist in address spaces
other than the !(stem %F2 address space. This is accomplished through the specification of an address space
%- in the register definition =see section *.2.3.4, J$eneric Address !tructure,L for more information>. :hen
specificall) directed !) the CP2 %anufacturer' the s(stem firmware ma( define an interface as
functional fi/ed hardware 0( suppl(ing a special address space identifier, )fi%edH6 (5%9)), in the address
space %- field for register definitions. %t is emphasiHed that functional fi/ed hardware definitions ma( 0e
declared in the AC'% s(stem firmware onl) as indicated !) the CP2 Manufacturer for specific interfaces
as the use of functional fi/ed hardware re:uires specific coordination with the 2! vendor.
2nl( certain AC'%&defined interfaces ma( 0e implemented using functional fi/ed hardware and onl( when
the interfaces are common across machine designs for e/ample, s(stems sharing a common C',
architecture that does not support fi/ed hardware implementation of an AC'%&defined interface. 2.Ms are
cautioned not to anticipate that functional fi/ed hardware support will 0e provided 0( 2!'M differentl( on
a s(stem&0(&s(stem 0asis. The use of functional fi/ed hardware carries with it a reliance on 2! specific
software that must 0e considered. 2.Ms should consult 2! vendors to ensure that specific functional fi/ed
hardware interfaces are supported 0( specific operating s(stems.
5.2 Generic Hardware Programming Model
Although the fi/ed hardware programming model re:uires hardware registers to 0e defined at specific
address locations, the generic hardware programming model allows hardware registers to reside in most
address spaces and provides s(stem 2.Ms with a wide degree of fle/i0ilit( in the implementation of
specific functions in hardware. 2!'M directl( accesses the fi/ed hardware registers, 0ut relies on 2.M&
provided AC'% Machine 1anguage =AM1> code to access generic hardware registers.
AM1 code allows the 2.M to provide the means for 2!'M to control a generic hardware featureMs control
and event logic.
The section entitled JAC'% !ource 1anguage 3eferenceL descri0es the AC'% !ource 1anguage =A!1>Pa
programming language that 2.Ms use to create AM1. The A!1 language provides man( of the operators
found in common o0#ect&oriented programming languages, 0ut it has 0een optimiHed to ena0le the
description of platform power management and configuration hardware. An A!1 compiler converts A!1
source code to AM1, which is a ver( compact machine language that the AC'% AM1 code interpreter
e/ecutes.
AM1 does two things<
A0stracts the hardware from 2!'M
;uffers 2.M code from the different 2! implementations
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
+2 Advanced Configuration and 'ower %nterface !pecification
2ne goal of AC'% is to allow the 2.M Jvalue addedL hardware to remain 0asicall( unchanged in an AC'%
configuration. 2ne attri0ute of value&added hardware is that it is all implemented differentl(. To ena0le
2!'M to e/ecute properl( on different t(pes of value added hardware, AC'% defines higher level Jcontrol
methodsL that it calls to perform an action. The 2.M provides AM1 code, which is associated with control
methods, to 0e e/ecuted 0( 2!'M. ;( providing AM1 code, generic hardware can take on almost an(
form.
Another important goal of AC'% is to provide 2! independence. To do this, the 2.M AM1 code has to
e/ecute the same under an( AC'%&compati0le 2!. AC'% allows for this 0( making the AM1 code
interpreter part of 2!'M. This allows 2!'M to take care of s(nchroniHing and 0locking issues specific to
each particular 2!.
The generic feature model is represented in the following 0lock diagram. %n this model the generic feature
is descri0ed to 2!'M through AM1 code. This description takes the form of an o0#ect that sits in the AC'%
Namespace associated with the hardware to which it is adding value.

;eneric 1vent
Logic
Control
1vents
ACPI 5river
and AML-
Code Interpreter
;eneric
Control
Logic
AML
Code
"ds
;P 1vent Status
;eneric Child
1vent Status
6igure (-+ ;eneric Hardware 6eature Model
As an e/ample of a generic hardware control feature, a platform might 0e designed such that the %-.
@--Ms -3 state has value&added hardware to remove power from the drive. The %-. drive would then have
a reference to the AM1 Power"esource o0#ect =which controls the value added power plane> in its
namespace, and associated with that o0#ect would 0e control methods that 2!'M invokes to control the -3
state of the drive<
DPS$. A control method to se:uence the %-. drive to the - state.
DPS#. A control method to se:uence the %-. drive to the -3 state.
DPSC. A control method that returns the status of the %-. drive =on or off>.
The control methods under this o0#ect provide an a0straction la(er 0etween 2!'M and the hardware.
2!'M understands how to control power planes =turn them on or off or to get their status> through its
defined Power"esource o0#ect, while the hardware has platform&specific AM1 code =contained in the
appropriate control methods> to perform the desired function. %n this e/ample, the platform would descri0e
its hardware to the AC'% 2! 0( writing and placing the AM1 code to turn the hardware off within the C'!3
control method. This ena0les the following se:uence<
When 2!'M decides to place the %-. drive in the -3 state, it calls the %-. driver and tells it to place the
drive into the -3 state =at which point the driver saves the deviceMs conte/t>.
When the %-. driver returns control, 2!'M places the drive in the -3 state.
2!'M finds the o0#ect associated with the @-- and then finds within that o0#ect an( AM1 code associated
with the -3 state.
2!'M e/ecutes the appropriate C'!3 control method to control the value&added JgenericL hardware to
place the @-- into an even lower power state.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ +3
As an e/ample of a generic event feature, a platform might have a docking capa0ilit(. %n this case, it will
want to generate an event. Notice that all AC'% events generate an !C%, which can 0e mapped to an(
sharea0le s(stem interrupt. %n the case of docking, the event is generated when a docking has 0een detected
or when the user re:uests to undock the s(stem. This ena0les the following se:uence<
2!'M responds to the !C% and calls the AM1 code event handler associated with that generic event. The
AC'% ta0le associates the hardware event with the AM1 code event handler.
The AM1&code event handler collects the appropriate information and then e/ecutes an AM1 Notif(
command to indicate to 2!'M that a particular 0us needs re&enumeration.
The following sections descri0e the fi/ed and generic hardware feature set of AC'%. These sections ena0le
a reader to understand the following<
Which hardware registers are re:uired or optional when an AC'% feature, concept or interface is
re:uired 0( a design guide for a platform class
@ow to design fi/ed hardware features
@ow to design generic hardware features
The AC'% .vent Model
5.3 Diagram Legends
The hardware section uses simplified logic diagrams to represent how certain aspects of the hardware are
implemented. The following s(m0ols are used in the logic diagrams to represent programming 0its.
Write&onl( control 0it
.na0le, control or status 0it
!tick( status 0it
88
Guer( value
The half round s(m0ol with an inverted JDL represents a write&onl( control 0it. This 0it has the 0ehavior
that it generates its control function when it is set. 3eads to write&onl( 0its are treated as ignore 0( software
=the 0it position is masked off and ignored>.
The round s(m0ol with an JAL represents a programming 0it. As an ena0le or control 0it, software setting
or clearing this 0it will result in the 0it 0eing read as set or clear =unless otherwise noted>. As a status 0it it
directl( represents the value of the signal.
The s:uare s(m0ol represents a stick( status 0it. A stick( status 0it is set 0( the level =not edge> of a
hardware signal =active high or active low>. The 0it is onl( cleared 0( software writing a J4L to its 0it
position.
The rectangular s(m0ol represents a :uer( value from the em0edded controller. This is the value the
em0edded controller returns to the s(stem software upon a :uer( command in response to an !C% event.
The :uer( value is associated with the event control method that is scheduled to e/ecute upon an em0edded
controller event.
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+" Advanced Configuration and 'ower %nterface !pecification
5.4 Register Bit Notation
Throughout this section there are logic diagrams that reference 0its within registers. These diagrams use a
notation that easil( references the register name and 0it position. The notation is as follows<
$egistername.)it
$egistername contains the name of the register as it appears in this specification
)it contains a Hero&0ased decimal value of the 0it position.
5or e/ample, the !1'C.N 0it resides in the 'M4/CCNT register 0it 43 and would 0e represented in
diagram notation as<
SLP_EN
PM1x_CNT.13
5.5 The ACPI Hardware Model
The AC'% hardware model is defined to allow 2!'M to se:uence the platform 0etween the various glo0al
s(stem states =$&$3> as illustrated in the following figure 0( manipulating the defined interfaces. When
first powered on, the platform finds itself in the glo0al s(stem state $3 or JMechanical 2ff.L This state is
defined as one where power consumption is ver( close to HeroPthe power plug has 0een removedK
however, the real&time clock device still runs off a 0atter(. The $3 state is entered 0( an( power failure,
defined as accidental or user&initiated power loss.
The $3 state transitions into either the $ working state or the 1egac( state depending on what the
platform supports. %f the platform is an AC'%&onl( platform, then it allows a direct 0oot into the $
working state 0( alwa(s returning the status 0it !C%C.N set =4> =for more information, see section ".9.2.*,
J1egac(FAC'% !elect and the !C% %nterruptL>. %f the platform supports 0oth legac( and AC'% operations
=which is necessar( for supporting a non&AC'% 2!>, then it would alwa(s 0oot into the 1egac( state
=illustrated 0( returning the !C%C.N clear =>>. %n either case, a transition out of the $3 state re:uires a total
0oot of 2!'M.
The 1egac( s(stem state is the glo0al state where a non&AC'% 2! e/ecutes. This state can 0e entered from
either the $3 JMechanical 2ff,L the $2 J!oft 2ff,L or the $ JWorkingL states onl( if the hardware
supports 0oth 1egac( and AC'% modes. %n the 1egac( state, the AC'% event model is disa0led =no !C%s are
generated> and the hardware uses legac( power management and configuration mechanisms. While in the
1egac( state, an AC'%&compliant 2! can re:uest a transition into the $ working state 0( performing an
AC'% mode re:uest. 2!'M performs this transition 0( writing the AC'%C.NA;1. value to the
!M%CCM-, which generates an event to the hardware to transition the platform into AC'% mode. When
hardware has finished the transition, it sets the !C%C.N 0it and returns control 0ack to 2!'M. While in the
$ Jworking state,L 2!'M can re:uest a transition to 1egac( mode 0( writing the AC'%C-%!A;1. value
to the !M%CCM- register, which results in the hardware going into legac( mode and resetting the !C%C.N
0it 12W =for more information, see section ".9.2.*, J1egac(FAC'% !elect and the !C% %nterruptL>.
The $ JWorkingL state is the normal operating environment of an AC'% machine. %n this state different
devices are d(namicall( transitioning 0etween their respective power states =-, -4, -2 or -3> and
processors are d(namicall( transitioning 0etween their respective power states =C, C4, C2 or C3>. %n this
state, 2!'M can make a polic( decision to place the platform into the s(stem $4 JsleepingL state. The
platform can onl( enter a single sleeping state at a time =referred to as the glo0al $4 state>K however, the
hardware can provide up to four s(stem sleeping states that have different power and e/it latencies
represented 0( the !4, !2, !3, or !" states. When 2!'M decides to enter a sleeping state it picks the most
appropriate sleeping state supported 0( the hardware =2! polic( e/amines what devices have ena0led wake
events and what sleeping states these support>. 2!'M initiates the sleeping transition 0( ena0ling the
appropriate wake events and then programming the !1'CTS'/ field with the desired sleeping state and
then setting the !1'C.N/ 0it. The s(stem will then enter a sleeping stateK when one of the ena0led wake
events occurs, it will transition the s(stem 0ack to the working state =for more information, see section 4*,
JWaking and !leepingL>.
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Another glo0al state transition option while in the $ JworkingL state is to enter the $2 Jsoft offL or the $3
Jmechanical offL state. These transitions represent a controlled transition that allows 2!'M to 0ring the
s(stem down in an orderl( fashion =unloading applications, closing files, and so on>. The polic( for these
t(pes of transitions can 0e associated with the AC'% power 0utton, which when pressed generates an event
to the power 0utton driver. When 2!'M is finished preparing the operating environment for a power loss,
it will either generate a pop&up message to indicate to the user to remove power, in order to enter the $3
JMechanical 2ffL state, or it will initiate a $2 Jsoft&offL transition 0( writing the value of the !* Jsoft offL
s(stem state to the !1'CTS'/ register and setting the !1'C.N 0it.
The $4 sleeping state is represented 0( four possi0le sleeping states that the hardware can support. .ach
sleeping state has different power and wake latenc( characteristics. The sleeping state differs from the
working state in that the userMs operating environment is froHen in a low&power state until awakened 0( an
ena0led wake event. No work is performed in this state, that is, the processors are not e/ecuting
instructions. .ach s(stem sleeping state has re:uirements a0out who is responsi0le for s(stem conte/t and
wake se:uences =for more information, see section 4*, Waking and !leepingL>.
The $2 Jsoft offL state is an 2! initiated s(stem shutdown. This state is initiated similar to the sleeping
state transition =!1'CTS'/ is set to the !* value and setting the !1'C.N 0it initiates the se:uence>.
./iting the $2 soft&off state re:uires re0ooting the s(stem. %n this case, an AC'%&onl( machine will re&enter
the $ state directl( =hardware returns the !C%C.N 0it set>, while an AC'%F1egac( machine transitions to
the 1egac( state =!C%C.N 0it is clear>.
S4BIOS>6
S4BIOS>R&?
ACPI>DISAB+&
1SCI>&@<02
,- -*ech
Off
+egacy
Boot
1SCI>&@<02
+egacy
Boot
1SCI>&@<02
ACPI>&@AB+&
1SCI>&@<32
+egacy
S+P>TAP'<S7
an"
S+P>&@
or
P.RBT@>OR
.a/e
&vent
C0
,0 1S02 -
.or/ing
,3 -
Sleeping
S4
S-
S5
S3
Po#er
6ail(re$
Po#er Off
ACPI
Boot
1SCI>&@<32
ACPI
Boot
1SCI>&@<32
,5 1S72 -
Soft Off
S+P>TAP'<1S3-S42
an"
S+P>&@
D0
D3
D5
D-
*o"e%
D0
D3
D5
D-
!DD
D0
D3
D5
D-
CDRO*
BIOS
Routine
C5
C3
Cn
Performance
State Px
Throttling
C0
CP8
6igure (-& ;lo!al States and Their Transitions
The AC'% architecture defines mechanisms for hardware to generate events and control logic to implement
this 0ehavior model. .vents are used to notif( 2!'M that some action is needed, and control logic is used
0( 2!'M to cause some state transition. AC'%&defined events are JhardwareL or JinterruptL events. A
hardware event is one that causes the hardware to unconditionall( perform some operation. 5or e/ample,
an( wake event will se:uence the s(stem from a sleeping state =!4, !2, !3, and !" in the glo0al $4 state> to
the $ working state =see 5igure 4*&4>.
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++ Advanced Configuration and 'ower %nterface !pecification
An interrupt event causes the e/ecution of an event handler =AM1 code or an AC'%&aware driver>, which
allows the software to make a polic( decision 0ased on the event. 5or AC'% fi/ed&feature events, 2!'M or
an AC'%&aware driver acts as the event handler. 5or generic logic events 2!'M will schedule the e/ecution
of an 2.M&supplied AM1 control method associated with the event.
5or legac( s(stems, an event normall( generates an 2!&transparent interrupt, such as a !(stem
Management %nterrupt, or !M%. 5or AC'% s(stems the interrupt events need to generate an 2!&visi0le
interrupt that is sharea0leK edge&st(le interrupts will not work. @ardware platforms that want to support
0oth legac( operating s(stems and AC'% s(stems support a wa( of re&mapping the interrupt events 0etween
!M%s and !C%s when switching 0etween AC'% and legac( models. This is illustrated in the following 0lock
diagram.
Po#er Plane
Control
5eneric Space
,+B+ STBA
Ti%er
P.RBT@
+ID
T!R*
DOCK
STS>C!,
RI
S*I Arbiter
Sleep$.a/e
State %achine
S*IB
SCIB
+egacy Only &vent +ogic
ACPI$+egacy &vent +ogic
ACPI Only &vent +ogic
S*I &vents
SCI$S*I &vents
'ec
1
!
CP8 Cloc/
Control
Device
Traps
Device I"le
Ti%ers
8ser
Interface
Ther%al
+ogic
!ar"#are
&vents
RTC
SCI%$&
ACPI$+egacy ,eneric Control 6eat(res
ACPI$+egacy 6i'e" Control 6eat(res
.a/e-(p &vents
P* Ti%er
SCI Arbiter
6igure (-# 1xa%ple 1vent Structure for a Legac)@ACPI Co%pati!le 1vent Model
This e/ample logic illustrates the event model for a sample platform that supports 0oth legac( and AC'%
event models. This e/ample platform supports a num0er of e/ternal events that are power&related =power
0utton, 1%- openFclose, thermal, ring indicate> or 'lug and 'la(&related =dock, status change>. The logic
represents the three different t(pes of events<
3S Transparent 1vents. These events represent 2.M&specific functions that have no 2! support
and use software that can 0e operated in an 2!&transparent fashion =that is, !M%s>.
Interrupt 1vents. These events represent features supported 0( AC'%&compati0le operating
s(stems, 0ut are not supported 0( legac( operating s(stems. When a legac( 2! is loaded, these events
are mapped to the transparent interrupt =!M%Y in this e/ample>, and when in AC'% mode the( are
mapped to an 2!&visi0le sharea0le interrupt =!C%Y>. This logic is represented 0( routing the event
logic through the decoder that routes the events to the !M%Y ar0iter when the !C%C.N 0it is cleared, or
to the !C%Y ar0iter when the !C%C.N 0it is set.
Hardware events. These events are used to trigger the hardware to initiate some hardware
se:uence such as waking, resetting, or putting the machine to sleep unconditionall(.
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%n this e/ample, the legac( power management event logic is used to determine deviceFs(stem activit( or
idleness 0ased on device idle timers, device traps, and the glo0al stand0( timer. 1egac( power management
models use the idle timers to determine when a device should 0e placed in a low&power state 0ecause it is
idlePthat is, the device has not 0een accessed for the programmed amount of time. The device traps are
used to indicate when a device in a low&power state is 0eing accessed 0( 2!'M. The glo0al stand0( timer
is used to determine when the s(stem should 0e allowed to go into a sleeping state 0ecause it is idlePthat
is, the user interface has not 0een used for the programmed amount of time.
These legac( idle timers, trap monitors, and glo0al stand0( timer are not used 0( 2!'M in the AC'% mode.
This work is handled 0( different software structures in an AC'%&compati0le 2!. 5or e/ample, the driver
model of an AC'%&compati0le 2! is responsi0le for placing its device into a low&power state =-4, -2, or
-3> and transitioning it 0ack to the 2n state =-> when needed. And 2!'M is responsi0le for determining
when the s(stem is idle 0( profiling the s(stem =using the 'M Timer> and other knowledge it gains through
its operating structure environment =which will var( from 2! to 2!>. When the s(stem is placed into the
AC'% mode, these events no longer generate !M%s, as 2!'M handles this function. These events are
disa0led through some 2.M&proprietar( method.
2n the other hand, man( of the hardware events are shared 0etween the AC'% and legac( models =docking,
the power 0utton, and so on> and this t(pe of interrupt event changes to an !C% event when ena0led for
AC'%. The AC'% 2! will generate a re:uest to the platformMs hardware =;%2!> to enter into the AC'%
mode. The ;%2! sets the !C%C.N 0it to indicate that the s(stem has successfull( entered into the AC'%
mode, so this is a convenient mechanism to map the desired interrupt =!M% or !C%> for these events =as
shown in 5igure "&3>.
The AC'% architecture specifies some dedicated hardware not found in the legac( hardware model< the
power management timer ='M Timer>. This is a free running timer that the AC'% 2! uses to profile s(stem
activit(. The fre:uenc( of this timer is e/plicitl( defined in this specification and must 0e implemented as
descri0ed.
Although the AC'% architecture reuses most legac( hardware as is, it does place restrictions on where and
how the programming model is generated. %f used, all fi/ed hardware features are implemented as
descri0ed in this specification so that 2!'M can directl( access the fi/ed hardware feature registers.
$eneric hardware features are manipulated 0( AC'% control methods residing in the AC'% Namespace.
These interfaces can 0e ver( fle/i0leK however, their use is limited 0( the defined AC'% control methods
=for more information, see section 6, JAC'% -evices and -evice !pecific 20#ectsL>. $eneric hardware
usuall( controls power planes, 0uffer isolation, and device reset resources. Additionall(, JchildL interrupt
status 0its can 0e accessed via generic hardware interfacesK however, the( have a JparentL interrupt status
0it in the $'C!T! register. AC'% defines seven address spaces that ma( 0e accessed 0( generic hardware
implementations. These include<
!(stem %F2 space
!(stem memor( space
'C% configuration space
.m0edded controller space
!(stem Management ;us =!M;us> space
CM2!
'C% ;A3 Target
$eneric hardware power management features can 0e implemented accessing spare %F2 ports residing in
an( of these address spaces. The AC'% specification defines an optional em0edded controller and !M;us
interfaces needed to communicate with these associated address spaces.
5.5.1 Hardware Reserved Bits
AC'% hardware registers are designed such that reserved 0its alwa(s return Hero, and data writes to them
have no side affects. 2!'M implementations must write Heros to reserved 0its in ena0le and status registers
and preserve 0its in control registers, and the( will treat these 0its as ignored.
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+8 Advanced Configuration and 'ower %nterface !pecification
5.5.2 Hardware Ignored Bits
AC'% hardware registers are designed such that ignored 0its are undefined and are ignored 0( software.
@ardware&ignored 0its can return Hero or one. When software reads a register with ignored 0its, it masks off
ignored 0its prior to operating on the result. When software writes to a register with ignored 0it fields, it
preserves the ignored 0it fields.
5.5.3 Hardware Write-Only Bits
AC'% hardware defines a num0er of write&onl( control 0its. These 0its are activated 0( software writing a 4
to their 0it position. 3eads to write&onl( 0it positions generate undefined results. ,pon reads to registers
with write&onl( 0its, software masks out all write&onl( 0its.
5.5.4 Cross Device Dependencies
Cross -evice -ependenc( is a condition in which an operation to a device interferes with the operation of
other unrelated devices, or allows other unrelated devices to interfere with its 0ehavior. This condition is
not supporta0le and can cause platform failures. AC'% provides no support for cross device dependencies
and suggests that devices 0e designed to not e/hi0it this 0ehavior. The following two e/amples descri0e
cross device dependencies<
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5.5.4.1
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9 Advanced Configuration and 'ower %nterface !pecification
Example 1: Related Device Interference
This e/ample illustrates a cross device dependenc( where a device interferes with the proper operation of
other unrelated devices. -evice A has a dependenc( that when it is 0eing configured it 0locks all accesses
that would normall( 0e targeted for -evice ;. Thus, the device driver for -evice ; cannot access -evice ;
while -evice A is 0eing configuredK therefore, it would need to s(nchroniHe access with the driver for
-evice A. @igh performance, multithreaded operating s(stems cannot perform this kind of s(nchroniHation
without seriousl( impacting performance.
To further illustrate the point, assume that -evice A is a serial port and -evice ; is a hard drive controller.
%f these devices demonstrate this 0ehavior, then when a software driver configures the serial port, accesses
to the hard drive need to 0lock. This can onl( 0e done if the hard disk driver s(nchroniHes access to the disk
controller with the serial driver. Without this s(nchroniHation, hard drive data will 0e lost when the serial
port is 0eing configured.
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5.5.4.2
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92 Advanced Configuration and 'ower %nterface !pecification
Example 2: Unrelated Device Interference
This e/ample illustrates a cross&device dependenc( where a device demonstrates a 0ehavior that allows
other unrelated devices to interfere with its proper operation. -evice A e/hi0its a programming 0ehavior
that re:uires atomic 0ack&to&0ack write accesses to successfull( write to its registersK if an( other platform
access is a0le to 0reak 0etween the 0ack&to&0ack accesses, then the write to -evice A is unsuccessful. %f the
-evice A driver is una0le to generate atomic 0ack&to&0ack accesses to its device, then it relies on software
to s(nchroniHe accesses to its device with ever( other driver in the s(stemK then a device cross dependenc(
is created and the platform is prone to -evice A failure.
5.6 ACPI Hardware Features
This section descri0es the different hardware features defined 0( the AC'% interface. These features are
categoriHed as the following<
5i/ed @ardware 5eatures
$eneric @ardware 5eatures
5i/ed hardware features reside in a num0er of the AC'%&defined address spaces at the locations descri0ed
0( the AC'% programming model. $eneric hardware features reside in one of four address spaces =s(stem
%F2, s(stem memor(, 'C% configuration, em0edded controller, or serial device %F2 space> and are descri0ed
0( the AC'% Namespace through the declaration of AM1 control methods.
5i/ed hardware features have e/act definitions for their implementation. Although man( fi/ed hardware
features are optional, if implemented the( must 0e implemented as descri0ed since 2!'M manipulates the
registers of fi/ed hardware devices and e/pects the defined 0ehavior. 5unctional fi/ed hardware provides
functional e:uivalents of the fi/ed hardware feature interfaces as descri0ed in section ".4.4, J5unctional
5i/ed @ardware.L
$eneric hardware feature implementation is fle/i0le. This logic is controlled 0( 2.M&supplied AM1 code
=for more information, see section *, JAC'% !oftware 'rogramming ModelL>, which can 0e written to
support a wide variet( of hardware. Also, AC'% provides specialiHed control methods that provide
capa0ilities for specialiHed devices. 5or e/ample, the Notif( command can 0e used to notif( 2!'M from a
generic hardware event handler =control method> that a docking or thermal event has taken place. A good
understanding of this section and section * of this specification will give designers a good understanding of
how to design hardware to take full advantage of an AC'%&compati0le 2!.
Notice that the generic features are listed for illustration onl(, the AC'% specification can support man(
t(pes of hardware not listed.
Ta!le (-+ 6eature@Progra%%ing Model Su%%ar)
6eature 0a%e 5escription Progra%%ing Model
'ower Management Timer 2"&0it or 32&0it free running timer. 5i/ed @ardware 5eature Control
1ogic
'ower ;utton ,ser pushes 0utton to switch the
s(stem 0etween the working and
sleeping states.
5i/ed @ardware .vent and
Control 1ogic or $eneric
@ardware .vent and 1ogic
!leep ;utton ,ser pushes 0utton to switch the
s(stem 0etween the working and
sleeping state.
5i/ed @ardware .vent and
Control 1ogic or $eneric
@ardware .vent and 1ogic
'ower ;utton 2verride ,ser se:uence =press the power
0utton for " seconds> to turn off a
hung s(stem.
3eal Time Clock Alarm 'rogrammed time to wake the
s(stem.
2ptional 5i/ed @ardware .vent
2
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6eature 0a%e 5escription Progra%%ing Model
!leepFWake Control 1ogic 1ogic used to transition the s(stem
0etween the sleeping and working
states.
5i/ed @ardware Control and
.vent 1ogic
.m0edded Controller
%nterface
AC'% .m0edded Controller protocol
and interface, as descri0ed in section
42, JAC'% .m0edded Controller
%nterface !pecification.L
$eneric @ardware .vent 1ogic,
must reside in the general&
purpose register 0lock
1egac(FAC'% !elect !tatus 0it that indicates the s(stem is
using the legac( or AC'% power
management model =!C%C.N>.
5i/ed @ardware Control 1ogic
1id switch ;utton used to indicate whether the
s(stemMs lid is open or closed =mo0ile
s(stems onl(>.
$eneric @ardware .vent 5eature
C4 'ower !tate 'rocessor instruction to place the
processor into a low&power state.
'rocessor %!A
C2 'ower Control 1ogic to place the processor into a
C2 power state.
5i/ed @ardware Control 1ogic
C3 'ower Control 1ogic to place the processor into a
C3 power state.
5i/ed @ardware Control 1ogic
Thermal Control 1ogic to generate thermal events at
specified trip points.
$eneric @ardware .vent and
Control 1ogic =!ee description of
thermal logic in section 3.4,
JThermal Management.L>
-evice 'ower Management Control logic for switching 0etween
different device power states.
$eneric @ardware control logic
AC Adapter 1ogic to detect the insertion and
removal of the AC adapter.
$eneric @ardware event logic
-ockingFdevice insertion
and removal
1ogic to detect device insertion and
removal events.
$eneric @ardware event logic
5.7 ACPI Register Model
AC'% hardware resides in one of si/ address spaces<
!(stem %F2
!(stem memor(
'C% configuration
!M;us
.m0edded controller
5unctional 5i/ed @ardware
-ifferent implementations will result in different address spaces 0eing used for different functions. The
AC'% specification consists of fi/ed hardware registers and generic hardware registers. 5i/ed hardware
registers are re:uired to implement AC'%&defined interfaces. The generic hardware registers are needed for
an( events generated 0( value&added hardware.
2
3TC wakeup alarm is re:uired, the fi/ed hardware feature status 0it is optional.
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9" Advanced Configuration and 'ower %nterface !pecification
AC'% defines register 0locks. An AC'%&compati0le s(stem provides an AC'% ta0le =the 5A-T, 0uilt in
memor( at 0oot&up> that contains a list of pointers to the different fi/ed hardware register 0locks used 0(
2!'M. The 0its within these registers have attri0utes defined for the given register 0lock. The t(pes of
registers that AC'% defines are<
!tatusF.na0le 3egisters =for events>
Control 3egisters
%f a register 0lock is of the statusFena0le t(pe, then it will contain a register with status 0its, and a
corresponding register with ena0le 0its. The status and ena0le 0its have an e/act implementation definition
that needs to 0e followed =unless otherwise noted>, which is illustrated 0( the following diagram<
Status Bit
$na0le Bit
$9ent Input
$9ent Output
6igure (-( <lock 5iagra% of a Status@1na!le Cell
Notice that the status 0it, which hardware sets 0( the .vent %nput 0eing set in this e/ample, can onl( 0e
cleared 0( software writing a 4 to its 0it position. Also, the ena0le 0it has no effect on the setting or
resetting of the status 0itK it onl( determines if the !.T status 0it will generate an J.vent 2utput,L which
generates an !C% when set if its ena0le 0it is set.
AC'% also defines register groupings. A register grouping consists of two register 0locks, with two pointers
to two different 0locks of registers, where each 0it location within a register grouping is fi/ed and cannot
0e changed. The 0its within a register grouping, which have fi/ed 0it positions, can 0e split 0etween the
two register 0locks. This allows the 0its within a register grouping to reside in either or 0oth register 0locks,
facilitating the a0ilit( to map 0its within several different chips to the same register thus providing the
programming model with a single register grouping 0it structure.
2!'M treats a register grouping as a single registerK 0ut located in multiple places. To read a register
grouping, 2!'M will read the JAL register 0lock, followed 0( the J;L register 0lock, and then will
logicall( J23L the two results together =the !1'CTS' field is an e/ception to this rule>. 3eserved 0its, or
unused 0its within a register 0lock alwa(s return Hero for reads and have no side effects for writes =which is
a re:uirement>.
The !1'CTS'/ field can 0e different for each register grouping. The respective sleeping o0#ect BC!x
contains a !1'CTS'a and a !1'CTS'0 field. That is, the o0#ect returns a package with two integer values
of &9 in it. 2!'M will alwa(s write the !1'CTS'a value to the JAL register 0lock followed 0( the
!1'CTS'0 value within the field to the J;L register 0lock. All other 0it locations will 0e written with the
same value. Also, 2!'M does not read the !1'CTS'/ value 0ut throws it awa(.
Register Bloc: A
Register Bloc: B
B
it d
B
it c
B
it 0
B
it a
B
it e
Register
5rouping
6igure (-A 1xa%ple 6ixed Hardware 6eature "egister ;rouping
As an e/ample, the a0ove diagram represents a register grouping consisting of register 0lock A and register
0lock 0. ;its JaL and JdL are implemented in register 0lock ; and register 0lock A returns a Hero for these
0it positions. ;its J0L, JcL and JeL are implemented in register 0lock A and register 0lock ; returns a Hero
for these 0it positions. All reserved or ignored 0its return their defined AC'% values.
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When accessing this register grouping, 2!'M must read register 0lock a, followed 0( reading register
0lock 0. 2!'M then does a logical 23 of the two registers and then operates on the results.
When writing to this register grouping, 2!'M will write the desired value to register group A followed 0(
writing the same value to register group ;.
AC'% defines the following fi/ed hardware register 0locks. .ach register 0lock gets a separate pointer from
the 5A-T. These addresses are set 0( the 2.M as static resources, so the( are never changedP2!'M
cannot re&map AC'% resources. The following register 0locks are defined<
PM!a%$6T%B-#
PM!0%$6T%B-#
PM" Control Bloc:
PMTimer Bloc:
Processor Bloc:
Register ,ro(pings Register Bloc/s
PM!a%STS
PM!a%$&
PM! $6T 5rouping
PM! C&T 5rouping
PM!a%C&T%B-#
PM!0%C&T%B-#
PM!0%STS
PM!0%$&
PM!a%C&T
PM!0%C&T
PM"%C&T%B-# PM"%C&T
PM%TMR%B-# PM%TMR
P%B-#
P%C&T
P%-6-"
P%-6-(
Registers
5P$1%B-#
5P$!%B-#
5P$1%STS
5P$1%$&
5P$!%STS
5P$!%$&
5eneral Purpose $9ent 1
Bloc:
5eneral Purpose $9ent !
Bloc:
6igure (-- "egister <locks versus "egister ;roupings
The 'M4 .DT grouping consists of the 'M4aC.DT and 'M40C.DT register 0locks, which contain the
fi/ed hardware feature event 0its. .ach event register 0lock =if implemented> contains two registers< a
status register and an ena0le register. .ach register grouping has a defined 0it position that cannot 0e
changedK however, the 0it can 0e implemented in either register 0lock =A or ;>. The A and ; register 0locks
for the events allow chipsets to var( the partitioning of events into two or more chips. 5or read operations,
2!'M will generate a read to the associated A and ; registers, 23 the two values together, and then
operate on this result. 5or write operations, 2!'M will write the value to the associated register in 0oth
register 0locks. Therefore, there are two rules to follow when implementing event registers<
3eserved or unimplemented 0its alwa(s return Hero =control or ena0le>.
Writes to reserved or unimplemented 0its have no affect.
The 'M4 CNT grouping contains the fi/ed hardware feature control 0its and consists of the
'M4aCCNTC;1E and 'M40CCNTC;1E register 0locks. .ach register 0lock is associated with a single
control register. .ach register grouping has a defined 0it position that cannot 0e changedK however, the 0it
can 0e implemented in either register 0lock =A or ;>. There are two rules to follow when implementing
CNT registers<
3eserved or unimplemented 0its alwa(s return Hero =control or ena0le>.
Writes to reserved or unimplemented 0its have no affect.
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9+ Advanced Configuration and 'ower %nterface !pecification
The 'M2CCNTC;1E register 0lock currentl( contains a single 0it for the ar0iter disa0le function. The
general&purpose event register contains the event programming model for generic features. All generic
events, #ust as fi/ed events, generate !C%s. $eneric event status 0its can reside an(whereK however, the top&
level generic event resides in one of the general&purpose register 0locks. An( generic feature event status
not in the general&purpose register space is considered a child or si0ling status 0it, whose parent status 0it is
in the general&purpose event register space. Notice that it is possi0le to have N levels of general&purpose
events prior to hitting the $'. event status.
$eneral&purpose event registers are descri0ed 0( two register 0locks< The $'.C;1E or the $'.4C;1E.
.ach register 0lock is pointed to separatel( from within the 5A-T. .ach register 0lock is further 0roken
into two registers< $'./C!T! and $'./C.N. The status and ena0le registers in the general&purpose event
registers follow the event model for the fi/ed hardware event registers.
5.7.1 ACPI Register Summary
The following ta0les summariHe the AC'% registers<
Ta!le (-& PM+ 1vent "egisters
"egister SiBe ><)tes? Address >relative to register !lock?
'M4aC!T! 'M4C.DTC1.NF2 T'M4aC.DTC;1E )
'M4aC.N 'M4C.DTC1.NF2 T'M4aC.DTC;1E )Z'M4C.DTC1.NF2
'M40C!T! 'M4C.DTC1.NF2 T'M40C.DTC;1E )
'M40C.N 'M4C.DTC1.NF2 T'M40C.DTC;1E )Z'M4C.DTC1.NF2
Ta!le (-# PM+ Control "egisters
"egister SiBe ><)tes? Address >relative to register !lock?
'M4CCNTa 'M4CCNTC1.N T'M4aCCNTC;1E )
'M4CCNT0 'M4CCNTC1.N T'M40CCNTC;1E )
Ta!le (-( PM& Control "egister
"egister SiBe ><)tes? Address >relative to register !lock?
'M2CCNT 'M2CCNTC1.N T'M2CCNTC;1E )
Ta!le (-A PM Ti%er "egister
"egister SiBe ><)tes? Address >relative to register !lock?
'MCTM3 'MCTM3C1.N T'MCTM3C;1E )
Ta!le (-- Processor Control "egisters
"egister SiBe ><)tes? Address >relative to register !lock?
'CCNT " .ither T'C;1E) or specified 0( the 'TC o0#ect =!ee section 8.3.4, C'TC
V'rocessor Throttling ControlW.L>
'C1D12 4 T'C;1E)Z"h
'C1D13 4 T'C;1E)Z*h
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Ta!le (-. ;eneral-Purpose 1vent "egisters
"egister SiBe ><)tes? Address >relative to register !lock?
$'.C!T! $'.C1.NF2 T$'.C;1E)
$'.C.N $'.C1.NF2 T$'.C;1E)Z$'.C1.NF2
$'.4C!T! $'.4C1.NF2 T$'.4C;1E)
$'.4C.N $'.4C1.NF2 T$'.4C;1E)Z$'.4C1.NF2
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5.7.1.1
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PM1 Event Registers
The 'M4 event register grouping contains two register 0locks< the 'M4aC.DTC;1E is a re:uired register
0lock when the following AC'% interface categories are re:uired 0( a class specific platform design guide<
'ower management timer controlFstatus
'rocessor power state controlFstatus
$lo0al 1ock related interfaces
'ower or !leep 0utton =fi/ed register interfaces>
!(stem power state controls =sleepingFwake control>
The 'M40C.DTC;1E is an optional register 0lock. .ach register 0lock has a uni:ue 32&0it pointer in the
5i/ed AC'% Ta0le =5A-T> to allow the 'M4 event 0its to 0e partitioned 0etween two chips. %f the
'M40C.DTC;1E is not supported, its pointer contains a value of Hero in the 5A-T.
.ach register 0lock in the 'M4 event grouping contains two registers that are re:uired to 0e the same siHe<
the 'M4/C!T! and 'M4/C.N =where / can 0e JaL or J0L>. The length of the registers is varia0le and is
descri0ed 0( the 'M4C.DTC1.N field in the 5A-T, which indicates the total length of the register 0lock
in 0(tes. @ence if a length of J"L is given, this indicates that each register contains two 0(tes of %F2 space.
The 'M4 event register 0lock has a minimum siHe of " 0(tes.
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5.7.1.2
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PM1 Control Registers
The 'M4 control register grouping contains two register 0locks< the 'M4aCCNTC;1E is a re:uired
register 0lock when the following AC'% interface categories are re:uired 0( a class specific platform design
guide<
!C%F!M% routing controlFstatus for power management and general&purpose events
'rocessor power state controlFstatus
$lo0al 1ock related interfaces
!(stem power state controls =sleepingFwake control>
The 'M40CCNTC;1E is an optional register 0lock. .ach register 0lock has a uni:ue 32&0it pointer in the
5i/ed AC'% Ta0le =5A-T> to allow the 'M4 event 0its to 0e partitioned 0etween two chips. %f the
'M40CCNTC;1E is not supported, its pointer contains a value of Hero in the 5A-T.
.ach register 0lock in the 'M4 control grouping contains a single register< the 'M4/CCNT. The length of
the register is varia0le and is descri0ed 0( the 'M4CCNTC1.N field in the 5A-T, which indicates the total
length of the register 0lock in 0(tes. The 'M4 control register 0lock must have a minimum siHe of 2 0(tes.
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5.7.1.3
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PM2 Control Register
The 'M2 control register is contained in the 'M2CCNTC;1E register 0lock. The 5A-T contains a length
varia0le for this register 0lock ='M2CCNTC1.N> that is e:ual to the siHe in 0(tes of the 'M2CCNT register
=the onl( register in this register 0lock>. This register 0lock is optional, if not supported its 0lock pointer
and length contain a value of Hero.
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5.7.1.4
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PM Timer Register
The 'M timer register is contained in the 'MCTM3C;1E register 0lock, which is a re:uired register 0lock
when the power management timer controlFstatus AC'% interface categor( is re:uired 0( a class specific
platform design guide.
This register 0lock contains the register that returns the running value of the power management timer. The
5A-T also contains a length varia0le for this register 0lock ='MCTM3C1.N> that is e:ual to the siHe in
0(tes of the 'MCTM3 register =the onl( register in this register 0lock>.
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5.7.1.5
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Processor Control Block (P_BLK)
There is an optional processor control register 0lock for each processor in the s(stem. As this is a
homogeneous feature, all processors must have the same level of support. The AC'% 2! will revert to the
lowest common denominator of processor control 0lock support. The processor control 0lock contains the
processor control register ='CCNT&a 32&0it performance control configuration register>, and the 'C1D12
and 'C1D13 C', sleep state control registers. The 32&0it 'CCNT register controls the 0ehavior of the
processor clock logic for that processor, the 'C1D12 register is used to place the C', into the C2 state, and
the 'C1D13 register is used to place the processor into the C3 state.
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5.7.1.6
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General-Purpose Event Registers
The general&purpose event registers contain the root level events for all generic features. To facilitate the
fle/i0ilit( of partitioning the root events, AC'% provides for two different general&purpose event 0locks<
$'.C;1E and $'.4C;1E. These are separate register 0locks and are not a register grouping, 0ecause
there is no need to maintain an orthogonal 0it arrangement. Also, each register 0lock contains its own
length varia0le in the 5A-T, where $'.C1.N and $'.4C1.N represent the length in 0(tes of each
register 0lock.
.ach register 0lock contains two registers of e:ual length< $'./C!T! and $'./C.N =where / is or 4>.
The length of the $'.C!T! and $'.C.N registers is e:ual to half the $'.C1.N. The length of the
$'.4C!T! and $'.4C.N registers is e:ual to half the $'.4C1.N. %f a generic register 0lock is not
supported then its respective 0lock pointer and 0lock length values in the 5A-T ta0le contain Heros. The
$'.C1.N and $'.4C1.N do not need to 0e the same siHe.
5.7.2 Fixed Hardware Features
This section descri0es the fi/ed hardware features defined 0( AC'%.
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5.7.2.1
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Power Management Timer
The AC'% specification re:uires a power management timer that provides an accurate time value used 0(
s(stem software to measure and profile s(stem idleness =along with other tasks>. The power management
timer provides an accurate time function while the s(stem is in the working =$> state. To allow software to
e/tend the num0er of 0its in the timer, the power management timer generates an interrupt when the last 0it
of the timer changes =from to 4 or 4 to >. AC'% supports either a 2"&0it or 32&0it power management
timer. The 'M Timer is accessed directl( 0( 2!'M, and its programming model is contained in fi/ed
register space. The programming model can 0e partitioned in up to three different register 0locks. The event
0its are contained in the 'M4C.DT register grouping, which has two register 0locks, and the timer value
can 0e accessed through the 'MCTM3C;1E register 0lock. A 0lock diagram of the power management
timer is illustrated in the following figure<
PMTMR%PM$
TMR%$&
PM!x%$&41
(4;<=;>; M7?
// ">/("
TMR%6A-
PM%TMR41/"(/1/(!
TMR%STS
PM!x%STS41
">/("/0it
Counter
Bits)"(/(!/1+
6igure (-. Power Manage%ent Ti%er
The power management timer is a 2"&0it or 32&0it fi/ed rate free running count&up timer that runs off a
3.*96*"* M@H clock. The AC'% 2! checks the 5A-T to determine whether the 'M Timer is a 32&0it or 2"&
0it timer. The programming model for the 'M Timer consists of event logic, and a read port to the counter
value. The event logic consists of an event status and ena0le 0it. The status 0it is set an( time the last 0it of
the timer =0it 23 or 0it 34> goes from set to clear or clear to set. %f the TM3C.N 0it is set, then the setting of
the TM3C!T! will generate an AC'% event in the 'M4C.DT register grouping =referred to as
'MTM3C'M. in the diagram>. The event logic is onl( used to emulate a larger timer.
2!'M uses the read&onl( TM3CDA1 field =in the 'M TM3 register grouping> to read the current value of
the timer. 2!'M never assumes an initial value of the TM3CDA1 fieldK instead, it reads an initial
TM3CDA1 upon loading 2!'M and assumes that the timer is counting. %t is allowa0le to stop the Timer
when the s(stem transitions out of the working =$F!> state. The onl( timer reset re:uirement is that the
timer functions while in the working state.
The 'M TimerMs programming model is implemented as a fi/ed hardware feature to increase the accurac(
of reading the timer.
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5.7.2.2
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Console Buttons
AC'% defines user&initiated events to re:uest 2!'M to transition the platform 0etween the $ working
state and the $4 sleeping, $2 soft off and $3 mechanical off states. AC'% also defines a recommended
mechanism to unconditionall( transition the platform from a hung $ working state to the $2 soft&off state.
AC'% operating s(stems use power 0utton events to determine when the user is present. As such, these
AC'% events are associated with 0uttons in the AC'% specification.
The AC'% specification supports two 0utton models<
A single&0utton model that generates an event for 0oth sleeping and entering the soft&off state. The
function of the 0utton can 0e configured using 2!'M ,%.
A dual&0utton model where the power 0utton generates a soft&off transition re:uest and a sleeping
0utton generates a sleeping transition re:uest. The t(pe of 0utton implies the function of the 0utton.
Control of these 0utton events is either through the fi/ed hardware programming model or the generic
hardware programming model =control method 0ased>. The fi/ed hardware programming model has the
advantage that 2!'M can access the 0utton at an( time, including when the s(stem is crashed. %n a crashed
s(stem with a fi/ed hardware power 0utton, 2!'M can make a J0estL effort to determine whether the
power 0utton has 0een pressed to transition to the s(stem to the soft&off state, 0ecause it doesnMt re:uire the
AM1 interpreter to access the event 0its.
5.7.2.2.1 Power Button
The power 0utton logic can 0e used in one of two models< single 0utton or dual 0utton. %n the single&0utton
model, the user 0utton acts as 0oth a power 0utton for transitioning the s(stem 0etween the $ and $2
states and a sleeping 0utton for transitioning the s(stem 0etween the $ and $4 states. The action of the
user pressing the 0utton is determined 0( software polic( or user settings. %n the dual&0utton model, there
are separate 0uttons for sleeping and power control. Although the 0uttons still generate events that cause
software to take an action, the function of the 0utton is now dedicated< the sleeping 0utton generates a
sleeping re:uest to 2!'M and the power 0utton generates a waking re:uest.
!upport for a power 0utton is indicated 0( a com0ination of the 'W3C;,TT2N flag and the power 0utton
device o0#ect, as shown in the following<
Ta!le (-/ Power <utton Support
Indicated Support P:"D<2TT30 6lag Power <utton 5evice 3!Cect
5i/ed hardware power 0utton Clear A0sent
Control method power 0utton !et 'resent
The power 0utton can also have an additional capa0ilit( to unconditionall( transition the s(stem from a
hung working state to the $2 soft&off state. %n the case where 2!'M event handler is no longer a0le to
respond to power 0utton events, the power 0utton override feature provides a 0ack&up mechanism to
unconditionall( transition the s(stem to the soft&off state. This feature can 0e used when the platform
doesnMt have a mechanical off 0utton, which can also provide this function. AC'% defines that holding the
power 0utton active for four seconds or longer will generate a power 0utton override event.
5.7.2.2.1.1 Fixed Power Button
PRBT&8
PRBT&%$&
PM!x%$&4@
PRBT&%STS
PM!x%STS4@
'e0ounce
-ogic
PRBT&$9ent
PRBT&
O9er/ride
PRBT&
Statemachine
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6igure (-/ 6ixed Power <utton Logic
The fi/ed hardware power 0utton has its event programming model in the 'M4/C.DTC;1E. This logic
consists of a single ena0le 0it and stick( status 0it. When the user presses the power 0utton, the power
0utton status 0it ='W3;TNC!T!> is unconditionall( set. %f the power 0utton ena0le 0it ='W3;TNC.N> is
set and the power 0utton status 0it is set ='W3;TNC!T!> due to a 0utton press while the s(stem is in the
$ state, then an !C% is generated. 2!'M responds to the event 0( clearing the 'W3;TNC!T! 0it. The
power 0utton logic provides de0ounce logic that sets the 'W3;TNC!T! 0it on the 0utton press Jedge.L
While the s(stem is in the $4 or $2 glo0al states =!4, !2, !3, !" or !* states>, an( further power 0utton
press after the 0utton press that transitioned the s(stem into the sleeping state unconditionall( sets the
power 0utton status 0it and wakes the s(stem, regardless of the value of the power 0utton ena0le 0it. 2!'M
responds 0( clearing the power 0utton status 0it and waking the s(stem.
5.7.2.2.1.2 Control Method Power Button
The power 0utton programming model can also use the generic hardware programming model. This allows
the power 0utton to reside in an( of the generic hardware address spaces =for e/ample, the em0edded
controller> instead of fi/ed space. %f the power 0utton is implemented using generic hardware, then the
2.M needs to define the power 0utton as a device with an C@%- o0#ect value of J'N'CC,L which then
identifies this device as the power 0utton to 2!'M. The AM1 event handler then generates a Notif(
command to notif( 2!'M that a power 0utton event was generated. While the s(stem is in the working
state, a power 0utton press is a user re:uest to transition the s(stem into either the sleeping =$4> or soft&off
state =$2>. %n these cases, the power 0utton event handler issues the Notif( command with the device
specific code of /8. This indicates to 2!'M to pass control to the power 0utton driver ='N'CC> with
the knowledge that a transition out of the $ state is 0eing re:uested. ,pon waking from a $4 sleeping
state, the AM1 event handler generates a notif( command with the code of /2 to indicate it was
responsi0le for waking the s(stem.
The power 0utton device needs to 0e declared as a device within the AC'% Namespace for the platform and
onl( re:uires an C@%-. An e/ample definition follows.
This e/ample A!1 code performs the following<
Creates a device named J'W3;L and associates the 'lug and 'la( identifier =through the C@%-
o0#ect> of J'N'CC.L
The 'lug and 'la( identifier associates this device o0#ect with the power 0utton driver.
Creates an operational region for the control method power 0uttonMs programming model< !(stem
%F2 space at /2.
5ields that are not accessed are written as Heros. These status 0its clear upon writing a 4 to their 0it
position, therefore preserved would fail in this case.
Creates a field within the operational region for the power 0utton status 0it =called ';'>. %n this
case the power 0utton status 0it is a child of the general&purpose event status 0it . When this 0it is
set, it is the responsi0ilit( of the A!1&code to clear it =2!'M clears the general&purpose status
0its>. The address of the status 0it is /2. =0it at address /2>.
Creates an additional status 0it called ';W for the power 0utton wake event. This is the ne/t 0it
and its ph(sical address would 0e /2.4 =0it 4 at address /2>.
$enerates an event handler for the power 0utton that is connected to 0it of the general&purpose
event status register . The event handler does the following<
Clears the power 0utton status 0it in hardware =writes a one to it>.
Notifies 2!'M of the event 0( calling the Notif( command passing the power 0utton o0#ect and
the device specific event indicator /8.
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// Define a control method power button
Device(\_SB.PWRB)
!ame(_"#D$ %#S&#D('P!P()()*))
!ame(_PRW$ Pac+a,e()($ (-./)
0perationRe,ion(\P"0$ S12tem#0$ (-3(($ (-4)
5ield(\P"0$ B1te&cc$ !o6oc+$ Write&27ero2)
PBP$ 4$ // 2leep/off re8ue2t
PBW$ 4 // wa+eup re8ue2t
/
/ // end of power button device ob9ect
Scope(\_:P%) // Root level event handler2
;ethod(_6(() // u2e2 bit ( of :P(_S<S re,i2ter
#f(\PBP)
Store(0ne$ \PBP) // clear power button 2tatu2
!otif1(\_SB.PWRB$ (-=() // !otif1 0S of event
/
#f(\PBW)
Store(0ne$ \PBW)
!otif1(\_SB.PWRB$ (-3)
/
/ // end of _6(( handler
/ // end of \_:P% 2cope
5.7.2.2.1.3 Power Button Override
The AC'% specification also allows that if the user presses the power 0utton for more than four seconds
while the s(stem is in the working state, a hardware event is generated and the s(stem will transition to the
soft&off state. This hardware event is called a power 0utton override. %n reaction to the power 0utton
override event, the hardware clears the power 0utton status 0it ='W3;TNC!T!>.
5.7.2.2.2 Sleep Button
When using the two 0utton model, AC'% supports a second 0utton that when pressed will re:uest 2!'M to
transition the platform 0etween the $ working and $4 sleeping states. !upport for a sleep 0utton is
indicated 0( a com0ination of the !1..'C;,TT2N flag and the sleep 0utton device o0#ect<
Ta!le (-, Sleep <utton Support
Indicated Support SL11PD<2TT30 6lag Sleep <utton 5evice 3!Cect
No sleep 0utton !et A0sent
5i/ed hardware sleep 0utton Clear A0sent
Control method sleep 0utton !et 'resent
5.7.2.2.2.1 Fixed Hardware Sleeping Button
S-PBT&8
S-PBT&%$&
PM!x%$&4=
S-PBT&%STS
PM!x%STS4=
'e0ounce
-ogic
S-PBT& $9ent
S-PBT&
State machine
6igure (-, 6ixed Hardware Sleep <utton Logic
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The fi/ed hardware sleep 0utton has its event programming model in the 'M4/C.DTC;1E. This logic
consists of a single ena0le 0it and stick( status 0it. When the user presses the sleep 0utton, the sleep 0utton
status 0it =!1';TNC!T!> is unconditionall( set. Additionall(, if the sleep 0utton ena0le 0it =!1';TNC.N>
is set, and the sleep 0utton status 0it is set =!1';TNC!T!, due to a 0utton press> while the s(stem is in the
$ state, then an !C% is generated. 2!'M responds to the event 0( clearing the !1';TNC!T! 0it. The
sleep 0utton logic provides de0ounce logic that sets the !1';TNC!T! 0it on the 0utton press Jedge.L
While the s(stem is sleeping =in either the !, !4, !2, !3 or !" states>, an( further sleep 0utton press =after
the 0utton press that caused the s(stem transition into the sleeping state> sets the sleep 0utton status 0it
=!1';TNC!T!> and wakes the s(stem if the !1'C.N 0it is set. 2!'M responds 0( clearing the sleep
0utton status 0it and waking the s(stem.
5.7.2.2.2.2 Control Method Sleeping Button
The sleep 0utton programming model can also use the generic hardware programming model. This allows
the sleep 0utton to reside in an( of the generic hardware address spaces =for e/ample, the em0edded
controller> instead of fi/ed space. %f the sleep 0utton is implemented via generic hardware, then the 2.M
needs to define the sleep 0utton as a device with an C@%- o0#ect value of J'N'C.L, which then
identifies this device as the sleep 0utton to 2!'M. The AM1 event handler then generates a Notif(
command to notif( 2!'M that a sleep 0utton event was generated. While in the working state, a sleep
0utton press is a user re:uest to transition the s(stem into the sleeping =$4> state. %n these cases the sleep
0utton event handler issues the Notif( command with the device specific code of /8. This will indicate to
2!'M to pass control to the sleep 0utton driver ='N'C.> with the knowledge that the user is re:uesting
a transition out of the $ state. ,pon waking&up from a $4 sleeping state, the AM1 event handler generates
a Notif( command with the code of /2 to indicate it was responsi0le for waking the s(stem.
The sleep 0utton device needs to 0e declared as a device within the AC'% Namespace for the platform and
onl( re:uires an C@%-. An e/ample definition is shown 0elow.
The AM1 code 0elow does the following<
Creates a device named J!1';L and associates the 'lug and 'la( identifier =through the C@%-
o0#ect> of J'N'C..L
The 'lug and 'la( identifier associates this device o0#ect with the sleep 0utton driver.
Creates an operational region for the control method sleep 0uttonMs programming model< !(stem
%F2 space at /24.
5ields that are not accessed are written as J4sL =these status 0its clear upon writing a J4L to their
0it position, hence preserved would fail in this case>.
Creates a field within the operational region for the sleep 0utton status 0it =called ';'>. %n this
case the sleep 0utton status 0it is a child of the general&purpose status 0it . When this 0it is set it
is the responsi0ilit( of the AM1 code to clear it =2!'M clears the general&purpose status 0its>. The
address of the status 0it is /24. =0it at address /24>.
Creates an additional status 0it called ';W for the sleep 0utton wake event. This is the ne/t 0it
and its ph(sical address would 0e /24.4 =0it 4 at address /24>.
$enerates an event handler for the sleep 0utton that is connected to 0it of the general&purpose
status register . The event handler does the following<
Clears the sleep 0utton status 0it in hardware =writes a J4L to it>.
Notifies 2!'M of the event 0( calling the Notif( command passing the sleep 0utton o0#ect and
the device specific event indicator /8.
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// Define a control method 2leep button
Device(\_SB.S6PB)
!ame(_"#D$ %#S&#D('P!P()(%*))
!ame(_PRW$ Pac+a,e()(-(4$ (-(./)
0perationRe,ion(\Boo$ S12tem#0$ (-3(4$ (-4)
5ield(\Boo$ B1te&cc$ !o6oc+$ Write&27ero2)
SBP$ 4$ // 2leep re8ue2t
SBW$ 4 // wa+eup re8ue2t
/ // end of field definition
/
Scope(\_:P%) // Root level event handler2
;ethod(_6(4) // u2e2 bit 4 of :P(_S<S re,i2ter
#f(\SBP)
Store(0ne$ \SBP) // clear 2leep button 2tatu2
!otif1(\_SB.S6PB$ (-=() // !otif1 0S of event
/
#f(\SBW)
Store(0ne$ \SBW)
!otif1(\_SB.S6PB$ (-3)
/
/ // end of _6(4 handler
/ // end of \_:P% 2cope
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68 Advanced Configuration and 'ower %nterface !pecification
5.7.2.3
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5.7.2.3
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4 Advanced Configuration and 'ower %nterface !pecification
Sleeping/Wake Control
The sleepingFwake logic consists of logic that will se:uence the s(stem into the defined low&power
hardware sleeping state =!4&!"> or soft&off state =!*> and will wake the s(stem 0ack to the working state
upon a wake event. Notice that the !";%2! state is entered in a different manner =for more information, see
section 4*.4.".2, JThe !";%2! TransitionL>.
S-P%$&
PM!x%C&T4S>4!(
A#%STS
PM!x%STS4S14!;
Sleeping
S-P%TAP2(
PM!x%C&T4S>4B!1/!"C
.a/e(p$
Sleep
+ogic
DORD or all
a:e
$9ents
PRBT&%OR
6igure (-+$ Sleeping@:ake Logic
The logic is controlled via two 0it fields< !leep .na0le =!1'C.N> and !leep T(pe =!1'CTS'/>. The t(pe
of sleep state desired is programmed into the !1'CTS'/ field and upon assertion of the !1'C.N the
hardware will se:uence the s(stem into the defined sleeping state. 2!'M gets values for the !1'CTS'/
field from the BC!x o0#ects defined in the static definition 0lock. %f the o0#ect is missing 2!'M assumes the
hardware does not support that sleeping state. 'rior to entering the desired sleeping state, 2!'M will read
the designated BC!x o0#ect and place this value in the !1'CTS' field.
Additionall( AC'% defines a fail&safe 2ff protocol called the Jpower 0utton override,L which allows the
user to initiate an 2ff se:uence in the case where the s(stem software is no longer a0le to recover the
s(stem =the s(stem has hung>. AC'% defines that this se:uence 0e initiated 0( the user pressing the power
0utton for over " seconds, at which point the hardware unconditionall( se:uences the s(stem to the 2ff
state. This logic is represented 0( the 'W3;TNC23 signal coming into the sleep logic.
While in an( of the sleeping states =$4>, an ena0led JWakeL event will cause the hardware to se:uence the
s(stem 0ack to the working state =$>. The JWake !tatusL 0it =WAEC!T!> is provided for 2!'M to Jspin&
onL after setting the !1'C.NF!1'CTS' 0it fields. When waking from the !4 sleeping state, e/ecution
control is passed 0acked to 2!'M immediatel(, whereas when waking from the !2&!* states e/ecution
control is passed to the ;%2! software =e/ecution 0egins at the C',Ms reset vector>. The WAEC!T! 0it
provides a mechanism to separate 2!'MMs sleeping and waking code during an !4 se:uence. When the
hardware has se:uenced the s(stem into the sleeping state =defined here as the processor is no longer a0le
to e/ecute instructions>, an( ena0led wake event is allowed to set the WAEC!T! 0it and se:uence the
s(stem 0ack on =to the $ state>. %f the s(stem does not support the !4 sleeping state, the WAEC!T! 0it
can alwa(s return Hero.
&%f more than a single sleeping state is supported, then the sleepingFwake logic is re:uired to 0e a0le to
d(namicall( se:uence 0etween the different sleeping states. This is accomplished 0( waking the s(stemK
2!'M programs the new sleep state into the !1'CTS' field, and then sets the !1'C.N 0itIplacing the
s(stem again in the sleeping state.
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5.7.2.4
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5.7.2.4
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Real Time Clock Alarm
%f implemented, the 3eal Time Clock =3TC> alarm must generate a hardware wake event when in the
sleeping state. The 3TC can 0e programmed to generate an alarm. An ena0led 3TC alarm can 0e used to
generate a wake event when the s(stem is in a sleeping state. AC'% provides for additional hardware to
support 2!'M in determining that the 3TC was the source of the wake event< the 3TCC!T! and 3TCC.N
0its. Although these 0its are optional, if supported the( must 0e implemented as descri0ed here.
%f the 3TCC!T! and 3TCC.N 0its are not supported, 2!'M will attempt to identif( the 3TC as a possi0le
wake sourceK however, it might miss certain wake events. %f implemented, the 3TC wake feature is re:uired
to work in the following sleeping states< !4&!3. !" wake is optional and supported through the 3TCC!"
flag within the 5A-T =if set, then the platform supports 3TC wake in the !" state>
3
.
When the 3TC generates a wake event the 3TCC!T! 0it will 0e set. %f the 3TCC.N 0it is set, an 3TC
hardware power management event will 0e generated =which will wake the s(stem from a sleeping state,
provided the 0atter( low signal is not asserted>.
Real Time Cloc:
)RTC+
RTCa:e/up
$9ent
RTC%$&
PM!x%$&4!1
RTC%STS
PM!x%STS4!1
6igure (-++ "TC Alar%
The 3TC wake event status and ena0le 0its are an optional fi/ed hardware feature and a flag within the
5A-T =5%AC3TC> indicates if the register 0its are to 0e used 0( 2!'M. %f the 3TC wake event status and
ena0le 0its are implemented in fi/ed hardware, 2!'M can determine if the 3TC was the source of the wake
event without loading the entire 2!. This also gives the platform the capa0ilit( of indicating an 3TC wake
source without consuming a $'. 0it, as would 0e re:uired if 3TC wake was not implemented using the
fi/ed hardware 3TC feature. %f the fi/ed hardware feature event 0its are not supported, then 2!'M will
attempt to determine this 0( reading the 3TCMs status field. %f the platform implements the 3TC fi/ed
hardware feature, and this hardware consumes resources, the C5%A method can 0e used to correlate these
resources with the fi/ed hardware. !ee section +.2.", JC5%A =5i/ed 3egister 3esource 'rovideL, for details.
2!'M supports enhancements over the e/isting 3TC device =which onl( supports a 66 (ear date and 2"&
hour alarm>. 2ptional e/tensions are provided for the following features<
5a) Alar%. The -ASCA13M field points to an optional CM2! 3AM location that selects the
da( within the month to generate an 3TC alarm.
Month Alar%. The M2NCA13M field points to an optional CM2! 3AM location that selects
the month within the (ear to generate an 3TC alarm.
Centenar) 7alue. The C.NT field points to an optional CM2! 3AM location that represents the
centenar( value of the date =thousands and hundreds of (ears>.
The 3TCC!T! 0it ma( 0e set through the 3TC interrupt =%3G8 in %A&'C architecture s(stems>. 2!'M will
insure that the periodic and update interrupt sources are disa0led prior to sleeping. This allows the 3TCMs
interrupt pin to serve as the source for the 3TCC!T! 0it generation. Note however that if the 3TC interrupt
pin is used for 3TCC!T! generation, the 3TCC!T! 0it value ma( not 0e accurate when waking from !". %f
this value is accurate when waking from !", the platform should set the !"C3TCC!T!CDA1%- flag, so that
2!'M can utiliHe the 3TCC!T! information.
3
Notice that the $2F!* Jsoft offL and the $3 Jmechanical offL states are not sleeping states. The 2! will
disa0le the 3TCC.N 0it prior to entering the $2F!* or $3 states regardless.
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4" Advanced Configuration and 'ower %nterface !pecification
Ta!le (-+$ Alar% 6ield 5ecodings within the 6A5T
6ield 7alue
Address >Location? in "TC CM3S
"AM >Must !e <ank $?
-ASCA13M .ight 0it value that can represent /4&/34
da(s in ;C- or /4&/45 da(s in 0inar(.
;its + and 9 of this field are treated as
%gnored 0( software. The 3TC is initialiHed
such that this field contains a JdonMt careL
value when the ;%2! switches from legac(
to AC'% mode. A donMt care value can 0e an(
unused value =not /4&/34 ;C- or /4&
/45 he/> that the 3TC reverts 0ack to a 2"
hour alarm.
The -ASCA13M field in the 5A-T will
contain a non&Hero value that represents
an offset into the 3TCMs CM2! 3AM
area that contains the da( alarm value. A
value of Hero in the -ASCA13M field
indicates that the da( alarm feature is not
supported.
M2NCA13M .ight 0it value that can represent 4&42
months in ;C- or /4&/C months in
0inar(. The 3TC is initialiHed such that this
field contains a donMt care value when the
;%2! switches from legac( to AC'% mode. A
JdonMt careL value can 0e an( unused value
=not 4&42 ;C- or /4&/C he/> that the 3TC
reverts 0ack to a 2" hour alarm andFor 34 da(
alarm>.
The M2NCA13M field in the 5A-T
will contain a non&Hero value that
represents an offset into the 3TCMs
CM2! 3AM area that contains the
month alarm value. A value of Hero in
the M2NCA13M field indicates that the
month alarm feature is not supported. %f
the month alarm is supported, the da(
alarm function must also 0e supported.
C.NT,3S 8&0it ;C- or 0inar( value. This value
indicates the thousand (ear and hundred (ear
=Centenar(> varia0les of the date in ;C- =46
for this centur(, 2 for the ne/t> or 0inar(
=/43 for this centur(, /4" for the ne/t>.
The C.NT,3S field in the 5A-T will
contain a non&Hero value that represents
an offset into the 3TCMs CM2! 3AM
area that contains the Centenar( value
for the date. A value of Hero in the
C.NT,3S field indicates that the
Centenar( value is not supported 0( this
3TC.
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5.7.2.5
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5.7.2.5
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Legacy/ACPI Select and the SCI Interrupt
As mentioned previousl(, power management events are generated to initiate an interrupt or hardware
se:uence. AC'% operating s(stems use the !C% interrupt handler to respond to events, while legac( s(stems
use some t(pe of transparent interrupt handler to respond to these events =that is, an !M% interrupt handler>.
AC'%&compati0le hardware can choose to support 0oth legac( and AC'% modes or #ust an AC'% mode.
1egac( hardware is needed to support these features for non&AC'%&compati0le operating s(stems. When
the AC'% 2! loads, it scans the ;%2! ta0les to determine that the hardware supports AC'%, and then if the
it finds the !C%C.N 0it reset =indicating that AC'% is not ena0led>, issues an AC'% activate command to the
!M% handler through the !M% command port. The ;%2! acknowledges the switching to the AC'% model of
power management 0( setting the !C%C.N 0it =this 0it can also 0e used to switch over the event mechanism
as illustrated 0elow><
'ec
1
!
Power
Management
$9ent -ogic
SCI%$&
PM!x%C&T41
SMI%$6&T
SCI%$6&T
Sharea0le
Interrupt
6igure (-+& Power Manage%ent 1vents to SMI@SCI Control Logic
The interrupt events =those that generate !M%s in legac( mode and !C%s in AC'% mode> are sent through a
decoder controlled 0( the !C%C.N 0it. 5or legac( mode this 0it is reset, which routes the interrupt events to
the !M% interrupt logic. 5or AC'% mode this 0it is set, which routes interrupt events to the !C% interrupt
logic. This 0it alwa(s returns set for AC'%&compati0le hardware that does not support a legac( power
management mode =in other words, the 0it is wired to read as J4L and ignore writes>.
The !C% interrupt is defined to 0e a sharea0le interrupt and is connected to an 2! visi0le interrupt that uses
a sharea0le protocol. The 5A-T has an entr( that indicates what interrupt the !C% interrupt is mapped to
=see section *.2.+, J!(stem -escription Ta0le @eaderL>.
%f the AC'% platform supports 0oth legac( and AC'% modes, it has a register that generates a hardware
event =for e/ample, !M% for %A&'C processors>. 2!'M uses this register to make the hardware switch in
and out of AC'% mode. Within the 5A-T are three values that signif( the address =!M%CCM-> of this port
and the data value written to ena0le the AC'% state =AC'%C.NA;1.>, and to disa0le the AC'% state
=AC'%C-%!A;1.>.
To transition an AC'%F1egac( platform from the 1egac( mode to the AC'% mode the following would
occur<
AC'% driver checks that the !C%C.N 0it is Hero, and that it is in the 1egac( mode.
2!'M does an 2,T to the !M%CCM- port with the data in the AC'%C.NA;1. field of the
5A-T.
2!'M polls the !C%C.N 0it until it is sampled as !.T.
To transition an AC'%F1egac( platform from the AC'% mode to the 1egac( mode the following would
occur<
AC'% driver checks that the !C%C.N 0it is one, and that it is in the AC'% mode.
2!'M does an 2,T to the !M%CCM- port with the data in the AC'%C-%!A;1. field of the
5A-T.
2!'M polls the !C%C.N 0it until it is sampled as 3.!.T.
'latforms that onl( support AC'% alwa(s return a 4 for the !C%C.N 0it. %n this case 2!'M skips the
1egac( to AC'% transition stated a0ove.
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48 Advanced Configuration and 'ower %nterface !pecification
5.7.2.6
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5.7.2.6
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44 Advanced Configuration and 'ower %nterface !pecification
Processor Control
The AC'% specification defines several processor controls including power state control, throttling control,
and performance state control. !ee !ection 8, J'rocessor 'ower and 'erformance !tate Configuration and
Control,L for a complete description of the processor controls.
5.7.3 Fixed Hardware Registers
The fi/ed hardware registers are manipulated directl( 0( 2!'M. The following sections descri0e fi/ed
hardware features under the programming model. 2!'M owns all the fi/ed hardware resource registersK
these registers cannot 0e manipulated 0( AM1 code. 3egisters are accessed with an( width up to its register
width =0(te granular>.
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5.7.3.1
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442 Advanced Configuration and 'ower %nterface !pecification
PM1 Event Grouping
The 'M4 .vent $rouping has a set of 0its that can 0e distri0uted 0etween two different register 0locks.
This allows these registers to 0e partitioned 0etween two chips, or all placed in a single chip. Although the
0its can 0e split 0etween the two register 0locks =each register 0lock has a uni:ue pointer within the
5A-T>, the 0it positions are maintained. The register 0lock with unimplemented 0its =that is, those
implemented in the other register 0lock> alwa(s returns Heros, and writes have no side effects.
5.7.3.1.1 PM1 Status Registers
Re,i2ter 6ocation> ?P;4a_%@<_B6A / P;4b_%@<_B6AB S12tem #/0 or ;emor1 Space
Default @alue> ((h
&ttribute> Read/Write
SiCe> P;4_%@<_6%! / 3
The 'M4 status registers contain the fi/ed hardware feature status 0its. The 0its can 0e split 0etween two
registers< 'M4aC!T! or 'M40C!T!. .ach register grouping can 0e at a different 32&0it aligned address and
is pointed to 0( the 'M4aC.DTC;1E or 'M40C.DTC;1E. The values for these pointers to the register
space are found in the 5A-T. Accesses to the 'M4 status registers are done through 0(te or word accesses.
5or AC'%Flegac( s(stems, when transitioning from the legac( to the $ working state this register is
cleared 0( ;%2! prior to setting the !C%C.N 0it =and thus passing control to 2!'M>. 5or AC'% onl(
platforms =where !C%C.N is alwa(s set>, when transitioning from either the mechanical off =$3> or soft&off
state to the $ working state this register is cleared prior to entering the $ working state.
This register contains optional features ena0led or disa0led within the 5A-T. %f the 5A-T indicates that the
feature is not supported as a fi/ed hardware feature, then software treats these 0its as ignored.
Ta!le (-++ PM+ Status "egisters 6ixed Hardware 6eature Status <its
<it 0a%e 5escription
TM3C!T! This is the timer carr( status 0it. This 0it gets set an( time the 23
rd
F34
st

0it of a 2"F32&0it counter changes =whenever the M!; changes from
clear to set or set to clear. While TM3C.N and TM3C!T! are set, an
interrupt event is raised.
4&3 3eserved 3eserved
" ;MC!T! This is the 0us master status 0it. This 0it is set an( time a s(stem 0us
master re:uests the s(stem 0us, and can onl( 0e cleared 0( writing a J4L
to this 0it position. Notice that this 0it reflects 0us master activit(, not
C', activit( =this 0it monitors an( 0us master that can cause an
incoherent cache for a processor in the C3 state when the 0us master
performs a memor( transaction>.
Ta!le (-++ PM+ Status "egisters 6ixed Hardware 6eature Status <its (continued)
<it 0a%e 5escription
* $;1C!T! This 0it is set when an !C% is generated due to the ;%2! wanting the
attention of the !C% handler. ;%2! will have a control 0it =somewhere
within its address space> that will raise an !C% and set this 0it. This 0it is
set in response to the ;%2! releasing control of the $lo0al 1ock and
having seen the pending 0it set.
+&9 3eserved 3eserved. These 0its alwa(s return a value of Hero.
8 'W3;TNC!T! This optional 0it is set when the 'ower ;utton is pressed. %n the s(stem
working state, while 'W3;TNC.N and 'W3;TNC!T! are 0oth set, an
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<it 0a%e 5escription
interrupt event is raised. %n the sleeping or soft&off state, a wake event is
generated when the power 0utton is pressed =regardless of the
'W3;TNC.N 0it setting>. This 0it is onl( set 0( hardware and can onl(
0e reset 0( software writing a J4L to this 0it position.
AC'% defines an optional mechanism for unconditional transitioning a
s(stem that has stopped working from the $ working state into the $2
soft&off state called the power 0utton override. %f the 'ower ;utton is
held active for more than four seconds, this 0it is cleared 0( hardware
and the s(stem transitions into the $2F!* !oft 2ff state
=unconditionall(>.
!upport for the power 0utton is indicated 0( the 'W3C;,TT2N flag in
the 5A-T 0eing reset =Hero>. %f the 'W3C;,TT2N flag is set or a
power 0utton device o0#ect is present in the AC'% Namespace, then this
0it field is ignored 0( 2!'M.
%f the power 0utton was the cause of the wake =from an !4&!" state>,
then this 0it is set prior to returning control to 2!'M.
6 !1';TNC!T! This optional 0it is set when the sleep 0utton is pressed. %n the s(stem
working state, while !1';TNC.N and !1';TNC!T! are 0oth set, an
interrupt event is raised. %n the sleeping or soft&off states a wake event is
generated when the sleeping 0utton is pressed and the !1';TNC.N 0it
is set. This 0it is onl( set 0( hardware and can onl( 0e reset 0( software
writing a J4L to this 0it position.
!upport for the sleep 0utton is indicated 0( the !1'C;,TT2N flag in
the 5A-T 0eing reset =Hero>. %f the !1'C;,TT2N flag is set or a sleep
0utton device o0#ect is present in the AC'% Namespace, then this 0it field
is ignored 0( 2!'M.
%f the sleep 0utton was the cause of the wake =from an !4&!" state>, then
this 0it is set prior to returning control to 2!'M.
Ta!le (-++ PM+ Status "egisters 6ixed Hardware 6eature Status <its (continued)
<it 0a%e 5escription
4 3TCC!T! This optional 0it is set when the 3TC generates an alarm =asserts the 3TC
%3G signal>. Additionall(, if the 3TCC.N 0it is set then the setting of the
3TCC!T! 0it will generate a power management event =an !C%, !M%, or
resume event>. This 0it is onl( set 0( hardware and can onl( 0e reset 0(
software writing a J4L to this 0it position.
%f the 3TC was the cause of the wake =from an !4&!3 state>, then this 0it
is set prior to returning control to 2!'M. %f the 3TCC!" flag within the
5A-T is set, and the 3TC was the cause of the wake from the !" state>,
then this 0it is set prior to returning control to 2!'M.
44 %gnore This 0it field is ignored 0( software.
42&43 3eserved 3eserved. These 0its alwa(s return a value of Hero.
4" 'C%.A'CWAE.C!T!
This 0it is re:uired for chipsets that implement 'C% ./press. This 0it is
set 0( hardware to indicate that the s(stem woke due to a 'C% ./press
wakeup event. A 'C% ./press wakeup event is defined as the 'C%
./press WAE.Y pin 0eing active , one or more of the 'C% ./press ports
0eing in the 0eacon state, or receipt of a 'C% ./press 'M. message at a
root port. This 0it should onl( 0e set when one of these events causes the
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
44" Advanced Configuration and 'ower %nterface !pecification
<it 0a%e 5escription
s(stem to transition from a non&! s(stem power state to the ! s(stem
power state. This 0it is set independent of the state of the
'C%.A'CWAE.C-%! 0it.
!oftware writes a 4 to clear this 0it. %f the WAE.Y pin is still active
during the write, one or more 'C% ./press ports is in the 0eacon state or
the 'M. message received indication has not 0een cleared in the root
port, then the 0it will remain active =i.e. all inputs to this 0it are level&
sensitive>.
Note< This 0it does not itself cause a wake event or prevent entr( to a
sleeping state. Thus if the 0it is 4 and the s(stem is put into a sleeping
state, the s(stem will not automaticall( wake.
4* WAEC!T! This 0it is set when the s(stem is in the sleeping state and an ena0led
wake event occurs. ,pon setting this 0it s(stem will transition to the
working state. This 0it is set 0( hardware and can onl( 0e cleared 0(
software writing a J4L to this 0it position.
5.7.3.1.2 PM1 Enable Registers
Re,i2ter 6ocation> ?P;4a_%@<_B6A / P;4b_%@<_B6AB D P;4_%@<_6%! / 3 S12tem #/0 or
;emor1 Space
Default @alue> ((h
&ttribute> Read/Write
SiCe> P;4_%@<_6%! / 3
The 'M4 ena0le registers contain the fi/ed hardware feature ena0le 0its. The 0its can 0e split 0etween two
registers< 'M4aC.N or 'M40C.N. .ach register grouping can 0e at a different 32&0it aligned address and
is pointed to 0( the 'M4aC.DTC;1E or 'M40C.DTC;1E. The values for these pointers to the register
space are found in the 5A-T. Accesses to the 'M4 .na0le registers are done through 0(te or word
accesses.
5or AC'%Flegac( s(stems, when transitioning from the legac( to the $ working state the ena0les are
cleared 0( ;%2! prior to setting the !C%C.N 0it =and thus passing control to 2!'M>. 5or AC'%&onl(
platforms =where !C%C.N is alwa(s set>, when transitioning from either the mechanical off =$3> or soft&off
state to the $ working state this register is cleared prior to entering the $ working state.
This register contains optional features ena0led or disa0led within the 5A-T. %f the 5A-T indicates that the
feature is not supported as a fi/ed hardware feature, then software treats the ena0le 0its as write as Hero.
Ta!le (-+& PM+ 1na!le "egisters 6ixed Hardware 6eature 1na!le <its
<it 0a%e 5escription
TM3C.N This is the timer carr( interrupt ena0le 0it. When this 0it is set then an
!C% event is generated an(time the TM3C!T! 0it is set. When this 0it
is reset then no interrupt is generated when the TM3C!T! 0it is set.
4&" 3eserved 3eserved. These 0its alwa(s return a value of Hero.
* $;1C.N The glo0al ena0le 0it. When 0oth the $;1C.N 0it and the $;1C!T!
0it are set, an !C% is raised.
+&9 3eserved 3eserved
8 'W3;TNC.N This optional 0it is used to ena0le the setting of the 'W3;TNC!T! 0it
to generate a power management event =!C% or wake>. The
'W3;TNC!T! 0it is set an(time the power 0utton is asserted. The
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<it 0a%e 5escription
ena0le 0it does not have to 0e set to ena0le the setting of the
'W3;TNC!T! 0it 0( the assertion of the power 0utton =see
description of the power 0utton hardware>.
!upport for the power 0utton is indicated 0( the 'W3C;,TT2N flag
in the 5A-T 0eing reset =Hero>. %f the 'W3C;,TT2N flag is set or a
power 0utton device o0#ect is present in the AC'% Namespace, then
this 0it field is ignored 0( 2!'M.
6 !1';TNC.N This optional 0it is used to ena0le the setting of the !1';TNC!T! 0it
to generate a power management event =!C% or wake>. The
!1';TNC!T! 0it is set an(time the sleep 0utton is asserted. The
ena0le 0it does not have to 0e set to ena0le the setting of the
!1';TNC!T! 0it 0( the active assertion of the sleep 0utton =see
description of the sleep 0utton hardware>.
!upport for the sleep 0utton is indicated 0( the !1'C;,TT2N flag in
the 5A-T 0eing reset =Hero>. %f the !1'C;,TT2N flag is set or a sleep
0utton device o0#ect is present in the AC'% Namespace, then this 0it
field is ignored 0( 2!'M.
4 3TCC.N This optional 0it is used to ena0le the setting of the 3TCC!T! 0it to
generate a wake event. The 3TCC!T! 0it is set an( time the 3TC
generates an alarm.
44&43 3eserved 3eserved. These 0its alwa(s return a value of Hero.
4" 'C%.A'CWAE.C-%! This 0it is re:uired for chipsets that implement 'C% ./press. This 0it
disa0les the inputs to the 'C%.A'CWAE.C!T! 0it in the 'M4 !tatus
register from waking the s(stem. Modification of this 0it has no impact
on the value of the 'C%.A'CWAE.C!T! 0it.
4* 3eserved 3eserved. These 0its alwa(s return a value of Hero.
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5.7.3.2
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PM1 Control Grouping
The 'M4 Control $rouping has a set of 0its that can 0e distri0uted 0etween two different registers. This
allows these registers to 0e partitioned 0etween two chips, or all placed in a single chip. Although the 0its
can 0e split 0etween the two register 0locks =each register 0lock has a uni:ue pointer within the 5A-T>, the
0it positions specified here are maintained. The register 0lock with unimplemented 0its =that is, those
implemented in the other register 0lock> returns Heros, and writes have no side effects.
5.7.3.2.1 PM1 Control Registers
Re,i2ter 6ocation> ?P;4a_)!<_B6A / P;4b_)!<_B6AB S12tem #/0 or ;emor1 Space
Default @alue> ((h
&ttribute> Read/Write
SiCe> P;4_)!<_6%!
The 'M4 control registers contain the fi/ed hardware feature control 0its. These 0its can 0e split 0etween
two registers< 'M4aCCNT or 'M40CCNT. .ach register grouping can 0e at a different 32&0it aligned
address and is pointed to 0( the 'M4aCCNTC;1E or 'M40CCNTC;1E. The values for these pointers to
the register space are found in the 5A-T. Accesses to 'M4 control registers are accessed through 0(te and
word accesses.
This register contains optional features ena0led or disa0led within the 5A-T. %f the 5A-T indicates that the
feature is not supported as a fi/ed hardware feature, then software treats these 0its as ignored.
Ta!le (-+# PM+ Control "egisters 6ixed Hardware 6eature Control <its
<it 0a%e 5escription
!C%C.N !elects the power management event to 0e either an !C% or !M% interrupt for
the following events. When this 0it is set, then power management events will
generate an !C% interrupt. When this 0it is reset power management events
will generate an !M% interrupt. %t is the responsi0ilit( of the hardware to set or
reset this 0it. 2!'M alwa(s preserves this 0it position.
4 ;MC31- When set, this 0it allows the generation of a 0us master re:uest to cause an(
processor in the C3 state to transition to the C state. When this 0it is reset,
the generation of a 0us master re:uest does not affect an( processor in the C3
state.
2 $;1C31! This write&onl( 0it is used 0( the AC'% software to raise an event to the ;%2!
software, that is, generates an !M% to pass e/ecution control to the ;%2! for
%A&'C platforms. ;%2! software has a corresponding ena0le and status 0it to
control its a0ilit( to receive AC'% events =for e/ample, ;%2!C.N and
;%2!C!T!>. The $;1C31! 0it is set 0( 2!'M to indicate a release of the
$lo0al 1ock and the setting of the pending 0it in the 5AC! memor( structure.
3&8 3eserved 3eserved. These 0its are reserved 0( 2!'M.
6 %gnore !oftware ignores this 0it field.
4&42 !1'CTS'/ -efines the t(pe of sleeping state the s(stem enters when the !1'C.N 0it is
set to one. This 3&0it field defines the t(pe of hardware sleep state the s(stem
enters when the !1'C.N 0it is set. The BC!x o0#ect contains 3&0it 0inar(
values associated with the respective sleeping state =as descri0ed 0( the
o0#ect>. 2!'M takes the two values from the BC!x o0#ect and programs each
value into the respective !1'CTS'/ field.
43 !1'C.N This is a write&onl( 0it and reads to it alwa(s return a Hero. !etting this 0it
causes the s(stem to se:uence into the sleeping state associated with the
!1'CTS'/ fields programmed with the values from the BC!x o0#ect.
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<it 0a%e 5escription
4"&4* 3eserved 3eserved. This field alwa(s returns Hero.
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5.7.3.3
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42 Advanced Configuration and 'ower %nterface !pecification
5.7.3.3
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Power Management Timer (PM_TMR)
Re,i2ter 6ocation> ?P;_<;R_B6AB S12tem #/0 or ;emor1 Space
Default @alue> ((h
&ttribute> ReadE0nl1
SiCe> F3 bit2
This read&onl( register returns the current value of the power management timer ='M timer>. The 5A-T
has a flag called TM3CDA1C.AT that an 2.M sets to indicate a 32&0it 'M timer or reset to indicate a 2"&
0it 'M timer. When the last 0it of the timer toggles the TM3C!T! 0it is set. This register is accessed as 32
0its.
This register contains optional features ena0led or disa0led within the 5A-T. %f the 5A-T indicates that the
feature is not supported as a fi/ed hardware feature, then software treats these 0its as ignored.
Ta!le (-+( PM Ti%er <its
<it 0a%e 5escription
&23 TM3CDA1 This read&onl( field returns the running count of the power management
timer. This is a 2"&0it counter that runs off a 3.*96*"*&M@H clock and counts
while in the ! working s(stem state. The starting value of the timer is
undefined, thus allowing the timer to 0e reset =or not> 0( an( transition to the
! state from an( other state. The timer is reset =to an( initial value>, and then
continues counting until the s(stemMs 4".34848 M@H clock is stopped upon
entering its !x state. %f the clock is restarted without a reset, then the counter
will continue counting from where it stopped.
2"&34 .CTM3CDA1 This read&onl( field returns the upper eight 0its of a 32&0it power management
timer. %f the hardware supports a 32&0it timer, then this field will return the
upper eight 0itsK if the hardware supports a 2"&0it timer then this field returns
all Heros.
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5.7.3.4
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PM2 Control (PM2_CNT)
Re,i2ter 6ocation> ?P;3_)!<_B6AB S12tem #/0$ S12tem ;emor1$ or
5unctional 5i-ed "ardware Space
Default @alue> ((h
&ttribute> Read/Write
SiCe> P;3_)!<_6%!
This register 0lock is naturall( aligned and accessed 0ased on its length. 5or AC'% 4. this register is 0(te
aligned and accessed as a 0(te.
This register contains optional features ena0led or disa0led within the 5A-T. %f the 5A-T indicates that the
feature is not supported as a fi/ed hardware feature, then software treats these 0its as ignored.
Ta!le (-+A PM& Control "egister <its
<it 0a%e 5escription
A3;C-%! This 0it is used to ena0le and disa0le the s(stem ar0iter. When this 0it is
C1.A3 the s(stem ar0iter is ena0led and the ar0iter can grant the 0us to other
0us masters. When this 0it is !.T the s(stem ar0iter is disa0led and the default
C', has ownership of the s(stem.
2!'M clears this 0it when using the C, C4 and C2 power states.
) 3eserved 3eserved
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42" Advanced Configuration and 'ower %nterface !pecification
5.7.3.5
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5.7.3.5
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42+ Advanced Configuration and 'ower %nterface !pecification
Processor Register Block (P_BLK)
This optional register 0lock is used to control each processor in the s(stem. There is one uni:ue processor
register 0lock per processor in the s(stem. 5or more information a0out controlling processors and control
methods that can 0e used to control processors, see section 8, J'rocessor 'ower and 'erformance !tate
Configuration and Control.L This register 0lock is -W23- aligned and the conte/t of this register 0lock is
not maintained across !3 or !" sleeping states, or the !* soft&off state.
5.7.3.5.1 Processor Control (P_CNT): 32
Re,i2ter 6ocation> %ither ?P_B6AB> S12tem #/0 Space
or 2pecified b1 _P<) 0b9ect> S12tem #/0$ S12tem ;emor1$ or
5unctional 5i-ed "ardware Space
Default @alue> ((h
&ttribute> Read/Write
SiCe> F3 bit2
This register is accessed as a -W23-. The C1ECDA1 field is where the dut( setting of the throttling
hardware is programmed as descri0ed 0( the -,TSCW%-T@ and -,TSC255!.T values in the 5A-T.
!oftware treats all other C1ECDA1 0its as ignored =those not used 0( the dut( setting value>.
Ta!le (-+- Processor Control "egister <its
<it 0a%e 5escription
&3 C1ECDA1 'ossi0le locations for the clock throttling value.
" T@TC.N This 0it ena0les clock throttling of the clock as set in the C1ECDA1 field.
T@TC.N 0it must 0e reset 12W when changing the C1ECDA1 field =changing
the dut( setting>.
*&34 C1ECDA1 'ossi0le locations for the clock throttling value.
5.7.3.5.2 Processor LVL2 Register (P_LVL2): 8
Re,i2ter 6ocation> %ither ?P_B6AB D .> S12tem #/0 Space
or 2pecified b1 _)S< 0b9ect> S12tem #/0$ S12tem ;emor1$ or
5unctional 5i-ed "ardware Space
Default @alue> ((h
&ttribute> ReadE0nl1
SiCe> = bit2
This register is accessed as a 0(te.
Ta!le (-+. Processor L7L& "egister <its
<it 0a%e 5escription
&9 'C1D12 3eads to this register return all HerosK writes to this register have no effect. 3eads
to this register also generate an Jenter a C2 power stateL to the clock control
logic.
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5.7.3.5.3 Processor LVL3 Register (P_LVL3): 8
Re,i2ter 6ocation> %ither ?P_B6AB D G> S12tem #/0 Space
or 2pecified b1 _)S< 0b9ect> S12tem #/0$ S12tem ;emor1$ or
5unctional 5i-ed "ardware Space
Default @alue> ((h
&ttribute> ReadE0nl1
SiCe> = bit2
This register is accessed as a 0(te.
Ta!le (-+/ Processor L7L# "egister <its
<it 0a%e 5escription
&9 'C1D13 3eads to this register return all HerosK writes to this register have no effect. 3eads
to this register also generate an Jenter a C3 power stateL to the clock control
logic.
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428 Advanced Configuration and 'ower %nterface !pecification
5.7.3.6
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Reset Register
The optional AC'% reset mechanism specifies a standard mechanism that provides a complete s(stem reset.
When implemented, this mechanism must reset the entire s(stem. This includes processors, core logic, all
0uses, and all peripherals. 5rom an 2!'M perspective, asserting the reset mechanism is the logical
e:uivalent to power c(cling the machine. ,pon gaining control after a reset, 2!'M will perform actions in
like manner to a cold 0oot.
The reset mechanism is implemented via an 8&0it register descri0ed 0( 3.!.TC3.$ in the 5A-T =alwa(s
accessed via the natural alignment and siHe descri0ed in 3.!.TC3.$>. To reset the machine, software will
write a value =indicated in 3.!.TCDA1,. in 5A-T> to the reset register. The 3.!.TC3.$ field in the
5A-T indicates the location of the reset register.
The reset register ma( e/ist onl( in %F2 space, Memor( space, or in 'C% Configuration space on a function
in 0us . Therefore, the AddressC!paceC%- value in 3.!.TC3.$ must 0e set to %F2 space, Memor( space,
or 'C% Configuration space =with a 0us num0er of >. As the register is onl( 8 0its, 3egisterC;itCWidth
must 0e 8 and 3egisterC;itC2ffset must 0e .
The s(stem must reset immediatel( following the write to this register. 2!'M assumes that the processor
will not e/ecute 0e(ond the write instruction. 2!'M should e/ecute spin loops on the C',s in the s(stem
following a write to this register.
5.7.4 Generic Hardware Registers
AC'% provides a mechanism that allows a uni:ue piece of Jvalue addedL hardware to 0e descri0ed to
2!'M in the AC'% Namespace. There are a num0er of rules to 0e followed when designing AC'%&
compati0le hardware.
'rogramming 0its can reside in an( of the defined generic hardware address spaces =s(stem %F2, s(stem
memor(, 'C% configuration, em0edded controller, or !M;us>, 0ut the top&level event 0its are contained in
the general&purpose event registers. The general&purpose event registers are pointed to 0( the $'.C;1E
and $'.4C;1E register 0locks, and the generic hardware registers can 0e in an( of the defined AC'%
address spaces. A deviceMs generic hardware programming model is descri0ed through an associated o0#ect
in the AC'% Namespace, which specifies the 0itMs function, location, address space, and address location.
The programming model for devices is normall( 0roken into status and control functions. !tatus 0its are
used to generate an event that allows 2!'M to call a control method associated with the pending status 0it.
The called control method can then control the hardware 0( manipulating the hardware control 0its or 0(
investigating child status 0its and calling their respective control methods. AC'% re:uires that the top level
JparentL event status and ena0le 0its reside in either the $'.C!T! or $'.4C!T! registers, and JchildL
event status 0its can reside in generic address space.
The e/ample 0elow illustrates some of these concepts. The top diagram shows how the logic is partitioned
into two chips< a chipset and an em0edded controller.
The chipset contains the interrupt logic, performs the power 0utton =which is part of the fi/ed
register space, and is not discussed here>, the lid switch =used in porta0les to indicate when the
clam shell lid is open or closed>, and the 3%Y function =which can 0e used to wake a sleeping
s(stem>.
The em0edded controller chip is used to perform the AC power detect and dockFundock event
logic. Additionall(, the em0edded controller supports some s(stem management functions using
an 2!&transparent interrupt in the em0edded controller =represented 0( the .AT!M%Y signal>.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
43 Advanced Configuration and 'ower %nterface !pecification
5Px%R$5
Bloc:
ACPI/Compati0le
Chip Set
Momentar,
Momentar,
PRBT&8
+ID
S#itch
Po#er
B(tton
-I'8
$m0edded
Controller
@
$C%CS8
$ETSMI8
$ETPM$8
AC8
$
m
0
e
d
d
e
d
C
o
n
tro
lle
r In
te
rfa
c
e
$C%STS
5P%STS41
$C%$&
5P%$&41
Other SCI
sources
SCI8
Sharea0le
Interrupt
AC%STS
$141
'OC#%STS
P14>14!
'OC#8
RI8
$ETPM$8
RI%STS
5P%STS4!
RI%$&
5P%$&4!
RI8
AC8
'OC#8
$ETPM$8 $ETPM$8
-I'%STS
5P%STS4"
-I'%$&
5P%$&4"
-I'
-I'%PO-
S((4"
$ETSMI8
SMI/onl,
sources $ETSMI8
$ETSMI8
SMI Onl,
$9ents
'e0ounce
'oc:ing
Chip
'OC#8
(>
(;
6igure (-+# 1xa%ple of ;eneral-Purpose vs ;eneric Hardware 1vents
At the top level, the generic events in the $'.xC!T! register are the<
.m0edded controller interrupt, which contains two :uer( events< one for AC detection and one for
docking =the docking :uer( event has a child interrupt status 0it in the docking chip>.
3ing indicate status =used for waking the s(stem>.
1id status.
The em0edded controller event status 0it =.CC!T!> is used to indicate that one of two :uer( events is
active.
A :uer( event is generated when the ACY signal is asserted. The em0edded controller returns a
:uer( value of 3" =an( 0(te num0er can 0e used> upon a :uer( command in response to this eventK
2!'M will then schedule for e/ecution the control method associated with :uer( value 3".
Another :uer( event is for the docking chip that generates a docking event. %n this case, the em0edded
controller will return a :uer( value of 3* upon a :uer( command from s(stem software responding to an
!C% from the em0edded controller. 2!'M will then schedule the control method associated with the :uer(
value of 3* to 0e e/ecuted, which services the docking event.
5or each of the status 0its in the $'.xC!T! register, there is a corresponding ena0le 0it in the $'.xC.N
register. Notice that the child status 0its do not necessaril( need ena0le 0its =see the -2CEC!T! 0it>.
The lid logic contains a control 0it to determine if its status 0it is set when the 1%- is open =1%-C'21 is set
and 1%- is set> or closed =1%-C'21 is clear and 1%- is clear>. This control 0it resides in generic %F2 space
=in this case, 0it 2 of s(stem %F2 space 33h> and would 0e manipulated with a control method associated
with the lid o0#ect.
As with fi/ed hardware events, 2!'M will clear the status 0its in the $'.x register 0locks. @owever, AM1
code clears all si0ling status 0its in the generic hardware.
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$eneric hardware features are controlled 0( 2.M supplied control methods, encoded in AM1. AC'%
provides 0oth an event and control model for development of these features. The AC'% specification also
provides specific control methods for notif(ing 2!'M of certain power management and 'lug and 'la(
events. !ection *, JAC'% !oftware 'rogramming Model,L provides information on the t(pes of hardware
functionalit( that support the different t(pes of su0s(stems. The following is a list of features supported 0(
AC'%. The list is not intended to 0e complete or comprehensive.
-evice insertionFe#ection =for e/ample, docking, device 0a(, AFC adapter>
;atteries
"
'latform thermal su0s(stem
Turning onFoff power resources
Mo0ile lid %nterface
.m0edded controller
!(stem indicators
2.M&specific wake events
'lug and 'la( configuration
"
AC'% operating s(stems assume the use of the !mart ;atter( !(stem %mplementers 5orum defined
standard for 0atteries, called the J!mart ;atter( !pecificationL =!;!>. AC'% provides a set of control
methods for use 0( 2.Ms that use a proprietar( Jcontrol methodL 0atter( interface.
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432 Advanced Configuration and 'ower %nterface !pecification
5.7.4.1
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General-Purpose Event Register Blocks
AC'% supports up to two general&purpose register 0locks as descri0ed in the 5A-T =see section *, JAC'%
!oftware 'rogramming ModelL> and an ar0itrar( num0er of additional $'. 0locks descri0ed as devices
within the AC'% namespace. .ach register 0lock contains two registers< an ena0le and a status register.
.ach register 0lock is 32&0it aligned. .ach register in the 0lock is accessed as a 0(te. %t is up to the specific
design to determine if these 0its retain their conte/t across sleeping or soft&off states. %f the( lose their
conte/t across a sleeping or soft&off state, then ;%2! resets the respective ena0le 0it prior to passing control
to the 2! upon waking.
5.7.4.1.1 General-Purpose Event 0 Register Block
This register 0lock consists of two registers< The $'.C!T! and the $'.C.N registers. .ach registerMs
length is defined to 0e half the length of the $'. register 0lock, and is descri0ed in the AC'% 5A-TMs
$'.C;1E and $'.C;1EC1.N operators. 2!'M owns the general&purpose event resources and these
0its are onl( manipulated 0( 2!'MK AM1 code cannot access the general&purpose event registers.
%t is envisioned that chipsets will contain $'. event registers that provide $'. input pins for various
events.
The platform designer would then wire the $'.s to the various value&added event hardware and the AM1
code would descri0e to 2!'M how to utiliHe these events. As such, there will 0e the case where a platform
has $'. events that are not wired to an(thing =the( are present in the chip set>, 0ut are not utiliHed 0( the
platform and have no associated AM1 code. %n such, cases these event pins are to 0e tied inactive such that
the corresponding !C% status 0it in the $'. register is not set 0( a floating input pin.
5.7.4.1.1.1 General-Purpose Event 0 Status Register
Re,i2ter 6ocation> ?:P%(_S<SB S12tem #/0 or S12tem ;emor1 Space
Default @alue> ((h
&ttribute> Read/Write
SiCe> :P%(_B6A_6%!/3
The general&purpose event status register contains the general&purpose event status 0its in 0ank Hero of
the general&purpose registers. .ach availa0le status 0it in this register corresponds to the 0it with the same
0it position in the $'.C.N register. .ach availa0le status 0it in this register is set when the event is
active, and can onl( 0e cleared 0( software writing a J4L to its respective 0it position. 5or the general&
purpose event registers, unimplemented 0its are ignored 0( 2!'M.
.ach status 0it can optionall( wake the s(stem if asserted when the s(stem is in a sleeping state with its
respective ena0le 0it set. 2!'M accesses $'. registers through 0(te accesses =regardless of their length>.
5.7.4.1.1.2 General-Purpose Event 0 Enable Register
Re,i2ter 6ocation> ?:P%(_%!B S12tem #/0 or S12tem ;emor1 Space
Default @alue> ((h
&ttribute> Read/Write
SiCe> :P%(_B6A_6%!/3
The general&purpose event ena0le register contains the general&purpose event ena0le 0its. .ach availa0le
ena0le 0it in this register corresponds to the 0it with the same 0it position in the $'.C!T! register. The
ena0le 0its work similarl( to how the ena0le 0its in the fi/ed&event registers are defined< When the ena0le
0it is set, then a set status 0it in the corresponding status 0it will generate an !C% 0it. 2!'M accesses $'.
registers through 0(te accesses =regardless of their length>.
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5.7.4.1.2 General-Purpose Event 1 Register Block
This register 0lock consists of two registers< The $'.4C!T! and the $'.4C.N registers. .ach registerMs
length is defined to 0e half the length of the $'.4 register 0lock, and is descri0ed in the AC'% 5A-TMs
$'.4C;1E and $'.4C;1EC1.N operators.
5.7.4.1.2.1 General-Purpose Event 1 Status Register
Re,i2ter 6ocation> ?:P%4_S<SB S12tem #/0 or S12tem ;emor1 Space
Default @alue> ((h
&ttribute> Read/Write
SiCe> :P%4_B6A_6%!/3
The general &purpose event 4 status register contains the general&purpose event status 0its. .ach availa0le
status 0it in this register corresponds to the 0it with the same 0it position in the $'.4C.N register. .ach
availa0le status 0it in this register is set when the event is active, and can onl( 0e cleared 0( software
writing a J4L to its respective 0it position. 5or the general&purpose event registers, unimplemented 0its are
ignored 0( the operating s(stem.
.ach status 0it can optionall( wake the s(stem if asserted when the s(stem is in a sleeping state with its
respective ena0le 0it set.
2!'M accesses $'. registers through 0(te accesses =regardless of their length>.
5.7.4.1.2.2 General-Purpose Event 1 Enable Register
Re,i2ter 6ocation> ?:P%4_%!B S12tem #/0 or S12tem ;emor1 Space
Default @alue> ((h
&ttribute> Read/Write
SiCe> :P%4_B6A_6%!/3
The general&purpose event 4 ena0le register contains the general&purpose event ena0le. .ach availa0le
ena0le 0it in this register corresponds to the 0it with the same 0it position in the $'.4C!T! register. The
ena0le 0its work similarl( to how the ena0le 0its in the fi/ed&event registers are defined< When the ena0le
0it is set, a set status 0it in the corresponding status 0it will generate an !C% 0it.
2!'M accesses $'. registers through 0(te accesses =regardless of their length>.
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5.7.4.2
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Example Generic Devices
This section points out generic devices with specific AC'% driver support.
5.7.4.2.1 Lid Switch
The 1id switch is an optional feature present in most Jclam shellL st(le mo0ile computers. %t can 0e used 0(
the 2! as polic( input for sleeping the s(stem, or for waking the s(stem from a sleeping state. %f used, then
the 2.M needs to define the lid switch as a device with an C@%- o0#ect value of JC'N'C-L, which
identifies this device as the lid switch to 2!'M. The 1id device needs to contain a control method that
returns its status. The 1id event handler AM1 code reconfigures the lid hardware =if it needs to> to generate
an event in the other direction, clear the status, and then notif( 2!'M of the event.
./ample hardware and A!1 code is shown 0elow for such a design.
-I'%PO-
-I'%STS
@ ms
'e0ounce
Momentar, &ormall,
Open push 0utton
6igure (-+( 1xa%ple ;eneric Address Space Lid Switch Logic
This logic will set the 1id status 0it when the 0utton is pressed or released =depending on the 1%-C'21
0it>.
The A!1 code 0elow defines the following<
An operational region where the lid polarit( resides in address space !(stem address space in
registers /24.
A field operator to allow AM1 code to access this 0it< 'olarit( control 0it =1%-C'21> is called
1'21 and is accessed at /24..
A device named BC!;.1%- with the following<
A 'lug and 'la( identifier J'N'C-L that associates 2!'M with this o0#ect.
-efines an o0#ect that specifies a change in the lidMs status 0it can wake the s(stem from the !"
sleep state and from all higher sleep states =!4, !2, or !3>.
The lid switch event handler that does the following<
-efines the lid status 0it =1%-C!T!> as a child of the general&purpose event register 0it 4.
-efines the event handler for the lid =onl( event handler on this status 0it> that does the following<
5lips the polarit( of the 1'21 0it =to cause the event to 0e generated on the opposite
condition>.
$enerates a notif( to the 2! that does the following<
'asses the BC!;.1%- o0#ect.
%ndicates a device specific event =notif( value /8>.
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// Define a 6id 2witch
0perationRe,ion(\P"0$ S12tem#0$ (-3(4$ (-4)
5ield(\P"0$ B1te&cc$ !o6oc+$ Pre2erve)
6P06$ 4 // 6id polarit1 control bit
/
Device(\_SB.6#D)
!ame(_"#D$ %#S&#D('P!P()(D*))
;ethod(_6#D)Return(6P06)/
!ame(_PRW$ Pac+a,e(3)
4$ // bit 4 of :P% to enable 6id wa+eup
(-(./ // can wa+eup from S. 2tate
)
/
Scope(\_:P%) // Root level event handler2
;ethod(_6(4) // u2e2 bit 4 of :P(_S<S re,i2ter
!ot(6P06$ 6P06) // 5lip the lid polarit1 bit
!otif1(6#D$ (-=() // !otif1 0S of event
/
/
5.7.4.2.2 Embedded Controller
AC'% provides a standard interface that ena0les AM1 code to define and access generic logic in Jem0edded
controller space.L This supports current computer models where much of the value added hardware is
contained within the em0edded controller while allowing the AM1 code to access this hardware in an
a0stracted fashion.
The em0edded controller is defined as a device and must contain a set num0er of control methods<
C@%- with a value of 'N'C6 to associate this device with the AC'%Ms em0edded controllerMs
driver.
CC3! to return the resources 0eing consumed 0( the em0edded controller.
C$'. that returns the general&purpose event 0it that this em0edded controller is wired to.
Additionall( the em0edded controller can support up to 2** generic events per em0edded controller,
referred to as :uer( events. These :uer( event handles are defined within the em0edded controllerMs device
as control methods. An e/ample of defining an em0edded controller device is shown 0elow<
Device(%)()
// PnP #D
!ame(_"#D$ %#S&#D('P!P()(H*))
// Return2 the ')urrent Re2ource2* of %)
!ame(_)RS$
Re2ource<emplate()
#0(Decode4I$ (-I3$ (-I3$ ($ 4)
#0(Decode4I$ (-II$ (-II$ ($ 4)
/)
// Define that the %) S)# i2 bit ( of the :P_S<S re,i2ter
!ame(_:P%$ () // embedded controller i2 wired to bit ( of :P%
0perationRe,ion(\%)($ %mbedded)ontrol$ ($ (-55)
5ield(%)($ B1te&cc$ 6oc+$ Pre2erve)
// 5ield definition2
/
;ethod(J(()../
;ethod(J55)../
/
5or more information on the em0edded controller, see section 42, JAC'% .m0edded Controller %nterface
!pecification.L
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5.7.4.2.3 Fan
AC'% has a device driver to control fans =active cooling devices> in platforms. A fan is defined as a device
with the 'lug and 'la( %- of J'N'C;.L %t should then contain a list power resources used to control the
fan.
5or more information, see section 6, JAC'% -evices and -evice !pecific 20#ects.L
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6 ACPI Software Programming Model
AC'% defines a hardware register interface that an AC'%&compati0le 2! uses to control core power
management features of a machine, as descri0ed in section ", JAC'% @ardware !pecification.L AC'% also
provides an a0stract interface for controlling the power management and configuration of an AC'% s(stem.
5inall(, AC'% defines an interface 0etween an AC'%&compati0le 2! and the s(stem ;%2!.
To give hardware vendors fle/i0ilit( in choosing their implementation, AC'% uses ta0les to descri0e s(stem
information, features, and methods for controlling those features. These ta0les list devices on the s(stem
0oard or devices that cannot 0e detected or power managed using some other hardware standard, plus their
capa0ilities as descri0ed in section 3, J2verview.L The( also list s(stem capa0ilities such as the sleeping
power states supported, a description of the power planes and clock sources availa0le in the s(stem,
0atteries, s(stem indicator lights, and so on. This ena0les 2!'M to control s(stem devices without needing
to know how the s(stem controls are implemented.
Topics covered in this section are<
The AC'% s(stem description ta0le architecture is defined, and the role of 2.M&provided
definition 0locks in that architecture is discussed.
The concept of the AC'% Namespace is discussed.
6.1 Overview of the System Description Table Architecture
The 3oot !(stem -escription 'ointer =3!-'> structure is located in the s(stemMs memor( address space
and is setup 0( the platform firmware. This structure contains the address of the ./tended !(stem
-escription Ta0le =3!-T>, which references other description ta0les that provide data to 2!'M, suppl(ing
it with knowledge of the 0ase s(stemMs implementation and configuration =see 5igure *&4>.
- o c a t e d i n s , s t e m F s m e m o r , a d d r e s s s p a c e
$ x t e n d e d S , s t e m
' e s c r i p t i o n T a 0 l e
7 e a d e r
C S D T
E n t r y
E n t r y
. . .
E n t r y
. . .
R o o t S , s t e m
' e s c r i p t i o n P o i n t e r
7 e a d e r
S i g
c o n t e n t s
7 e a d e r
S i g
c o n t e n t s
R S D P T R
P o i n t e r
P o i n t e r
6igure A-+ "oot S)ste% 5escription Pointer and Ta!le
All s(stem description ta0les start with identical headers. The primar( purpose of the s(stem description
ta0les is to define for 2!'M various industr(&standard implementation details. !uch definitions ena0le
various portions of these implementations to 0e fle/i0le in hardware re:uirements and design, (et still
provide 2!'M with the knowledge it needs to control hardware directl(.
The ./tended !(stem -escription Ta0le =3!-T> points to other ta0les in memor(. Alwa(s the first ta0le, it
points to the 5i/ed AC'% -escription ta0le =5A-T>. The data within this ta0le includes various fi/ed&length
entries that descri0e the fi/ed AC'% features of the hardware. The 5A-T ta0le alwa(s refers to the
-ifferentiated !(stem -escription Ta0le =-!-T>, which contains information and descriptions for various
s(stem features. The relationship 0etween these ta0les is shown in 5igure *&2.
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'e9ice I/O
'e9ice Memor,
PCI configuration
$m0edded Controller space
.irmware ACPI
Control Structure
a:e 6ector
Shared -oc:
6ACS
,P'>B+K
P*5'>B+K
'ifferentiated S,stem
'escription Ta0le
7eader
DSDT
-ifferentiated
-efinition
;lock
P*3'>B+K
.ixed ACPI
'escription Ta0le
7eader
6ACP
Static info
-ocated in
port space
O$M/Specific
ACPI
'ri9er
Software
7ardware
.IRM
'S'T
B-#s
...
6igure A-& 5escription Ta!le Structures
2!'M finds the 3!-' structure as descri0ed in section *.2.*.4 =J5inding the 3!-' on %A&'C
!(stemsL> or section *.2.*.2 =J5inding the 3!-' on .5% .na0led !(stemsL>.
When 2!'M locates the structure, it looks at the ph(sical address for the 3oot !(stem -escription Ta0le or
the ./tended !(stem -escription Ta0le. The 3oot !(stem -escription Ta0le starts with the signature
J3!-TL, while the ./tended !(stem -escription Ta0le starts with the signature JA!-TL. These ta0les
contain one or more ph(sical pointers to other s(stem description ta0les that provide various information
a0out the s(stem. As shown in 5igure *&4, there is alwa(s a ph(sical address in the 3oot !(stem
-escription Ta0le for the 5i/ed AC'% -escription ta0le =5A-T>.
When 2!'M follows a ph(sical pointer to another ta0le, it e/amines each ta0le for a known signature.
;ased on the signature, 2!'M can then interpret the implementation&specific data within the description
ta0le.
The purpose of the 5A-T is to define various static s(stem information related to configuration and power
management. The 5i/ed AC'% -escription Ta0le starts with the J5AC'L signature. The 5A-T descri0es the
implementation and configuration details of the AC'% hardware registers on the platform.
5or a specification of the AC'% @ardware 3egister ;locks ='M4aC.DTC;1E, 'M40C.DTC;1E,
'M4aCCNTC;1E, 'M40CCNTC;1E, 'M2CCNTC;1E, 'MCTM3C;1E, $'C;1E, $'4C;1E, and one
or more 'C;1Es>, see section ".9, JAC'% 3egister Model.L The 'M4aC.DTC;1E, 'M40C.DTC;1E,
'M4aCCNTC;1E, 'M40CCNTC;1E, 'M2CCNTC;1E, and 'MCTM3C;1E 0locks are for controlling
low&level AC'% s(stem functions.
The $'.C;1E and $'.4C;1E 0locks provide the foundation for an interrupt&processing model for
Control Methods. The 'C;1E 0locks are for controlling processor features.
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;esides AC'% @ardware 3egister implementation information, the 5A-T also contains a ph(sical pointer to
the -ifferentiated !(stem -escription Ta0le =-!-T>. The -!-T contains a -efinition ;lock named the
-ifferentiated -efinition ;lock for the -!-T that contains implementation and configuration information
2!'M can use to perform power management, thermal management, or 'lug and 'la( functionalit( that
goes 0e(ond the information descri0ed 0( the AC'% hardware registers.
A -efinition ;lock contains information a0out hardware implementation details in the form of a
hierarchical namespace, data, and control methods encoded in AM1. 2!'M JloadsL or JunloadsL an entire
definition 0lock as a logical unit. The -ifferentiated -efinition ;lock is alwa(s loaded 0( 2!'M at 0oot
time and cannot 0e unloaded.
-efinition ;locks can either define new s(stem attri0utes or, in some cases, 0uild on prior definitions. A
-efinition ;lock can 0e loaded from s(stem memor( address space. 2ne use of a -efinition ;lock is to
descri0e and distri0ute platform version changes.
-efinition 0locks ena0le wide variations of hardware platform implementations to 0e descri0ed to the
AC'%&compati0le 2! while confining the variations to reasona0le 0oundaries. -efinition 0locks ena0le
simple platform implementations to 0e e/pressed 0( using a few well&defined o0#ect names. %n theor(, it
might 0e possi0le to define a 'C% configuration space&like access method within a -efinition ;lock, 0(
0uilding it from %F2 space, 0ut that is not the goal of the -efinition ;lock specification. !uch a space is
usuall( defined as a J0uilt inL operator.
!ome operators perform simple functions and others encompass comple/ functions. The power of the
-efinition ;lock comes from its a0ilit( to allow these operations to 0e glued together in numerous wa(s, to
provide functionalit( to 2!'M. The operators present are intended to allow man( useful hardware designs
to 0e AC'%&e/pressed, not to allow all hardware designs to 0e e/pressed.
6.1.1 Address Space Translation
!ome platforms ma( contain 0ridges that perform translations as %F2 andFor Memor( c(cles pass through
the 0ridges. This translation can take the form of the addition or su0traction of an offset. 2r it can take the
form of a conversion from %F2 c(cles into Memor( c(cles and 0ack again. When translation takes place, the
addresses placed on the processor 0us 0( the processor during a read or write c(cle are not the same
addresses that are placed on the %F2 0us 0( the %F2 0us 0ridge. The address the processor places on the
processor 0us will 0e known here as the processor&relative address. And the address that the 0ridge places
on the %F2 0us will 0e known as the 0us&relative address. ,nless otherwise noted, all addresses used within
this section are processor&relative addresses.
5or e/ample, consider a platform with two root 'C% 0uses. The platform designer has several choices. 2ne
solution would 0e to split the 4+&0it %F2 space into two parts, assigning one part to the first root 'C% 0us
and one part to the second root 'C% 0us. Another solution would 0e to make 0oth root 'C% 0uses decode the
entire 4+&0it %F2 space, mapping the second root 'C% 0usMs %F2 space into memor( space. %n this second
scenario, when the processor needs to read from an %F2 register of a device underneath the second root 'C%
0us, it would need to perform a memor( read within the range that the root 'C% 0us 0ridge is using to map
the %F2 space.
0oteH %ndustr( standard 'Cs do not provide address space translations 0ecause of historical compati0ilit(
issues.
6.2 ACPI System Description Tables
This section specifies the structure of the s(stem description ta0les<
3oot !(stem -escription 'ointer =3!-'>
!(stem -escription Ta0le @eader
3oot !(stem -escription Ta0le =3!-T>
5i/ed AC'% -escription Ta0le =5A-T>
5irmware AC'% Control !tructure =5AC!>
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-ifferentiated !(stem -escription Ta0le =-!-T>
!econdar( !(stem -escription Ta0le =!!-T>
Multiple A'%C -escription Ta0le =MA-T>
!mart ;atter( Ta0le =!;!T>
./tended !(stem -escription Ta0le =A!-T>
.m0edded Controller ;oot 3esources Ta0le =.C-T>
!(stem 1ocalit( -istance %nformation Ta0le =!1%T>
!(stem 3esource Affinit( Ta0le =!3AT>
All numeric values from the a0ove ta0les, 0locks, and structures are alwa(s encoded in little endian format.
!ignature values are stored as fi/ed&length strings.
6.2.1 Reserved Bits and Fields
5or future e/pansion, all data items marked as reser2ed in this specification have strict meanings. This
section lists software re:uirements for reser2ed fields. Notice that the list contains terms such as AC'%
ta0les and AM1 code defined later in this section of the specification.
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6.2.1.1
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Reserved Bits and Software Components
2.M implementations of software and AM1 code return the 0it value of for all reserved 0its in
AC'% ta0les or in other software values, such as resource descriptors.
5or all reserved 0its in AC'% ta0les and registers, 2!'M implementations must<
%gnore all reserved 0its that are read.
'reserve reserved 0it values of readFwrite data items =for e/ample, 2!'M writes 0ack reserved 0it
values it reads>.
Write Heros to reserved 0its in write&onl( data items.
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6.2.1.2
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Reserved Values and Software Components
2.M implementations of software and AM1 code return onl( defined values and do not return
reserved values.
2!'M implementations write onl( defined values and do not write reserved values.
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6.2.1.3
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Reserved Hardware Bits and Software Components
!oftware ignores all reserved 0its read from hardware ena0le or status registers.
!oftware writes Hero to all reserved 0its in hardware ena0le registers.
!oftware ignores all reserved 0its read from hardware control and status registers.
!oftware preserves the value of all reserved 0its in hardware control registers 0( writing 0ack read
values.
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6.2.1.4
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Ignored Hardware Bits and Software Components
!oftware handles ignored 0its in AC'% hardware registers the same wa( it handles reserved 0its in
these same t(pes of registers.
6.2.2 Compatibility
All versions of the AC'% ta0les must maintain 0ackward compati0ilit(. To accomplish this, modifications of
the ta0les consist of redefinition of previousl( reserved fields and values plus appending data to the 4.
ta0les. Modifications of the AC'% ta0les re:uire that the version num0ers of the modified ta0les 0e
incremented. The length field in the ta0les includes all additions and the checksum is maintained for the
entire length of the ta0le.
6.2.3 Address Format
Addresses used in the AC'% 4. s(stem description ta0les were e/pressed as either s(stem memor( or %F2
space. This was targeted at the %A&32 environment. Newer architectures re:uire addressing mechanisms
0e(ond that defined in AC'% 4.. To support these architectures AC'% must support +"&0it addressing and it
must allow the placement of control registers in address spaces other than !(stem %F2.
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6.2.3.1
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Generic Address Structure
The $eneric Address !tructure =$A!> provides the platform with a ro0ust means to descri0e register
locations. This structure, descri0ed 0elow =Ta0le *&4>, is used to e/press register addresses within ta0les
defined 0( AC'% .
Ta!le A-+ ;eneric Address Structure >;AS?
6ield
<)te
Length
<)te
3ffset 5escription
AddressC!paceC%- 4 The address space where the data structure or register e/ists.
-efined values are<
!(stem Memor(
4 !(stem %F2
2 'C% Configuration !pace
3 .m0edded Controller
" !M;us
* to /9. I 3eserved
/95 5unctional 5i/ed @ardware
/8 to /;5 I 3eserved
/C to /55 I 2.M -efined
3egisterC;itCWidth 4 4 The siHe in 0its of the given register. When addressing a data
structure, this field must 0e Hero.
3egisterC;itC2ffset 4 2 The 0it offset of the given register at the given address. When
addressing a data structure, this field must 0e Hero.
AccessC!iHe 4 3 !pecifies access siHe.
,ndefined =legac( reasons>
4 ;(te access
2 Word access
3 -word access
" Gword access
Address 8 " The +"&0it address of the data structure or register in the given
address space =relative to the processor>. =!ee 0elow for
specific formats.>
Ta!le A-& Address Space 6or%at
Address Space 6or%at
I!(stem Memor( The +"&0it ph(sical memor( address =relative to the processor> of the register. 32&
0it platforms must have the high -W23- set to .
4I!(stem %F2 The +"&0it %F2 address =relative to the processor> of the register. 32&0it platforms
must have the high -W23- set to .
2I'C% Configuration
!pace
'C% Configuration space addresses must 0e confined to devices on 'C% !egment
$roup , 0us . This restriction e/ists to accommodate access to fi/ed hardware
prior to 'C% 0us enumeration. The format of addresses are defined as follows<
:3"5 Location 5escription
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 4*3
Address Space 6or%at
@ighest W23- 3eserved =must 0e >
N 'C% -evice num0er on 0us
N 'C% 5unction num0er
1owest W23- 2ffset in the configuration space header
5or e/ample< 2ffset 23h of 5unction 2 on device 9 on 0us segment would 0e
represented as< /9223.
/95I5unctional
5i/ed @ardware
,se of $A! fields other than AddressC!paceC%- is specified 0( the C',
manufacturer. The use of functional fi/ed hardware carries with it a reliance on 2!
specific software that must 0e considered. 2.Ms should consult 2! vendors to
ensure that specific functional fi/ed hardware interfaces are supported 0( specific
operating s(stems.
6.2.4 Universal Uniform Identifers (UUID)
,,%-s =,niversall( ,ni:ue %-entifiers>, also known as $,%-s =$lo0all( ,ni:ue %-entifiers> are 428 0it
long values that e/tremel( likel( to 0e different from all other ,,%-s generated until 3" A.-. ,,%-s are
used to distinguish 0etween callers of A!1 methods, such as C-!M and C2!C.
The format of 0oth the 0inar( and string representations of ,,%-s along with an algorithm to generate
them is specified in %!2F%.C 44*98<466+ and can 0e found as part of the -istri0uted Computing
.nvironment 4.4< 3emote 'rocedure Call specification, which can 0e downloaded from here<
http<FFwww.opengroup.orgFpu0licationsFcatalogFc9+.htm.
6.2.5 Root System Description Pointer (RSDP)
-uring 2! initialiHation, 2!'M must o0tain the 3oot !(stem -escription 'ointer =3!-'> structure from
the platform. When 2!'M locates the 3oot !(stem -escription 'ointer =3!-'> structure, it then locates
the 3oot !(stem -escription Ta0le =3!-T> or the ./tended 3oot !(stem -escription Ta0le =A!-T> using
the ph(sical s(stem address supplied in the 3!-'.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
4*" Advanced Configuration and 'ower %nterface !pecification
6.2.5.1
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Finding the RSDP on IA-PC Systems
2!'M finds the 3oot !(stem -escription 'ointer =3!-'> structure 0( searching ph(sical memor( ranges
on 4+&0(te 0oundaries for a valid 3oot !(stem -escription 'ointer structure signature and checksum match
as follows<
The first 4 E; of the ./tended ;%2! -ata Area =.;-A>. 5or .%!A or MCA s(stems, the .;-A
can 0e found in the two&0(te location "<.h on the ;%2! data area.
The ;%2! read&onl( memor( space 0etween .h and 55555h.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
4*+ Advanced Configuration and 'ower %nterface !pecification
6.2.5.2
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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Finding the RSDP on EFI Enabled Systems
%n ./tensi0le 5irmware %nterface =.5%> ena0led s(stems =for e/ample, %tanium
TM
&0ased platforms> a pointer
to the 3!-' structure e/ists within the .5% !(stem Ta0le. The 2! loaderMs .5% image is provided a pointer
to the .5% !(stem Ta0le at invocation. The 2! loader must retrieve the pointer to the 3!-' structure from
the .5% !(stem ta0le and conve( the pointer to 2!'M, using an 2! dependent data structure, as part of the
hand off of control from the 2! loader to the 2!.
The 2! loader locates the pointer to the 3!-' structure 0( e/amining the .5% configuration ta0le within
the .5% s(stem ta0le. .5% configuration ta0le entries consist of $lo0all( ,ni:ue %dentifier =$,%->Fta0le
pointer pairs. The .5% 4. specification defines a $,%- for AC'%. An .5% configuration ta0le entr( that
matches this $,%- points to an AC'% 4.&compati0le 3!-' structure =AC'% 4. $,%->.
The .5% $,%- for a pointer to the current revision 3!-' structure is< 88+8.894&."54&44d3&;C22&
8C93C8884.
The 2! loader for an AC'%&compati0le 2! will search for an 3!-' structure pointer using the current
revision $,%- first and if it finds one, will use the corresponding 3!-' structure pointer. %f the $,%- is
not found then the 2! loader will search for the 3!-' structure pointer using the AC'% 4. version $,%-.
The 2! loader must retrieve the pointer to the 3!-' structure from the .5% !(stem Ta0le !efore assuming
platform control via the .5% ./it;oot!ervices interface. !ee the .5% specification for more information.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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6.2.5.3
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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RSDP Structure
The revision num0er contained within the structure indicates the siHe of the ta0le structure.
Ta!le A-# "oot S)ste% 5escription Pointer Structure
6ield
<)te
Length
<)te
3ffset 5escription
!ignature 8 J3!- 'T3 L =Notice that this signature must contain a trailing
0lank character.>
Checksum 4 8 This is the checksum of the fields defined in the AC'% 4.
specification. This includes onl( the first 2 0(tes of this ta0le,
0(tes to 46, including the checksum field. These 0(tes must sum
to Hero.
2.M%- + 6 An 2.M&supplied string that identifies the 2.M.
3evision 4 4* The revision of this structure. 1arger revision num0ers are
0ackward compati0le to lower revision num0ers. The AC'% version
4. revision num0er of this ta0le is Hero. The current value for this
field is 2.
3sdtAddress " 4+ 32 0it ph(sical address of the 3!-T.
1ength " 2 The length of the ta0le, in 0(tes, including the header, starting from
offset . This field is used to record the siHe of the entire ta0le.
AsdtAddress 8 2" +" 0it ph(sical address of the A!-T.
./tended
Checksum
4 32 This is a checksum of the entire ta0le, including 0oth checksum
fields.
3eserved 3 33 3eserved field
6.2.6 System Description Table Header
All s(stem description ta0les 0egin with the structure shown in Ta0le *&". The !ignature field determines
the content of the s(stem description ta0le. !(stem description ta0le signatures defined 0( this specification
are listed in Ta0le *&*.
Ta!le A-( 51SC"IPTI30DH1A51" 6ields
6ield
<)te
Length
<)te
3ffset 5escription
!ignature " The A!C%% string representation of the ta0le identifier. Notice that
if 2!'M finds a signature in a ta0le that is not listed in Ta0le *&*,
2!'M ignores the entire ta0le =it is not loaded into AC'%
namespace>K 2!'M ignores the ta0le even though the values in
the 1ength and Checksum fields are correct.
1ength " " The length of the ta0le, in 0(tes, including the header, starting
from offset . This field is used to record the siHe of the entire
ta0le.
3evision 4 8 The revision of the structure corresponding to the signature field
for this ta0le. 1arger revision num0ers are 0ackward compati0le to
lower revision num0ers with the same signature.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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6ield
<)te
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<)te
3ffset 5escription
Checksum 4 6 The entire ta0le, including the checksum field, must add to Hero to
0e considered valid.
2.M%- + 4 An 2.M&supplied string that identifies the 2.M.
2.M Ta0le %- 8 4+ An 2.M&supplied string that the 2.M uses to identif( the
particular data ta0le. This field is particularl( useful when
defining a definition 0lock to distinguish definition 0lock
functions. The 2.M assigns each dissimilar ta0le a new 2.M
Ta0le %-.
2.M 3evision " 2" An 2.M&supplied revision num0er. 1arger num0ers are assumed
to 0e newer revisions.
Creator %- " 28 Dendor %- of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the %- for the A!1 Compiler.
Creator 3evision " 32 3evision of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the revision for the A!1 Compiler.
5or 2.Ms, good design practices will ensure consistenc( when assigning 2.M%- and 2.M Ta0le %-
fields in an( ta0le. The intent of these fields is to allow for a 0inar( control s(stem that support services can
use. ;ecause man( support functions can 0e automated, it is useful when a tool can programmaticall(
determine which ta0le release is a compati0le and more recent revision of a prior ta0le on the same 2.M%-
and 2.M Ta0le %-.
Ta0les *&* and *&+ contain the s(stem description ta0le signatures defined 0( this specification. These
s(stem description ta0les ma( 0e defined 0( AC'% =Ta0le *&*> or reserved 0( AC'% and declared 0( other
industr( specifications =Ta0le *&+>. This allows 2! and platform specific ta0les to 0e defined and pointed to
0( the 3!-TFA!-T as needed. 5or ta0les defined 0( other industr( specifications, the AC'% specification
acts as gatekeeper to avoid collisions in ta0le signatures. To help avoid signature collisions, ta0le signatures
will 0e reserved 0( the AC'% promoters and posted independentl( of this specification in AC'% errata and
clarification documents on the AC'% We0 site. 3e:uests to reserve a "&0(te alphanumeric ta0le signature
should 0e sent to the email address infoLacpiinfo and should include the purpose of the ta0le and
reference url to a document that descri0es the ta0le format.
Ta!le A-A 51SC"IPTI30DH1A51" Signatures for ta!les defined !) ACPI
Signature 5escription "eference
JA'%CL Multiple A'%C -escription Ta0le !ection *.2.44.", JMultiple A'%C -escription
Ta0leL
J-!-TL -ifferentiated !(stem -escription Ta0le !ection *.2.44.4, J-ifferentiated !(stem
-escription Ta0leL
J.C-TL .m0edded Controller ;oot 3esources Ta0le !ection *.2.4", J.m0edded Controller ;oot
3esources Ta0leL
L5AC'L 5i/ed AC'% -escription Ta0le =5A-T> !ection *.2.6, J5i/ed AC'% -escription Ta0leL
J5AC!L 5irmware AC'% Control !tructure !ection *.2.4, J5irmware AC'% Control
!tructureL
J2.M/L 2.M !pecific %nformation Ta0les 2.M !pecific ta0les. All ta0le signatures
starting with J2.ML are reserved for 2.M
use.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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Signature 5escription "eference
J'!-TL 'ersistent !(stem -escription Ta0le !ection *.2.44.3, J'ersistent !(stem
-escription Ta0leL
J3!-TL 3oot !(stem -escription Ta0le !ection *.2.9, J3oot !(stem -escription
Ta0leL
J!;!TL !mart ;atter( !pecification Ta0le !ection *.2 43, J!mart ;atter( Ta0leL
J!1%TL !(stem 1ocalit( -istance %nformation Ta0le !ection *.2.4+, J!(stem 1ocalit( -istance
%nformation Ta0leL
J!3ATL !(stem 3esource Affinit( Ta0le !ection *.2.4*, J!(stem 3esource Affinit(
Ta0leL
J!!-TL !econdar( !(stem -escription Ta0le !ection *.2.44.2, J!econdar( !(stem
-escription Ta0leL
JA!-TL ./tended !(stem -escription Ta0le !ection *.2.8, J./tended !(stem -escription
Ta0leL
Ta!le A-- 51SC"IPTI30DH1A51" Signatures for ta!les reserved !) ACPI
Signature 5escription "eference
J;22TL !imple ;oot 5lag Ta0le Microsoft !imple ;oot 5lag !pecification
http<FFwww.microsoft.comF@W-.DF
desinitFsimpC0ios.htm
JC'.'L Corrected 'latform .rror 'olling Ta0le -%$+" Corrected 'latform .rror 'olling
!pecification
http<FFwww.dig+".orgFspecifications
J-;$'L -e0ug 'ort Ta0le Microsoft -e0ug 'ort !pecification
http<FFwww.microsoft.comF@W-.DF'1AT52
3MFpcdesignF13Fde0ugspec.asp
J.T-TL .vent Timer -escription Ta0le %A&'C Multimedia Timers !pecification. This
signature has 0een superseded 0( J@'.TL and
is now o0solete.
J@'.TL %A&'C @igh 'recision .vent Timer Ta0le %A&'C @igh 'recision .vent Timer
!pecification.
http<FFwww.intel.comFla0sFplatcompFhpetFhpets
pec.htm
JMC5$L 'C% ./press memor( mapped configuration
space 0ase address -escription Ta0le
'C% 5irmware !pecification, 3evision 3.
http<FFpcisig.com
J!'C3L !erial 'ort Console 3edirection Ta0le Microsoft !erial 'ort Console 3edirection
Ta0le
http<FFwww.microsoft.comF@W-.DF'1AT52
3MFserverFheadlessF!'C3.asp
J!'M%L !erver 'latform Management %nterface Ta0le ftp<FFdownload.intel.comFdesignFserversFipmiF%
'M%v2Crev4C.pdf
JTC'AL Trusted Computing 'latform Alliance
Capa0ilities Ta0le
http<FFwww.trustedpc.org TC'A 'C !pecific
%mplementation !pecification
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
4+2 Advanced Configuration and 'ower %nterface !pecification
Signature 5escription "eference
JW-3TL Watchdog 3esource Ta0le
3e:uirements for @ardware Watchdog Timers
!upported 0( Windows & -esign !pecification
http<FFwww.microsoft.comFwhdcFs(stemFC.CF
hw&wdt.msp/
6.2.7 Root System Description Table (RSDT)
2!'M locates that 3oot !(stem -escription Ta0le 0( following the pointer in the 3!-' structure. The
3!-T, shown in Ta0le *&9, starts with the signature O3!-TM followed 0( an arra( of ph(sical pointers to
other s(stem description ta0les that provide various information on other standards defined on the current
s(stem. 2!'M e/amines each ta0le for a known signature. ;ased on the signature, 2!'M can then
interpret the implementation&specific data within the ta0le.
'latforms provide the 3!-T to ena0le compati0ilit( with AC'% 4. operating s(stems. The A!-T,
descri0ed in the ne/t section, supersedes 3!-T functionalit(.
Ta!le A-. "oot S)ste% 5escription Ta!le 6ields >"S5T?
6ield
<)te
Length
<)te
3ffse
t 5escription
@eader
!ignature " O3!-T.M !ignature for the 3oot !(stem -escription Ta0le.
1ength " " 1ength, in 0(tes, of the entire 3!-T. The length implies the
num0er of .ntr( fields =n> at the end of the ta0le.
3evision 4 8 4
Checksum 4 6 .ntire ta0le must sum to Hero.
2.M%- + 4 2.M %-
2.M Ta0le %- 8 4+ 5or the 3!-T, the ta0le %- is the manufacture model %-. This
field must match the 2.M Ta0le %- in the 5A-T.
2.M 3evision " 2" 2.M revision of 3!-T ta0le for supplied 2.M Ta0le %-.
Creator %- " 28 Dendor %- of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the %- for the A!1 Compiler.
Creator 3evision " 32 3evision of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the revision for the A!1 Compiler.
.ntr( "[n 3+ An arra( of 32&0it ph(sical addresses that point to other
-.!C3%'T%2NC@.A-.3s. 2!'M assumes at least the
-.!C3%'T%2NC@.A-.3 is addressa0le, and then can further
address the ta0le 0ased upon its 1ength field.
6.2.8 Extended System Description Table (XSDT)
The A!-T provides identical functionalit( to the 3!-T 0ut accommodates ph(sical addresses of
-.!C3%'T%2N @.A-.3s that are larger than 32&0its. Notice that 0oth the A!-T and the 3!-T can 0e
pointed to 0( the 3!-' structure. An AC'%&compati0le 2! must use the A!-T if present.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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Ta!le A-/ 1xtended S)ste% 5escription Ta!le 6ields >=S5T?
6ield
<)te
Length
<)te
3ffse
t 5escription
@eader
!ignature " OA!-TM. !ignature for the ./tended !(stem -escription Ta0le.
1ength " " 1ength, in 0(tes, of the entire ta0le. The length implies the
num0er of .ntr( fields =n> at the end of the ta0le.
3evision 4 8 4
Checksum 4 6 .ntire ta0le must sum to Hero.
2.M%- + 4 2.M %-
2.M Ta0le %- 8 4+ 5or the A!-T, the ta0le %- is the manufacture model %-. This
field must match the 2.M Ta0le %- in the 5A-T.
2.M 3evision " 2" 2.M revision of A!-T ta0le for supplied 2.M Ta0le %-.
Creator %- " 28 Dendor %- of utilit( that created the ta0le. 5or ta0les
containing -efinition ;locks, this is the %- for the A!1
Compiler.
Creator 3evision " 32 3evision of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the revision for the A!1 Compiler.
.ntr( 8[n 3+ An arra( of +"&0it ph(sical addresses that point to other
-.!C3%'T%2NC@.A-.3s. 2!'M assumes at least the
-.!C3%'T%2NC@.A-.3 is addressa0le, and then can
further address the ta0le 0ased upon its 1ength field.
6.2.9 Fixed ACPI Description Table (FADT)
The 5i/ed AC'% -escription Ta0le =5A-T> defines various fi/ed hardware AC'% information vital to an
AC'%&compati0le 2!, such as the 0ase address for the following hardware registers 0locks<
'M4aC.DTC;1E, 'M40C.DTC;1E, 'M4aCCNTC;1E, 'M40CCNTC;1E, 'M2CCNTC;1E,
'MCTM3C;1E, $'.C;1E, and $'.4C;1E.
The 5A-T also has a pointer to the -!-T that contains the -ifferentiated -efinition ;lock, which in turn
provides varia0le information to an AC'%&compati0le 2! concerning the 0ase s(stem design.
All fields in the 5A-T that provide hardware addresses provide processor&relative ph(sical addresses.
Ta!le A-, 6ixed ACPI 5escription Ta!le >6A5T? 6or%at
6ield
<)te
Length
<)te
3ffse
t 5escription
@eader
!ignature " O5AC'M. !ignature for the 5i/ed AC'% -escription Ta0le.
1ength " " 1ength, in 0(tes, of the entire 5A-T.
3evision 4 8 "
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4+" Advanced Configuration and 'ower %nterface !pecification
6ield
<)te
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3ffse
t 5escription
Checksum 4 6 .ntire ta0le must sum to Hero.
2.M%- + 4 2.M %-
2.M Ta0le %- 8 4+ 5or the 5A-T, the ta0le %- is the manufacture model %-. This field
must match the 2.M Ta0le %- in the 3!-T.
2.M 3evision " 2" 2.M revision of 5A-T for supplied 2.M Ta0le %-.
Creator %- " 28 Dendor %- of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the %- for the A!1 Compiler.
Creator 3evision " 32 3evision of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the revision for the A!1 Compiler.
5%3MWA3.CCT31 " 3+ 'h(sical memor( address =&" $;> of the 5AC!, where 2!'M and
5irmware e/change control information. !ee section *.2.+, J3oot
!(stem -escription Ta0le,L for a description of the 5AC!.
-!-T " " 'h(sical memor( address =&" $;> of the -!-T.
3eserved 4 "" AC'% 4. defined this offset as a field named %NTCM2-.1, which
was eliminated in AC'% 2.. 'latforms should set this field to Hero
0ut field values of one are also allowed to maintain compati0ilit(
with AC'% 4..
'referredC'MC'rofile 4 "* This field is set 0( the 2.M to conve( the preferred power
management profile to 2!'M. 2!'M can use this field to set
default power management polic( parameters during 2!
installation.
5ield Dalues<
,nspecified
4 -esktop
2 Mo0ile
3 Workstation
" .nterprise !erver
* !2@2 !erver
+ Appliance 'C
9 'erformance !erver
)9 3eserved
!C%C%NT 2 "+ !(stem vector the !C% interrupt is wired to in 82*6 mode. 2n
s(stems that do not contain the 82*6, this field contains the $lo0al
!(stem interrupt num0er of the !C% interrupt. 2!'M is re:uired to
treat the AC'% !C% interrupt as a shara0le, level, active low
interrupt.
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6ield
<)te
Length
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3ffse
t 5escription
!M%CCM- " "8 !(stem port address of the !M% Command 'ort. -uring AC'% 2!
initialiHation, 2!'M can determine that the AC'% hardware
registers are owned 0( !M% =0( wa( of the !C%C.N 0it>, in which
case the AC'% 2! issues the AC'%C.NA;1. command to the
!M%CCM- port. The !C%C.N 0it effectivel( tracks the ownership
of the AC'% hardware registers. 2!'M issues commands to the
!M%CCM- port s(nchronousl( from the 0oot processor. This field
is reserved and must 0e Hero on s(stem that does not support
!(stem Management mode.
AC'%C.NA;1. 4 *2 The value to write to !M%CCM- to disa0le !M% ownership of the
AC'% hardware registers. The last action !M% does to relin:uish
ownership is to set the !C%C.N 0it. -uring the 2! initialiHation
process, 2!'M will s(nchronousl( wait for the transfer of !M%
ownership to complete, so the AC'% s(stem releases !M%
ownership as :uickl( as possi0le. This field is reserved and must 0e
Hero on s(stems that do not support 1egac( Mode.
AC'%C-%!A;1. 4 *3 The value to write to !M%CCM- to re&ena0le !M% ownership of the
AC'% hardware registers. This can onl( 0e done when ownership
was originall( ac:uired from !M% 0( 2!'M using
AC'%C.NA;1.. An 2! can hand ownership 0ack to !M% 0(
relin:uishing use to the AC'% hardware registers, masking off all
!C% interrupts, clearing the !C%C.N 0it and then writing
AC'%C-%!A;1. to the !M%CCM- port from the 0oot processor.
This field is reserved and must 0e Hero on s(stems that do not
support 1egac( Mode.
!";%2!C3.G 4 *" The value to write to !M%CCM- to enter the !";%2! state. The
!";%2! state provides an alternate wa( to enter the !" state where
the firmware saves and restores the memor( conte/t. A value of
Hero in !";%2!C5 indicates !";%2!C3.G is not supported. =!ee
Ta0le *&42.>
'!TAT.CCNT 4 ** %f non&Hero, this field contains the value 2!'M writes to the
!M%CCM- register to assume processor performance state control
responsi0ilit(.
'M4aC.DTC;1E " *+ !(stem port address of the 'M4a .vent 3egister ;lock. !ee section
".9.3.4, J'M4 .vent $rouping,L for a hardware description la(out
of this register 0lock. This is a re:uired field. This field is
superseded 0( the AC'M4aC.DTC;1E field.
'M40C.DTC;1E " + !(stem port address of the 'M40 .vent 3egister ;lock. !ee section
".9.3.4, J'M4 .vent $rouping,L for a hardware description la(out
of this register 0lock. This field is optionalK if this register 0lock is
not supported, this field contains Hero. This field is superseded 0(
the AC'M40C.DTC;1E field.
'M4aCCNTC;1E " +" !(stem port address of the 'M4a Control 3egister ;lock. !ee
section ".9.3.2, J'M4 Control $rouping,L for a hardware
description la(out of this register 0lock. This is a re:uired field.
This field is superseded 0( the AC'M4aCCNTC;1E field.
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4++ Advanced Configuration and 'ower %nterface !pecification
6ield
<)te
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<)te
3ffse
t 5escription
'M40CCNTC;1E " +8 !(stem port address of the 'M40 Control 3egister ;lock. !ee
section ".9.3.2, J'M4 Control $rouping,L for a hardware
description la(out of this register 0lock. This field is optionalK if
this register 0lock is not supported, this field contains Hero. This
field is superseded 0( the AC'M40CCNTC;1E field.
'M2CCNTC;1E " 92 !(stem port address of the 'M2 Control 3egister ;lock. !ee
section ".9.3.", J'M2 Control ='M2CCNT>,L for a hardware
description la(out of this register 0lock. This field is optionalK if
this register 0lock is not supported, this field contains Hero. This
field is superseded 0( the AC'M2CCNTC;1E field.
'MCTM3C;1E " 9+ !(stem port address of the 'ower Management Timer Control
3egister ;lock. !ee section ".9.3.3, J'ower Management Timer
='MCTM3>,L for a hardware description la(out of this register
0lock. This is a re:uired field. This field is superseded 0( the
AC'MCTM3C;1E field.
$'.C;1E " 8 !(stem port address of $eneral&'urpose .vent 3egister ;lock.
!ee section ".9.".4, J$eneral&'urpose .vent 3egister ;locks,L for a
hardware description of this register 0lock. This is an optional fieldK
if this register 0lock is not supported, this field contains Hero. This
field is superseded 0( the AC$'.C;1E field.
$'.4C;1E " 8" !(stem port address of $eneral&'urpose .vent 4 3egister ;lock.
!ee section ".9.".4, J$eneral&'urpose .vent 3egister ;locks,L for a
hardware description of this register 0lock. This is an optional fieldK
if this register 0lock is not supported, this field contains Hero. This
field is superseded 0( the AC$'.4C;1E field.
'M4C.DTC1.N 4 88 Num0er of 0(tes decoded 0( 'M4aC.DTC;1E and, if supported,
'M40C .DTC;1E. This value is ".
'M4CCNTC1.N 4 86 Num0er of 0(tes decoded 0( 'M4aCCNTC;1E and, if supported,
'M40CCNTC;1E. This value is 2.
'M2CCNTC1.N 4 6 Num0er of 0(tes decoded 0( 'M2CCNTC;1E. !upport for the
'M2 register 0lock is optional. %f supported, this value is 4. %f not
supported, this field contains Hero.
'MCTM3C1.N 4 64 Num0er of 0(tes decoded 0( 'MCTM3C;1E. This fieldMs value
must 0e ".
$'.C;1EC1.N 4 62 Num0er of 0(tes decoded 0( $'.C;1E. The value is a non&
negative multiple of 2.
$'.4C;1EC1.N 4 63 Num0er of 0(tes decoded 0( $'.4C;1E. The value is a non&
negative multiple of 2.
$'.4C;A!. 4 6" 2ffset within the AC'% general&purpose event model where $'.4
0ased events start.
C!TCCNT 4 6* %f non&Hero, this field contains the value 2!'M writes to the
!M%CCM- register to indicate 2! support for the CC!T o0#ect and
C !tates Changed notification.
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'C1D12C1AT 2 6+ The worst&case hardware latenc(, in microseconds, to enter and e/it
a C2 state. A value ) 4 indicates the s(stem does not support a
C2 state.
'C1D13C1AT 2 68 The worst&case hardware latenc(, in microseconds, to enter and e/it
a C3 state. A value ) 4 indicates the s(stem does not support a
C3 state.
51,!@C!%?. 2 4 %f W;%ND-\, the value of this field is the num0er of flush strides
that need to 0e read =using cachea0le addresses> to completel( flush
dirt( lines from an( processorMs memor( caches. Notice that the
value in 51,!@C!T3%-. is t(picall( the smallest cache line width
on an( of the processorMs caches =for more information, see the
51,!@C!T3%-. field definition>. %f the s(stem does not support a
method for flushing the processorMs caches, then 51,!@C!%?. and
W;%ND- are set to Hero. Notice that this method of flushing the
processor caches has limitations, and W;%ND-\4 is the preferred
wa( to flush the processors caches. This value is t(picall( at least 2
times the cache siHe. The ma/imum allowed value for
51,!@C!%?. multiplied 0( 51,!@C!T3%-. is 2 M; for a
t(pical ma/imum supported cache siHe of 4 M;. 1arger cache siHes
are supported using W;%ND-\4.
This value is ignored if W;%ND-\4.
This field is maintained for AC'% 4. processor compati0ilit( on
e/isting s(stems. 'rocessors in new AC'%&compati0le s(stems are
re:uired to support the W;%ND- function and indicate this to
2!'M 0( setting the W;%ND- field \ 4.
51,!@C!T3%-. 2 42 %f W;%ND-\, the value of this field is the cache line width, in
0(tes, of the processorMs memor( caches. This value is t(picall( the
smallest cache line width on an( of the processorMs caches. 5or
more information, see the description of the 51,!@C!%?. field.
This value is ignored if W;%ND-\4.
This field is maintained for AC'% 4. processor compati0ilit( on
e/isting s(stems. 'rocessors in new AC'%&compati0le s(stems are
re:uired to support the W;%ND- function and indicate this to
2!'M 0( setting the W;%ND- field \ 4.
-,TSC255!.T 4 4" The Hero&0ased inde/ of where the processorMs dut( c(cle setting is
within the processorMs 'CCNT register.
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-,TSCW%-T@ 4 4* The 0it width of the processorMs dut( c(cle setting value in the
'CCNT register. .ach processorMs dut( c(cle setting allows the
software to select a nominal processor fre:uenc( 0elow its a0solute
fre:uenc( as defined 0(<
T@T1C.N \ 4
;5 [ -CF=2
-,TSCW%-T@
>
Where<
;5I;ase fre:uenc(
-CI-ut( c(cle setting
When T@T1C.N is , the processor runs at its a0solute ;5. A
-,TSCW%-T@ value of indicates that processor dut( c(cle is
not supported and the processor continuousl( runs at its 0ase
fre:uenc(.
-ASCA13M 4 4+ The 3TC CM2! 3AM inde/ to the da(&of&month alarm value. %f
this field contains a Hero, then the 3TC da( of the month alarm
feature is not supported. %f this field has a non&Hero value, then this
field contains an inde/ into 3TC 3AM space that 2!'M can use to
program the da( of the month alarm. !ee section ".9.2.", J3eal
Time Clock Alarm,L for a description of how the hardware works.
M2NCA13M 4 49 The 3TC CM2! 3AM inde/ to the month of (ear alarm value. %f
this field contains a Hero, then the 3TC month of the (ear alarm
feature is not supported. %f this field has a non&Hero value, then this
field contains an inde/ into 3TC 3AM space that 2!'M can use to
program the month of the (ear alarm. %f this feature is supported,
then the -ASCA13M feature must 0e supported also.
C.NT,3S 4 48 The 3TC CM2! 3AM inde/ to the centur( of data value =hundred
and thousand (ear decimals>. %f this field contains a Hero, then the
3TC centenar( feature is not supported. %f this field has a non&Hero
value, then this field contains an inde/ into 3TC 3AM space that
2!'M can use to program the centenar( field.
%A'CC;22TCA3C@ 2 46 %A&'C ;oot Architecture 5lags. !ee Ta0le *&44 for a description of
this field.
3eserved 4 444 Must 0e .
5lags " 442 5i/ed feature flags. !ee Ta0le *&4 for a description of this field.
3.!.TC3.$ 42 44+ The address of the reset register represented in $eneric Address
!tructure format =!ee section ".9.3.+, J3eset 3egister,L for a
description of the reset mechanism.>
0ote< 2nl( !(stem %F2 space, !(stem Memor( space and 'C%
Configuration space =0us Y> are valid for values for
AddressC!paceC%-. Also, 3egisterC;itCWidth must 0e 8 and
3egisterC;itC2ffset must 0e .
3.!.TCDA1,. 4 428 %ndicates the value to write to the 3.!.TC3.$ port to reset the
s(stem. =!ee section ".9.3.+, J3eset 3egister,L for a description of
the reset mechanism.>
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3eserved 3 426 Must 0e .
AC5%3MWA3.CCT31 8 432 +"0it ph(sical address of the 5AC!.
AC-!-T 8 4" +"0it ph(sical address of the -!-T.
AC'M4aC.DTC;1E 42 4"8 ./tended address of the 'M4a .vent 3egister ;lock, represented in
$eneric Address !tructure format. !ee section ".9.3.4, J'M4 .vent
$rouping,L for a hardware description la(out of this register 0lock.
This is a re:uired field.
AC'M40C.DTC;1E 42 4+ ./tended address of the 'M40 .vent 3egister ;lock, represented
in $eneric Address !tructure format. !ee section ".9.3.4, J'M4
.vent $rouping,L for a hardware description la(out of this register
0lock. This field is optionalK if this register 0lock is not supported,
this field contains Hero.
AC'M4aCCNTC;1E 42 492 ./tended address of the 'M4a Control 3egister ;lock, represented
in $eneric Address !tructure format. !ee section ".9.3.2, J'M4
Control $rouping,L for a hardware description la(out of this
register 0lock. This is a re:uired field.
AC'M40CCNTC;1E 42 48" ./tended address of the 'M40 Control 3egister ;lock, represented
in $eneric Address !tructure format. !ee section ".9.3.2, J'M4
Control $rouping,L for a hardware description la(out of this
register 0lock. This field is optionalK if this register 0lock is not
supported, this field contains Hero.
AC'M2CCNTC;1E 42 46+ ./tended address of the 'ower Management 2 Control 3egister
;lock, represented in $eneric Address !tructure format. !ee
section ".9.3.", J'M2 Control ='M2CCNT>,L for a hardware
description la(out of this register 0lock. This field is optionalK if
this register 0lock is not supported, this field contains Hero.
AC'MCTM3C;1E 42 28 ./tended address of the 'ower Management Timer Control
3egister ;lock, represented in $eneric Address !tructure format.
!ee section ".9.3.3, J'ower Management Timer ='MCTM3>,L for a
hardware description la(out of this register 0lock. This is a re:uired
field.
AC$'.C;1E 42 22 ./tended address of the $eneral&'urpose .vent 3egister ;lock,
represented in $eneric Address !tructure format. !ee section *.2.8,
J5i/ed AC'% -escription Ta0le,L for a hardware description of this
register 0lock. This is an optional fieldK if this register 0lock is not
supported, this field contains Hero.
AC$'.4C;1E 42 232 ./tended address of the $eneral&'urpose .vent 4 3egister ;lock,
represented in $eneric Address !tructure format. !ee section *.2.8,
J5i/ed AC'% -escription Ta0le,L for a hardware description of this
register 0lock. This is an optional fieldK if this register 0lock is not
supported, this field contains Hero.
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49 Advanced Configuration and 'ower %nterface !pecification
Ta!le A-+$ 6ixed ACPI 5escription Ta!le 6ixed 6eature 6lags
6ACP - 6lag
<it
Length
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W;%ND- 4 'rocessor properl( implements a functional e:uivalent to the
W;%ND- %A&32 instruction.
%f set, signifies that the W;%ND- instruction correctl( flushes the
processor caches, maintains memor( coherenc(, and upon
completion of the instruction, all caches for the current processor
contain no cached data other than what 2!'M references and
allows to 0e cached. %f this flag is not set, the AC'% 2! is
responsi0le for disa0ling all AC'% features that need this function.
This field is maintained for AC'% 4. processor compati0ilit( on
e/isting s(stems. 'rocessors in new AC'%&compati0le s(stems are
re:uired to support this function and indicate this to 2!'M 0(
setting this field.
W;%ND-C51,!@ 4 4 %f set, indicates that the hardware flushes all caches on the
W;%ND- instruction and maintains memor( coherenc(, 0ut does
not guarantee the caches are invalidated. This provides the
complete semantics of the W;%ND- instruction, and provides
enough to support the s(stem sleeping states. %f neither of the
W;%ND- flags is set, the s(stem will re:uire 51,!@C!%?. and
51,!@C!T3%-. to support sleeping states. %f the 51,!@
parameters are also not supported, the machine cannot support
sleeping states !4, !2, or !3.
'32CCC4 4 2 A one indicates that the C4 power state is supported on all
processors.
'C1D12C,' 4 3 A Hero indicates that the C2 power state is configured to onl( work
on a uniprocessor =,'> s(stem. A one indicates that the C2 power
state is configured to work on a ,' or multiprocessor =M'> s(stem.
'W3C;,TT2N 4 " A Hero indicates the power 0utton is handled as a fi/ed feature
programming modelK a one indicates the power 0utton is handled as
a control method device. %f the s(stem does not have a power
0utton, this value would 0e J4L and no sleep 0utton device would
0e present.
%ndependent of the value of this field, the presence of a power
0utton device in the namespace indicates to 2!'M that the power
0utton is handled as a control method device.
!1'C;,TT2N 4 * A Hero indicates the sleep 0utton is handled as a fi/ed feature
programming modelK a one indicates the sleep 0utton is handled as
a control method device.
%f the s(stem does not have a sleep 0utton, this value would 0e J4L
and no sleep 0utton device would 0e present.
%ndependent of the value of this field, the presence of a sleep 0utton
device in the namespace indicates to 2!'M that the sleep 0utton is
handled as a control method device.
5%AC3TC 4 + A Hero indicates the 3TC wake status is supported in fi/ed register
spaceK a one indicates the 3TC wake status is not supported in fi/ed
register space.
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3TCC!" 4 9 %ndicates whether the 3TC alarm function can wake the s(stem
from the !" state. The 3TC must 0e a0le to wake the s(stem from
an !4, !2, or !3 sleep state. The 3TC alarm can optionall( support
waking the s(stem from the !" state, as indicated 0( this value.
TM3CDA1C.AT 4 8 A Hero indicates TM3CDA1 is implemented as a 2"&0it value. A
one indicates TM3CDA1 is implemented as a 32&0it value. The
TM3C!T! 0it is set when the most significant 0it of the TM3CDA1
toggles.
-CECCA' 4 6 A Hero indicates that the s(stem cannot support docking. A one
indicates that the s(stem can support docking. Notice that this flag
does not indicate whether or not a docking station is currentl(
presentK it onl( indicates that the s(stem is capa0le of docking.
3.!.TC3.$C!,' 4 4 %f set, indicates the s(stem supports s(stem reset via the 5A-T
3.!.TC3.$ as descri0ed in section ".9. 3.+, J3eset 3egister.L
!.A1.-CCA!. 4 44 !(stem T(pe Attri0ute. %f set indicates that the s(stem has no
internal e/pansion capa0ilities and the case is sealed.
@.A-1.!! 4 42 !(stem T(pe Attri0ute. %f set indicates the s(stem cannot detect the
monitor or ke(0oard F mouse devices.
C',C!WC!1' 4 43 %f set, indicates to 2!'M that a processor native instruction must
0e e/ecuted after writing the !1'CTS'/ register.
'C%C.A'CWAE 4 4" %f set, indicates the platform supports the 'C%.A'CWAE.C!T! 0it
in the 'M4 !tatus register and the 'C%.A'CWAE.C.N 0it in the
'M4 .na0le register.
,!.C'1AT523MCC1
2CE
4 4*
A value of one indicates that 2!'M should use a platform provided
timer to drive an( monotonicall( non&decreasing counters, such as
2!'M performance counter services. Which particular platform
timer will 0e used is 2!'M specific, however, it is recommended
that the timer used is 0ased on the following algorithm< %f the
@'.T is e/posed to 2!'M, 2!'M should use the @'.T.
2therwise, 2!'M will use the AC'% power management timer. A
value of one indicates that the platform is known to have a
correctl( implemented AC'% power management timer.
A platform ma( choose to set this flag if a internal processor clock
=or clocks in a multi&processor configuration> cannot provide
consistent monotonicall( non&decreasing counters.
Note< %f a value of Hero is present, 2!'M ma( ar0itraril( choose to
use an internal processor clock or a platform timer clock for these
operations. That is, a Hero does not impl( that 2!'M will
necessaril( use the internal processor clock to generate a
monotonicall( non&decreasing counter to the s(stem.
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!"C3TCC!T!CDA1%- 4 4+
A one indicates that the contents of the 3TCC!T! flag is valid
when waking the s(stem from !".
!ee Ta0le "&44 I 'M4 !tatus 3egisters 5i/ed @ardware 5eature
!tatus ;its for more information. !ome e/isting s(stems do not
relia0l( set this input toda(, and this 0it allows 2!'M to
differentiate correctl( functioning platforms from platforms with
this errata.
3.M2T.C'2W.3C2
NCCA'A;1.
4 49
A one indicates that the platform is compati0le with remote power
on.
That is, the platform supports 2!'M leaving $'. wake events
armed prior to an !* transition. !ome e/isting platforms do not
relia0l( transition to !* with wake events ena0led =for e/ample, the
platform ma( immediatel( generate a spurious wake event after
completing the !* transition>. This flag allows 2!'M to
differentiate correctl( functioning platforms from platforms with
this t(pe of errata.
523C.C
A'%CCC1,!T.3CM2
-.1
4 48
A one indicates that all local A'%Cs must 0e configured for the
cluster destination model when delivering interrupts in logical
mode.
%f this 0it is set, then logical mode interrupt deliver( operation ma(
0e undefined until 2!'M has moved all local A'%Cs to the cluster
model.
Note that the cluster destination model doesnMt appl( to %tanium
processor local !A'%Cs. This 0it is intended for /A'%C 0ased
machines that re:uire the cluster destination model even when 8 or
fewer local A'%Cs are present in the machine.
523C.CA'%CC'@S!%
CA1C-.!T%NAT%2NC
M2-.
4 46 A one indicates that all local /A'%Cs must 0e configured for
ph(sical destination mode. %f this 0it is set, interrupt deliver(
operation in logical destination mode is undefined. 2n machines
that contain fewer than 8 local /A'%Cs or that do not use the
/A'%C architecture, this 0it is ignored.
3eserved 42 2
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Preferred PM Profle System Types
The following descriptions of preferred power management profile s(stem t(pes are to 0e used as a guide
for setting the 'referredC'MC'rofile field in the 5A-T. 2!'M can use this field to set default power
management polic( parameters during 2! installation.
5esktop. A single user, full featured, stationar( computing device that resides on or near an individualMs
work area. Most often contains one processor. Must 0e connected to AC power to function. This device is
used to perform work that is considered mainstream corporate or home computing =for e/ample, word
processing, %nternet 0rowsing, spreadsheets, and so on>.
Mo!ile. A single&user, full&featured, porta0le computing device that is capa0le of running on 0atteries or
other power storage devices to perform its normal functions. Most often contains one processor. This
device performs the same task set as a desktop. @owever it ma( have limitations dues to its siHe, thermal
re:uirements, andFor power source life.
:orkstation. A single&user, full&featured, stationar( computing device that resides on or near an
individualMs work area. 2ften contains more than one processor. Must 0e connected to AC power to
function. This device is used to perform large :uantities of computations in support of such work as
CA-FCAM and other graphics&intensive applications.
1nterprise Server. A multi&user, stationar( computing device that fre:uentl( resides in a separate, often
speciall( designed, room. Will almost alwa(s contain more than one processor. Must 0e connected to AC
power to function. This device is used to support large&scale networking, data0ase, communications, or
financial operations within a corporation or government.
S3H3 Server. A multi&user, stationar( computing device that fre:uentl( resides in a separate area or room
in a small or home office. Ma( contain more than one processor. Must 0e connected to AC power to
function. This device is generall( used to support all of the networking, data0ase, communications, and
financial operations of a small office or home office.
Appliance PC. A device specificall( designed to operate in a low&noise, high&availa0ilit( environment such
as a consumerMs living rooms or famil( room. Most often contains one processor. This categor( also
includes home %nternet gatewa(s, We0 pads, set top 0o/es and other devices that support AC'%. Must 0e
connected to AC power to function. Normall( the( are sealed case st(le and ma( onl( perform a su0set of
the tasks normall( associated with toda(Ms personal computers.
Perfor%ance Server A multi&user stationar( computing device that fre:uentl( resides in a separate, often
speciall( designed room. Will often contain more than one processor. Must 0e connected to AC power to
function. This device is used in an environment where power savings features are willing to 0e sacrificed
for 0etter performance and :uicker responsiveness.
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System Type Attributes
This set of flags is used 0( the 2! to assist in determining assumptions a0out power and device
management. These flags are read at 0oot time and are used to make decisions a0out power management
and device settings. 5or e/ample, a s(stem that has the !.A1.-CCA!. 0it set ma( take a ver( aggressive
low noise polic( toward thermal management. %n another e/ample an 2! might not load video, ke(0oard or
mouse drivers on a @.A-1.!! s(stem.
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IA-PC Boot Architecture Flags
This set of flags is used 0( an 2! to guide the assumptions it can make in initialiHing hardware on %A&'C
platforms. These flags are used 0( an 2! at 0oot time =0efore the 2! is capa0le of providing an operating
environment suita0le for parsing the AC'% namespace> to determine the code paths to take during 0oot. %n
%A&'C platforms with reduced legac( hardware, the 2! can skip code paths for legac( devices if none are
present. 5or e/ample, if there are no %!A devices, an 2! could skip code that assumes the presence of these
devices and their associated resources. These flags are used independentl( of the AC'% namespace. The
presence of other devices must 0e descri0ed in the AC'% namespace as specified in section +,
JConfiguration.L These flags pertain onl( to %A&'C platforms. 2n other s(stem architectures, the entire
field should 0e set to .
Ta!le A-++ 6ixed ACPI 5escription Ta!le <oot Architecture 6lags
<33TDA"CH
<it
length
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offset 5escription
1.$ACSC-.D%C.! 4 %f set, indicates that the mother0oard supports user&visi0le
devices on the 1'C or %!A 0us. ,ser&visi0le devices are devices
that have end&user accessi0le connectors =for e/ample, 1'T
port>, or devices for which the 2! must load a device driver so
that an end&user application can use a device. %f clear, the 2!
ma( assume there are no such devices and that all devices in the
s(stem can 0e detected e/clusivel( via industr( standard device
enumeration mechanisms =including the AC'% namespace>.
8"2 4 4 %f set, indicates that the mother0oard contains support for a port
+ and +" 0ased ke(0oard controller, usuall( implemented as an
8"2 or e:uivalent micro&controller.
D$A Not 'resent 4 2 %f set, indicates to 2!'M that it must not 0lindl( pro0e the D$A
hardware =that responds to MM%2 addresses Ah&;5555h
and %2 ports 3;h&3;;h and 3Ch&3-5h> that ma( cause
machine check on this s(stem. %f clear, indicates to 2!'M that it
is safe to pro0e the D$A hardware..
3eserved 43 3 Must 0e .
6.2.10 Firmware ACPI Control Structure (FACS)
The 5irmware AC'% Control !tructure =5AC!> is a structure in readFwrite memor( that the ;%2! reserves
for AC'% usage. This structure is passed to an AC'%&compati0le 2! using the 5A-T. 5or more information
a0out the 5A-T 5%3MWA3.CCT31 field, see section *.2.6, J5i/ed AC'% -escription Ta0le =5A-T>.L
The ;%2! aligns the 5AC! on a +"&0(te 0oundar( an(where within the s(stemMs memor( address space.
The memor( where the 5AC! structure resides must not 0e reported as s(stem Address3angeMemor( in
the s(stem address map. 5or e/ample, the .82 address map reporting interface would report the region as
Address3ange3eserved. 5or more information a0out s(stem address map reporting interfaces, see
section 4", J!(stem Address Map %nterfaces.L
Ta!le A-+& 6ir%ware ACPI Control Structure >6ACS?
6ield
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3ffset 5escription
!ignature " O5AC!M
1ength " " 1ength, in 0(tes, of the entire 5irmware AC'% Control
!tructure. This value is +" 0(tes or larger.
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@ardware !ignature " 8 The value of the s(stemMs Jhardware signatureL at last 0oot.
This value is calculated 0( the ;%2! on a 0est effort 0asis to
indicate the 0ase hardware configuration of the s(stem such
that different 0ase hardware configurations can have different
hardware signature values. 2!'M uses this information in
waking from an !" state, 0( comparing the current hardware
signature to the signature values saved in the non&volatile sleep
image. %f the values are not the same, 2!'M assumes that the
saved non&volatile image is from a different hardware
configuration and cannot 0e restored.
5irmwareCWakingC
Dector
" 42 This field is superseded 0( the AC5irmwareCWakingCDector
field.
The 32&0it address field where 2!'M puts its waking vector.
;efore transitioning the s(stem into a glo0al sleeping state,
2!'M fills in this field with the ph(sical memor( address of
an 2!&specific wake function. -uring '2!T, the platform
firmware first checks if the value of the
AC5irmwareCWakingCDector field is non&Hero and if so
transfers control to 2!'M as outlined in the
AC5irmwareCWakingCvector field description 0elow. %f the
AC5irmwareCWakingCDector field is Hero then the platform
firmware checks the value of this field and if it is non&Hero,
transfers control to the specified address.
2n 'Cs, the wake function address is in memor( 0elow 4 M;
and the control is transferred while in real mode. 2!'MMs
wake function restores the processorsM conte/t.
5or %A&'C platforms, the following e/ample shows the
relationship 0etween the ph(sical address in the 5irmware
Waking Dector and the real mode address the ;%2! #umps to.
%f, for e/ample, the ph(sical address is /423"*, then the
;%2! must #ump to real mode address /423"</*. %n
general this relationship is
3eal&mode address \
'h(sical address))" < 'h(sical address and /5
Notice that on %A&'C platforms, A2 must 0e ena0led when
the ;%2! #umps to the real mode address derived from the
ph(sical address stored in the 5irmware Waking Dector.
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48 Advanced Configuration and 'ower %nterface !pecification
Ta!le A-+& 6ir%ware ACPI Control Structure >6ACS? (continued)
6ield
<)te
Length
<)te
3ffset 5escription
$lo0alC1ock " 4+ This field contains the $lo0al 1ock used to s(nchroniHe access
to shared hardware resources 0etween the 2!'M environment
and an e/ternal controller environment =for e/ample, the !M%
environment>. This lock is owned e/clusivel( 0( either 2!'M
or the firmware at an( one time. When ownership of the lock is
attempted, it might 0e 0us(, in which case the re:uesting
environment e/its and waits for the signal that the lock has
0een released. 5or e/ample, the $lo0al 1ock can 0e used to
protect an em0edded controller interface such that onl( 2!'M
or the firmware will access the em0edded controller interface
at an( one time. !ee section *.2.4.4, J$lo0al 1ock,L for more
information on ac:uiring and releasing the $lo0al 1ock.
5lags " 2 5irmware control structure flags. !ee Ta0le *&43 for a
description of this field.
AC5irmwareCWakin
gCDector
8 2" +"&0it ph(sical address of 2!'MMs Waking Dector.
;efore transitioning the s(stem into a glo0al sleeping state,
2!'M fills in this field with the ph(sical memor( address of
an 2!&specific wake function. -uring '2!T, the platform
firmware checks if the value of this field is non&Hero and if so
transfers control to 2!'M 0( #umping to this address. 'rior to
transferring control, the e/ecution environment must 0e
configured as follows<
Memor( address translation F paging and interrupts must 0e
disa0led.
5or %A 32&0it platforms, a "$; flat address space for all
segment registers and .51A$!.%5 set to .
5or +"&0it %tanium
TM
&0ased platforms, the processor must have
psr.i, psr.it, psr.dt, and psr.rt set to . !ee the Intel? Itani'm
TM

Arc1itect're Software De2eloper@s (an'al for more
information.
%f this field is Hero then 2!'M checks the
5irmwareCWakingCDector field as outlined a0ove.
Dersion 4 32 4IDersion of this ta0le
3eserved 34 33 This value is Hero.
Ta!le A-+# 6ir%ware Control Structure 6eature 6lags
6ACS M 6lag
<it
Length
<it
3ffset 5escription
!";%2!C5 4 %ndicates whether the platform supports !";%2!C3.G. %f
!";%2!C3.G is not supported, 2!'M must 0e a0le to save
and restore the memor( state in order to use the !" state.
3eserved 34 4 The value is Hero.
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6.2.10.1
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482 Advanced Configuration and 'ower %nterface !pecification
Global Lock
The purpose of the AC'% $lo0al 1ock is to provide mutual e/clusion 0etween the host 2! and the 32M
;%2!. The $lo0al 1ock is a 32&0it =-W23-> value in readFwrite memor( located within the 5AC! and is
accessed and updated 0( 0oth the 2! environment and the !M% environment in a defined manner to
provide an e/clusive lock. Note< this is not a pointer to the $lo0al 1ock, it is the act'al memor( location
of the lock. The 5AC! and $lo0al 1ock ma( 0e located an(where in ph(sical memor(.
;( convention, this lock is used to ensure that while one environment is accessing some hardware, the
other environment is not. ;( this convention, when ownership of the lock fails 0ecause the other
environment owns it, the re:uesting environment sets a JpendingL state within the lock, e/its its attempt to
ac:uire the lock, and waits for the owning environment to signal that the lock has 0een released 0efore
attempting to ac:uire the lock again. When releasing the lock, if the pending 0it in the lock is set after the
lock is released, a signal is sent via an interrupt mechanism to the other environment to inform it that the
lock has 0een released. -uring interrupt handling for the Jlock releasedL event within the corresponding
environment, if the lock ownership were still desired an attempt to ac:uire the lock would 0e made. %f
ownership is not ac:uired, then the environment must again set JpendingL and wait for another Jlock
releaseL signal.
The ta0le 0elow shows the encoding of the $lo0al 1ock -W23- in memor(.
Ta!le A-+( ;lo!al Lock Structure within the 6ACS
6ield
<it
Length
<it
3ffset 5escription
'ending 4 Non&Hero indicates that a re:uest for ownership of the
$lo0al 1ock is pending.
2wned 4 4 Non&Hero indicates that the $lo0al 1ock is 2wned.
3eserved 3 2 3eserved for future use.
The following code se:uence is used 0( 0oth 2!'M and the firmware to ac:uire ownership of the $lo0al
1ock. %f non&Hero is returned 0( the function, the caller has 0een granted ownership of the $lo0al 1ock and
can proceed. %f Hero is returned 0( the function, the caller has not 0een granted ownership of the $lo0al
1ock, the JpendingL 0it has 0een set, and the caller must wait until it is signaled 0( an interrupt event that
the lock is availa0le 0efore attempting to ac:uire access again.
Note< %n the e/amples that follow, the J$lo0al1ockL varia0le is a pointer that has 0een previousl(
initialiHed to point to the 32&0it $lo0al 1ock location within the 5AC!.
&c8uire:lobal6oc+>
mov ec-$ :lobal6oc+ K ec- L &ddre22 of :lobal 6oc+ in 5&)S
ac84(> mov ea-$ Mec-N K :et current value of :lobal 6oc+
mov ed-$ ea-
and ed-$ not 4 K )lear pendin, bit
bt2 ed-$ 4 K )hec+ and 2et owner bit
adc ed-$ ( K #f owned$ 2et pendin, bit
loc+ cmp-ch, dword ptrMec-N$ ed- K &ttempt to 2et new value
9nC 2hort ac84( K #f not 2et$ tr1 a,ain
cmp dl$ F K Wa2 it ac8uired or mar+ed pendin,O
2bb ea-$ ea- K ac8uired L E4$ pendin, L (
ret
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<he followin, code 2e8uence i2 u2ed b1 0SP; and the firmware to relea2e owner2hip of the
:lobal 6oc+. #f nonECero i2 returned$ the caller mu2t rai2e the appropriate event to the
other environment to 2i,nal that the :lobal 6oc+ i2 now free. Dependin, on the
environment$ thi2 2i,nalin, i2 done b1 2ettin, the either the :B6_R6S or B#0S_R6S within
their re2pective hardware re,i2ter 2pace2. <hi2 2i,nal onl1 occur2 when the other
environment attempted to ac8uire owner2hip while the loc+ wa2 owned.
Relea2e:lobal6oc+>
mov ec-$ :lobal6oc+ K ec- L &ddre22 of :lobal 6oc+ in 5&)S
rel4(> mov ea-$ Mec-N K :et current value of :lobal 6oc+
mov ed-$ ea-
and ed-$ not (Fh K )lear owner and pendin, field
loc+ cmp-ch, dword ptrMec-N$ ed- K &ttempt to 2et it
9nC 2hort rel4( K #f not 2et$ tr1 a,ain
and ea-$ 4 K Wa2 pendin, 2etO
K #f one i2 returned (we were pendin,) the caller mu2t 2i,nal that the
K loc+ ha2 been relea2ed u2in, either :B6_R6S or B#0S_R6S a2 appropriate
ret
Although using the $lo0al 1ock allows various hardware resources to 0e shared, it is important to notice
that its usage when there is ownership contention could entail a significant amount of s(stem overhead as
well as waits of an indeterminate amount of time to ac:uire ownership of the $lo0al 1ock. 5or this reason,
implementations should tr( to design the hardware to keep the re:uired usage of the $lo0al 1ock to a
minimum.
The $lo0al 1ock is re:uired whenever a logical register in the hardware is shared. 5or e/ample, if 0it is
used 0( AC'% =2!'M> and 0it 4 of the same register is used 0( !M%, then access to that register needs to 0e
protected under the $lo0al 1ock, ensuring that the registerMs contents do not change from underneath one
environment while the other is making changes to it. !imilarl( if the entire register is shared, as the case
might 0e for the em0edded controller interface, access to the register needs to 0e protected under the $lo0al
1ock.
6.2.11 Defnition Blocks
A -efinition ;lock consists of data in AM1 format =see section *." J-efinition ;lock .ncodingL> and
contains information a0out hardware implementation details in the form of AM1 o0#ects that contain data,
AM1 code, or other AM1 o0#ects. The top&level organiHation of this information after a definition 0lock is
loaded is name&tagged in a hierarchical namespace.
2!'M JloadsL or JunloadsL an entire definition 0lock as a logical unit. 2!'M will load a definition 0lock
either as a result of e/ecuting the AM1 Load>? or LoadTa!le>? operator or encountering a ta0le definition
during initialiHation. -uring initialiHation, 2!'M loads the -ifferentiated !(stem -escription Ta0le
=-!-T>, which contains the -ifferentiated -efinition ;lock, using the -!-T pointer retrieved from the
5A-T. 2!'M will load other definition 0locks during initialiHation as a result of encountering !econdar(
!(stem -escription Ta0le =!!-T> definitions in the 3!-TFA!-T. The -!-T and !!-T are descri0ed in
the following sections.
As mentioned, the AM1 Load>? and LoadTa!le>? operators make it possi0le for a -efinition ;lock to load
other -efinition ;locks, either staticall( or d(namicall(, where the( in turn can either define new s(stem
attri0utes or, in some cases, 0uild on prior definitions. Although this gives the hardware the a0ilit( to var(
widel( in implementation, it also confines it to reasona0le 0oundaries. %n some cases, the -efinition ;lock
format can descri0e onl( specific and well&understood variances. %n other cases, it permits implementations
to 0e e/pressi0le onl( 0( means of a specified set of J0uilt inL operators. 5or e/ample, the -efinition ;lock
has 0uilt in operators for %F2 space.
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48" Advanced Configuration and 'ower %nterface !pecification
%n theor(, it might 0e possi0le to define something like 'C% configuration space in a -efinition ;lock 0(
0uilding it from %F2 space, 0ut that is not the goal of the definition 0lock. !uch a space is usuall( defined as
a J0uilt inL operator.
!ome AM1 operators perform simple functions, and others encompass comple/ functions. The power of
the -efinition 0lock comes from its a0ilit( to allow these operations to 0e glued together in numerous
wa(s, to provide functionalit( to 2!'M.
The AM1 operators defined in this specification are intended to allow man( useful hardware designs to 0e
easil( e/pressed, not to allow all hardware designs to 0e e/pressed.
Note< To accommodate addressing 0e(ond 32 0its, the integer t(pe was e/panded to +" 0its in AC'% 2.,
see section 49.2.*, JA!1 -ata T(pesL. ./isting AC'% definition 0lock implementations ma( contain an
inherent assumption of a 32&0it integer width. Therefore, to maintain 0ackwards compati0ilit(, 2!'M uses
the 3evision field, in the header portion of s(stem description ta0les containing -efinition ;locks, to
determine whether integers declared within the -efinition ;lock are to 0e evaluated as 32&0it or +"&0it
values. A 3evision field value greater than or e:ual to 2 signifies that integers declared within the
-efinition ;lock are to 0e evaluated as +"&0it values. The A!1 writer specifies the value for the -efinition
;lock ta0le headerMs 3evision field via the A!1 -efinition;lockMs Compliance$e2ision field. !ee section
49.*.2+, J-efinition;lock =-eclare -efinition ;lock>L, for more information. %t is the responsi0ilit( of the
A!1 writer to ensure the -efinition ;lockMs compati0ilit( with the corresponding integer width when
setting the Compliance$e2ision field.
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6.2.11.1
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48+ Advanced Configuration and 'ower %nterface !pecification
Diferentiated System Description Table (DSDT)
The -ifferentiated !(stem -escription Ta0le =-!-T> is part of the s(stem fi/ed description. The -!-T is
comprised of a s(stem description ta0le header followed 0( data in -efinition ;lock format. This
-efinition ;lock is like all other -efinition ;locks, with the e/ception that it cannot 0e unloaded. !ee
section *.2.44, J-efinition ;locks,L for a description of -efinition ;locks.
Ta!le A-+A 5ifferentiated S)ste% 5escription Ta!le 6ields >5S5T?
6ield
<)te
Length
<)te
3ffset 5escription
@eader
!ignature " O-!-T.M !ignature for the -ifferentiated !(stem -escription
Ta0le.
1ength " " 1ength, in 0(tes, of the entire -!-T =including the header>.
3evision 4 8 2
Checksum 4 6 .ntire ta0le must sum to Hero.
2.M%- + 4 2.M %-
2.M Ta0le %- 8 4+ The manufacture model %-.
2.M 3evision " 2" 2.M revision of -!-T for supplied 2.M Ta0le %-.
Creator %- " 28 Dendor %- for the A!1 Compiler.
Creator 3evision " 32 3evision num0er of the A!1 Compiler.
-efinition ;lock n 3+ n 0(tes of AM1 code =see section *.", J-efinition ;lock
.ncodingL>
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6.2.11.2
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488 Advanced Configuration and 'ower %nterface !pecification
Secondary System Description Table (SSDT)
!econdar( !(stem -escription Ta0les =!!-T> are a continuation of the -!-T. The !!-T is comprised of a
s(stem description ta0le header followed 0( data in -efinition ;lock format. There can 0e multiple !!-Ts
present. 2!'M first loads the -!-T and then loads each !!-T. This allows the 2.M to provide the 0ase
support in one ta0le and add smaller s(stem options in other ta0les. 5or e/ample, the 2.M might put
d(namic o0#ect definitions into a secondar( ta0le such that the firmware can construct the d(namic
information at 0oot without needing to edit the static -!-T. A !!-T can onl( rel( on the -!-T 0eing
loaded prior to it.
Ta!le A-+- Secondar) S)ste% 5escription Ta!le 6ields >SS5T?
6ield
<)te
Length
<)te
3ffset 5escription
@eader
!ignature " O!!-T.M !ignature for the !econdar( !(stem -escription Ta0le.
1ength " " 1ength, in 0(tes, of the entire !!-T =including the header>.
3evision 4 8 2
Checksum 4 6 .ntire ta0le must sum to Hero.
2.M%- + 4 2.M %-
2.M Ta0le %- 8 4+ The manufacture model %-.
2.M 3evision " 2" 2.M revision of -!-T for supplied 2.M Ta0le %-.
Creator %- " 28 Dendor %- for the A!1 Compiler.
Creator 3evision " 32 3evision num0er of the A!1 Compiler.
-efinition ;lock n 3+ n 0(tes of AM1 code =see section *." , J-efinition ;lock
.ncodingL>
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6.2.11.3
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46 Advanced Configuration and 'ower %nterface !pecification
Persistent System Description Table (PSDT)
The ta0le signature, J'!-TL refers to the 'ersistent !(stem -escription Ta0le ='!-T> defined in the AC'%
4. specification. The '!-T was #udged to provide no specific 0enefit and as such has 0een deleted from
this version of the AC'% specification. 2!'M will evaluate a ta0le with the J'!-TL signature in like
manner to the evaluation of an !!-T as descri0ed in section *.2.44.2, J!econdar( !(stem -escription
Ta0le.L
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6.2.11.4
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462 Advanced Configuration and 'ower %nterface !pecification
Multiple APIC Description Table (MADT)
The AC'% interrupt model descri0es all interrupts for the entire s(stem in a uniform interrupt model
implementation. !upported interrupt models include the 'C&ATIcompati0le dual 82*6 interrupt controller
and, for %ntel processor&0ased s(stems, the %ntel Advanced 'rogramma0le %nterrupt Controller =A'%C> and
%ntel !treamlined Advanced 'rogramma0le %nterrupt Controller =!A'%C>. The choice of the interrupt
model=s> to support is up to the platform designer. The interrupt model cannot 0e d(namicall( changed 0(
the s(stem firmwareK 2!'M will choose which model to use and install support for that model at the time
of installation. %f a platform supports 0oth models, an 2! will install support for one model or the otherK it
will not mi/ models. Multi&0oot capa0ilit( is a feature in man( modern operating s(stems. This means that
a s(stem ma( have multiple operating s(stems or multiple instances of an 2! installed at an( one time.
'latform designers must allow for this.
This section descri0es the format of the Multiple A'%C -escription Ta0le =MA-T>, which provides 2!'M
with information necessar( for operation on s(stems with A'%C or !A'%C implementations.
AC'% represents all interrupts as JflatL values known as glo0al s(stem interrupts. Therefore to support
A'%Cs or !A'%Cs on an AC'%&ena0led s(stem, each used A'%C or !A'%C interrupt input must 0e mapped
to the glo0al s(stem interrupt value used 0( AC'%. !ee !ection *.2.42. $lo0al !(stem %nterrupts,L for a
description of $lo0al !(stem %nterrupts.
Additional support is re:uired to handle various multi&processor functions that A'%C or !A'%C
implementations might support =for e/ample, identif(ing each processorMs local A'%C %->.
All addresses in the MA-T are processor&relative ph(sical addresses.
Ta!le A-+. Multiple APIC 5escription Ta!le >MA5T? 6or%at
6ield
<)te
Length
<)te
3ffset 5escription
@eader
!ignature " OA'%C.M !ignature for the Multiple A'%C -escription Ta0le.
1ength " " 1ength, in 0(tes, of the entire MA-T.
3evision 4 8 2
Checksum 4 6 .ntire ta0le must sum to Hero.
2.M%- + 4 2.M %-
2.M Ta0le %- 8 4+ 5or the MA-T, the ta0le %- is the manufacturer model %-.
2.M 3evision " 2" 2.M revision of MA-T for supplied 2.M Ta0le %-.
Creator %- " 28 Dendor %- of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the %- for the A!1 Compiler.
Creator 3evision " 32 3evision of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the revision for the A!1 Compiler.
1ocal A'%C
Address
" 3+ The 32&0it ph(sical address at which each processor can access
its local A'%C.
5lags " " Multiple A'%C flags. !ee Ta0le *&48 for a description of this
field.
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6ield
<)te
Length
<)te
3ffset 5escription
A'%C !tructureVnW P "" A list of A'%C structures for this implementation. This list will
contain all of the %F2 A'%C, %F2 !A'%C, 1ocal A'%C, 1ocal
!A'%C, %nterrupt !ource 2verride, Non&maska0le %nterrupt
!ource, 1ocal A'%C NM% !ource, 1ocal A'%C Address 2verride,
and 'latform %nterrupt !ources structures needed to support this
platform. These structures are descri0ed in the following sections.
Ta!le A-+/ Multiple APIC 6lags
Multiple APIC
6lags
<it
Length
<it
3ffset 5escription
'CATCC2M'AT 4 A one indicates that the s(stem also has a 'C&AT&compati0le
dual&82*6 setup. The 82*6 vectors must 0e disa0led =that is,
masked> when ena0ling the AC'% A'%C operation.
3eserved 34 4 This value is Hero.
%mmediatel( after the 5lags value in the MA-T is a list of A'%C structures that declare the A'%C features
of the machine. The first 0(te of each structure declares the t(pe of that structure and the second 0(te
declares the length of that structure.
Ta!le A-+, APIC Structure T)pes
7alue 5escription
'rocessor 1ocal A'%C
4 %F2 A'%C
2 %nterrupt !ource 2verride
3 Non&maska0le %nterrupt !ource =NM%>
" 1ocal A'%C NM% !tructure
* 1ocal A'%C Address 2verride !tructure
+ %F2 !A'%C
9 1ocal !A'%C
8 'latform %nterrupt !ources
6&429 3eserved. 2!'M skips structures of the reserved t(pe.
428&2** 3eserved for 2.M use
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6.2.11.5
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Processor Local APIC
When using the A'%C interrupt model, each processor in the s(stem is re:uired to have a 'rocessor 1ocal
A'%C record and an AC'% 'rocessor o0#ect. 2!'M does not e/pect the information provided in this ta0le to
0e updated if the processor information changes during the lifespan of an 2! 0oot. While in the sleeping
state, processors are not allowed to 0e added, removed, nor can their A'%C %- or 5lags change. When a
processor is not present, the 'rocessor 1ocal A'%C information is either not reported or flagged as disa0led.
Ta!le A-&$ Processor Local APIC Structure
6ield
<)te
Length
<)te
3ffset 5escription
T(pe 4 'rocessor 1ocal A'%C structure
1ength 4 4 8
AC'% 'rocessor
%-
4 2 The 'rocessor%d for which this processor is listed in the AC'%
'rocessor declaration operator. 5or a definition of the 'rocessor
operator, see section 49.*.63, J'rocessor =-eclare 'rocessor>.L
A'%C %- 4 3 The processorMs local A'%C %-.
5lags " " 1ocal A'%C flags. !ee Ta0le *&24 for a description of this field.
Ta!le A-&+ Local APIC 6lags
LocalAPIC
6lags
<it
Length
<it
3ffset 5escription
.na0led 4 %f Hero, this processor is unusa0le, and the operating s(stem
support will not attempt to use it.
3eserved 34 4 Must 0e Hero.
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6.2.11.6
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I/O APIC
%n an A'%C implementation, there are one or more %F2 A'%Cs. .ach %F2 A'%C has a series of interrupt
inputs, referred to as %NT%n, where the value of n is from to the num0er of the last interrupt input on the
%F2 A'%C. The %F2 A'%C structure declares which glo0al s(stem interrupts are uni:uel( associated with the
%F2 A'%C interrupt inputs. There is one %F2 A'%C structure for each %F2 A'%C in the s(stem. 5or more
information on glo0al s(stem interrupts see !ection *.2.42, J$lo0al !(stem %nterrupts.L
Ta!le A-&& I@3 APIC Structure
6ield
<)te
Length
<)te
3ffset 5escription
T(pe 4 4 %F2 A'%C structure
1ength 4 4 42
%F2 A'%C %- 4 2 The %F2 A'%CMs %-.
3eserved 4 3
%F2 A'%C Address " " The 32&0it ph(sical address to access this %F2 A'%C. .ach %F2
A'%C resides at a uni:ue address.
$lo0al !(stem
%nterrupt ;ase
" 8 The glo0al s(stem interrupt num0er where this %F2 A'%CMs
interrupt inputs start. The num0er of interrupt inputs is determined
0( the %F2 A'%CMs (ax $edir *ntry register.
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6.2.11.7
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Platforms with APIC and Dual 8259 Support
!(stems that support 0oth A'%C and dual 82*6 interrupt models must map glo0al s(stem interrupts &4* to
the 82*6 %3Gs &4*, e/cept where %nterrupt !ource 2verrides are provided =see section *.2.4.8, J%nterrupt
!ource 2verridesL>. This means that %F2 A'%C interrupt inputs &4* must 0e mapped to glo0al s(stem
interrupts &4* and have identical sources as the 82*6 %3Gs &4* unless overrides are used. This allows a
platform to support 2!'M implementations that use the A'%C model as well as 2!'M implementations
that use the 82*6 model =2!'M will onl( use one modelK it will not mi/ models>.
When 2!'M supports the 82*6 model, it will assume that all interrupt descriptors reporting glo0al s(stem
interrupts &4* correspond to 82*6 %3Gs. %n the 82*6 model all glo0al s(stem interrupts greater than 4* are
ignored. %f 2!'M implements A'%C support, it will ena0le the A'%C as descri0ed 0( the A'%C
specification and will use all reported glo0al s(stem interrupts that fall within the limits of the interrupt
inputs defined 0( the %F2 A'%C structures. 5or more information on hardware resource configuration see
section +, JConfiguration.L
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2 Advanced Configuration and 'ower %nterface !pecification
6.2.11.8
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Interrupt Source Overrides
%nterrupt !ource 2verrides are necessar( to descri0e variances 0etween the %A&'C standard dual 82*6
interrupt definition and the platformMs implementation.
%t is assumed that the %!A interrupts will 0e identit(&mapped into the first %F2 A'%C sources. Most e/isting
A'%C designs, however, will contain at least one e/ception to this assumption. The %nterrupt !ource
2verride !tructure is provided in order to descri0e these e/ceptions. %t is not necessar( to provide an
%nterrupt !ource 2verride for ever( %!A interrupt. 2nl( those that are not identit(&mapped onto the A'%C
interrupt inputs need 0e descri0ed.
0ote< This specification onl( supports overriding %!A interrupt sources.
5or e/ample, if (our machine has the %!A 'rogramma0le %nterrupt Timer ='%T> connected to %!A %3G ,
0ut in A'%C mode, it is connected to %F2 A'%C interrupt input 2, then (ou would need an %nterrupt !ource
2verride where the source entr( is OM and the $lo0al !(stem %nterrupt is O2.M
Ta!le A-&# Interrupt Source 3verride Structure
6ield
<)te
Length
<)te
3ffset 5escription
T(pe 4 2 %nterrupt !ource 2verride
1ength 4 4 4
;us 4 2 Constant, meaning %!A
!ource 4 3 ;us&relative interrupt source =%3G>
$lo0al !(stem
%nterrupt
" " The $lo0al !(stem %nterrupt that this 0us&relative interrupt source
will signal.
5lags 2 8 M'! %NT% flags. !ee Ta0le *&2" for a description of this field.
The M'! %NT% flags listed in Ta0le *&2" are identical to the flags used in Ta0le "&4 of the M'! version
4." specifications. The 'olarit( flags are the '2 0its and the Trigger Mode flags are the .1 0its.
Ta!le A-&( MPS I0TI 6lags
Local APIC -
6lags
<it
Length
<it
3ffset 5escription
'olarit( 2 'olarit( of the A'%C %F2 input signals<
Conforms to the specifications of the 0us
=5or e/ample, .%!A is active&low for level&triggered interrupts>
4 Active high
4 3eserved
44 Active low
Trigger Mode 2 2 Trigger mode of the A'%C %F2 %nput signals<
Conforms to specifications of the 0us
=5or e/ample, %!A is edge&triggered>
4 .dge&triggered
4 3eserved
44 1evel&triggered
3eserved 42 " Must 0e Hero.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
22 Advanced Configuration and 'ower %nterface !pecification
%nterrupt !ource 2verrides are also necessar( when an identit( mapped interrupt input has a non&standard
polarit(.
0oteH Sou must have an interrupt source override entr( for the %3G mapped to the !C% interrupt if this %3G
is not identit( mapped. This entr( will override the value in !C%C%NT in 5A-T. 5or e/ample, if !C% is
connected to %3G 6 in '%C mode and %3G 6 is connected to %NT%N44 in A'%C mode, (ou should have 6 in
!C%C%NT in the 5A-T and an interrupt source override entr( mapping %3G 6 to %NT%N44.
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6.2.11.9
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2" Advanced Configuration and 'ower %nterface !pecification
Non-Maskable Interrupt Sources (NMIs)
This structure allows a platform designer to specif( which %F2 =!>A'%C interrupt inputs should 0e ena0led
as non&maska0le. An( source that is non&maska0le will not 0e availa0le for use 0( devices.
Ta!le A-&A 0on-%aska!le Source Structure
6ield
<)te
Length
<)te
3ffset 5escription
T(pe 4 3 NM%
1ength 4 4 8
5lags 2 2 !ame as M'! %NT% flags
$lo0al !(stem
%nterrupt
" " The $lo0al !(stem %nterrupt that this NM% will signal.
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6.2.11.10
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2+ Advanced Configuration and 'ower %nterface !pecification
Local APIC NMI
This structure descri0es the 1ocal A'%C interrupt input =1%NTn> that NM% is connected to for each of the
processors in the s(stem where such a connection e/ists. This information is needed 0( 2!'M to ena0le
the appropriate local A'%C entr(.
.ach 1ocal A'%C NM% connection re:uires a separate 1ocal A'%C NM% structure. 5or e/ample, if the
platform has " processors with %- &3 and NM% is connected 1%NT4 for processor 3 and 2, two 1ocal A'%C
NM% entries would 0e needed in the MA-T.
Ta!le A-&- Local APIC 0MI Structure
6ield
<)te
Length
<)te
3ffset 5escription
T(pe 4 " 1ocal A'%C NM% !tructure
1ength 4 4 +
AC'% 'rocessor
%-
4 2 'rocessor %- corresponding to the %- listed in the processor
o0#ect. A value of /55 signifies that this applies to all processors
in the machine.
5lags 2 3 M'! %NT% flags. !ee Ta0le *&2" for a description of this field.
1ocal A'%C
1%NTY
4 * 1ocal A'%C interrupt input 1%NTn to which NM% is connected.
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6.2.11.11
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28 Advanced Configuration and 'ower %nterface !pecification
Local APIC Address Override Structure
This optional structure supports +"&0it s(stems 0( providing an override of the ph(sical address of the local
A'%C in the MA-TMsta0le header, which is defined as a 32&0it field.
%f defined, 2!'M must use the address specified in this structure for all local A'%Cs =and local !A'%Cs>,
rather than the address contained in the MA-TMs ta0le header. 2nl( one 1ocal A'%C Address 2verride
!tructure ma( 0e defined.
Ta!le A-&. Local APIC Address 3verride Structure
6ield
<)te
Length
<)te
3ffset 5escription
T(pe 4 * 1ocal A'%C Address 2verride !tructure
1ength 4 4 42
3eserved 2 2 3eserved =must 0e set to Hero>
1ocal A'%C
Address
8 " 'h(sical address of 1ocal A'%C. 5or %tanium
TM
&0ased s(stems, this
field contains the starting address of the 'rocessor %nterrupt ;lock.
!ee the Intel? Itani'm
TM
Arc1itect're Software De2eloper@s
(an'al for more information.
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6.2.11.12
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24 Advanced Configuration and 'ower %nterface !pecification
I/O SAPIC Structure
The %F2 !A'%C structure is ver( similar to the %F2 A'%C structure. %f 0oth %F2 A'%C and %F2 !A'%C
structures e/ist for a specific A'%C %-, the information in the %F2 !A'%C structure must 0e used.
The %F2 !A'%C structure uses the %F2CA'%CC%- field as defined in the %F2 A'%C ta0le. The DectorC;ase
field remains unchanged 0ut has 0een moved. The %F2 A'%C address has 0een deleted. A new address and
reserved field have 0een added.
Ta!le A-&/ I@3 SAPIC Structure
6ield
<)te
Length
<)te
3ffset 5escription
T(pe 4 + %F2 !A'%C !tructure
1ength 4 4 4+
%F2 A'%C %- 4 2 %F2 !A'%C %-
3eserved 4 3 3eserved =must 0e Hero>
$lo0al !(stem
%nterrupt ;ase
" " The glo0al s(stem interrupt num0er where this %F2 !A'%CMs
interrupt inputs start. The num0er of interrupt inputs is determined
0( the %F2 !A'%CMs (ax $edir *ntry register.
%F2 !A'%C
Address
8 8 The +"&0it ph(sical address to access this %F2 !A'%C. .ach %F2
!A'%C resides at a uni:ue address.
%f defined, 2!'M must use the information contained in the %F2 !A'%C structure instead of the information
from the %F2 A'%C structure.
%f 0oth %F2 A'%C and an %F2 !A'%C structures e/ist in an MA-T, the 2.MF;%2! writer must prevent
Jmi/ingL %F2 A'%C and %F2 !A'%C addresses. This is done 0( ensuring that there are at least as man( %F2
!A'%C structures as %F2 A'%C structures and that ever( %F2 A'%C structure has a corresponding %F2 !A'%C
structure =same A'%C %->.
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6.2.11.13
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242 Advanced Configuration and 'ower %nterface !pecification
Local SAPIC Structure
The 'rocessor local !A'%C structure is ver( similar to the processor local A'%C structure. When using the
!A'%C interrupt model, each processor in the s(stem is re:uired to have a 'rocessor 1ocal !A'%C record
and an AC'% 'rocessor o0#ect. 2!'M does not e/pect the information provided in this ta0le to 0e updated
if the processor information changes during the lifespan of an 2! 0oot. While in the sleeping state,
processors are not allowed to 0e added, removed, nor can their !A'%C %- or 5lags change. When a
processor is not present, the 'rocessor 1ocal !A'%C information is either not reported or flagged as
disa0led.
Ta!le A-&, Processor Local SAPIC Structure
6ield
<)te
Length
<)te
3ffset 5escription
T(pe 4 9 'rocessor 1ocal !A'%C structure
1ength 4 4 1ength of the 1ocal !A'%C !tructure in 0(tes.
AC'% 'rocessor
%-
4 2 2!'M associates the 1ocal !A'%C !tructure with a processor
o0#ect declared in the namespace using the Processor statement 0(
matching the processor o0#ectMs 'rocessor%- value with this field.
5or a definition of the 'rocessor o0#ect, see section 49.*.63,
J'rocessor =-eclare 'rocessor>.L
1ocal !A'%C %- 4 3 The processorMs local !A'%C %-
1ocal !A'%C
.%-
4 " The processorMs local !A'%C .%-
3eserved 3 * 3eserved =must 0e set to Hero>
5lags " 8 1ocal !A'%C flags. !ee Ta0le *&24 for a description of this field.
AC'% 'rocessor
,%- Dalue
" 42
2!'M associates the 1ocal !A'%C !tructure with a processor
o0#ect declared in the namespace using the 5evice statement, when
the C,%- child o0#ect of the processor device evaluates to a
numeric value, 0( matching the numeric value with this field.
AC'% 'rocessor
,%- !tring
)\4 4+
2!'M associates the 1ocal !A'%C !tructure with a processor
o0#ect declared in the namespace using the 5evice statement, when
the C,%- child o0#ect of the processor device evaluates to a string,
0( matching the string with this field. This value is stored as a null&
terminated A!C%% string.
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6.2.11.14
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
24" Advanced Configuration and 'ower %nterface !pecification
Platform Interrupt Source Structure
The 'latform %nterrupt !ource structure is used to communicate which %F2 !A'%C interrupt inputs are
connected to the platform interrupt sources.
'latform Management %nterrupts ='M%s> are used to invoke platform firmware to handle various events
=similar to !M% in %A&32>. The %ntel] %tanium
TM
architecture permits the %F2 !A'%C to send a vector value
in the interrupt message of the 'M% t(pe. This value is specified in the %F2 !A'%C Dector field of the
'latform %nterrupt !ources !tructure.
%N%T messages cause processors to soft reset.
%f a platform can generate an interrupt after correcting platform errors =e.g., single 0it error correction>, the
interrupt input line used to signal such corrected errors is specified 0( the $lo0al !(stem %nterrupt field in
the following ta0le. !ome s(stems ma( restrict the retrieval of corrected platform error information to a
specific processor. %n such cases, the firmware indicates the processor that can retrieve the corrected
platform error information through the 'rocessor %- and .%- fields in the structure 0elow. 2!'M is
re:uired to program the %F2 !A'%C redirection ta0le entries with the 'rocessor %-, .%- values specified 0(
the AC'% s(stem firmware. 2n platforms where the retrieval of corrected platform error information can 0e
performed on an( processor, the firmware indicates this capa0ilit( 0( setting the C'.% 'rocessor 2verride
flag in the 'latform %nterrupt !ource 5lags field of the structure 0elow. %f the C'.% 'rocessor 2verride 5lag
is set, 2!'M uses the processor specified 0( 'rocessor %-, and .%- fields of the structure 0elow onl( as a
target processor hint and the error retrieval can 0e performed on an( processor in the s(stem. @owever,
firmware is re:uired to specif( valid values in 'rocessor %-, .%- fields to ensure 0ackward compati0ilit(.
%f the C'.% 'rocessor 2verride flag is clear, 2!'M ma( re#ect a e#ection re:uest for the processor that is
targeted for the corrected platform error interrupt. %f the C'.% 'rocessor 2verride flag is set, 2!'M can
retarget the corrected platform error interrupt to a different processor when the target processor is e#ected.
Note that the CMAT o0#ect can return a 0uffer containing 'latform %nterrupt !ource !tructure entries. %t is
allowed for such an entr( to refer to a $lo0al !(stem %nterrupt that is alread( specified 0( a 'latform
%nterrupt !ource !tructure provided through the static MA-T ta0le, provided the value of platform
interrupt source flags are identical.
3efer to the %tanium
TM
'rocessor 5amil( !(stem A0straction 1a(er =!A1> !pecification for details on
handling the Corrected 'latform .rror %nterrupt.
Ta!le A-#$ Platfor% Interrupt Sources Structure
6ield
<)te
Length
<)te
3ffset 5escription
T(pe 4 8 'latform %nterrupt !ource structure
1ength 4 4 4+
5lags 2 2 M'! %NT% flags. !ee Ta0le *&2" for a description of this field.
%nterrupt T(pe 4 " 4 'M%
2 %N%T
3 Corrected 'latform .rror %nterrupt
All other values are reserved.
'rocessor %- 4 * 'rocessor %- of destination.
'rocessor .%- 4 + 'rocessor .%- of destination.
%F2 !A'%C
Dector
4 9 Dalue that 2!'M must use to program the vector field of the %F2
!A'%C redirection ta0le entr( for entries with the 'M% interrupt
t(pe.
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6ield <)te
Length
<)te
3ffset 5escription
$lo0al !(stem
%nterrupt
" 8 The $lo0al !(stem %nterrupt that this platform interrupt will signal.
'latform
%nterrupt !ource
5lags
" 42 'latform %nterrupt !ource 5lags. !ee Ta0le *&34 for a description of
this field
Ta!le A-#+ Platfor% Interrupt Source 6lags
Platfor%
Interrupt Source
6lags
<it
Length
<it
3ffset 5escription
C'.% 'rocessor
2verride
4 When set, indicates that retrieval of error information is allowed
from an( processor and 2!'M is to use the information provided
0( the processor %-, .%- fields of the 'latform %nterrupt !ource
!tructure =Ta0le *&3> as a target processor hint.
3eserved 34 4 Must 0e Hero.
%NT%C $
.
.
.
23 %NT%C23
2" %NT%C &(
.
.
.
36 %NT%C4*

" %NT%C ($
.
*4 %NT%C44
.
** %NT%C23
2" input
%2A'%C
4+ input
%2A'%C
2" input
%2A'%C
$lo0al !(stem %nterrupt Dector
=ie AC'% 'n' %3GY >
%nterrupt %nput 1ines
on %2A'%C
O!(stem Dector ;aseM
reported in %2A'%C !truc
6igure A-# APICM;lo!al S)ste% Interrupts
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
24+ Advanced Configuration and 'ower %nterface !pecification
6.2.12 Global System Interrupts
$lo0al !(stem %nterrupts can 0e thought of as AC'% 'lug and 'la( %3G num0ers. The( are used to
virtualiHe interrupts in ta0les and in A!1 methods that perform resource allocation of interrupts. -o not
confuse glo0al s(stem interrupts with %!A %3Gs although in the case of the %A&'C 82*6 interrupts the(
correspond in a one&to&one fashion.
There are two interrupt models used in AC'%&ena0led s(stems.
The first model is the A'%C model. %n the A'%C model, the num0er of interrupt inputs supported 0( each
%F2 A'%C can var(. 2!'M determines the mapping of the $lo0al !(stem %nterrupts 0( determining how
man( interrupt inputs each %F2 A'%C supports and 0( determining the glo0al s(stem interrupt 0ase for each
%F2 A'%C as specified 0( the %F2 A'%C !tructure. 2!'M determines the num0er of interrupt inputs 0(
reading the Ma/ 3edirection register from the %F2 A'%C. The glo0al s(stem interrupts mapped to that %F2
A'%C 0egin at the glo0al s(stem interrupt 0ase and e/tending through the num0er of interrupts specified in
the Ma/ 3edirection register. This mapping is depicted in 5igure *&3.
There is e/actl( one %F2 A'%C structure per %F2 A'%C in the s(stem.
%3G
.
%3G3
.
%3G9
%38
.
%3G44
.
%3G4*
82*6 %!A %3Gs $lo0al !(stem %nterrupt Dector
=ie AC'% 'n' %3GY >
Master
82*6
!lave
82*6

8
4*
9
6igure A-( /&A,M;lo!al S)ste% Interrupts
The other interrupt model is the standard AT st(le mentioned a0ove which uses %!A %3Gs attached to a
master slave pair of 82*6 '%Cs. The s(stem vectors correspond to the %!A %3Gs. The %!A %3Gs and their
mappings to the 82*6 pair are part of the AT standard and are well defined. This mapping is depicted in
5igure *&".
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6.2.13 Smart Battery Table (SBST)
%f the platform supports 0atteries as defined 0( the !mart ;atter( !pecification 4. or 4.4, then an !mart
;atter( Ta0le =!;!T> is present. This ta0le indicates the energ( level trip points that the platform re:uires
for placing the s(stem into the specified sleeping state and the suggested energ( levels for warning the user
to transition the platform into a sleeping state. Notice that while !mart ;atteries can report either in current
=mAFmAh> or in energ( =mWFmWh>, 2!'M must set them to operate in energ( =mWFmWh> mode so that
the energ( levels specified in the !;!T can 0e used. 2!'M uses these ta0les with the capa0ilities of the
0atteries to determine the different trip points. 5or more precise definitions of these levels, see section
3.6.3, J;atter( $as $auge.L
Ta!le A-#& S%art <atter) 5escription Ta!le >S<ST? 6or%at
6ield
<)te
Length
<)te
3ffset 5escription
@eader
!ignature " O!;!T.M !ignature for the !mart ;atter( -escription Ta0le.
1ength " " 1ength, in 0(tes, of the entire !;!T
3evision 4 8 4
Checksum 4 6 .ntire ta0le must sum to Hero.
2.M%- + 4 2.M %-
2.M Ta0le %- 8 4+ 5or the !;!T, the ta0le %- is the manufacturer model %-.
2.M 3evision " 2" 2.M revision of !;!T for supplied 2.M Ta0le %-.
Creator %- " 28 Dendor %- of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the %- for the A!1 Compiler.
Creator 3evision " 32 3evision of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the revision for the A!1 Compiler.
Warning .nerg(
1evel
" 3+ 2.M suggested energ( level in milliWatt&hours =mWh> at which
2!'M warns the user.
1ow .nerg( 1evel " " 2.M suggested platform energ( level in mWh at which 2!'M
will transition the s(stem to a sleeping state.
Critical .nerg(
1evel
" "" 2.M suggested platform energ( level in mWh at which 2!'M
performs an emergenc( shutdown.
6.2.14 Embedded Controller Boot Resources Table (ECDT)
This optional ta0le provides the processor&relative, translated resources of an .m0edded Controller. The
presence of this ta0le allows 2!'M to provide .m0edded Controller operation region space access 0efore
the namespace has 0een evaluated. %f this ta0le is not provided, the .m0edded Controller region space will
not 0e availa0le until the .m0edded Controller device in the AM1 namespace has 0een discovered and
enumerated. The availa0ilit( of the region space can 0e detected 0( providing a C3.$ method o0#ect
underneath the .m0edded Controller device.
Ta!le A-## 1%!edded Controller <oot "esources Ta!le 6or%at
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248 Advanced Configuration and 'ower %nterface !pecification
6ield <)te
Length
<)te
3ffset 5escription
@eader
!ignature " O.C-T.M !ignature for the .m0edded Controller Ta0le.
1ength " " 1ength, in 0(tes, of the entire .m0edded Controller Ta0le
3evision 4 8 4
Checksum 4 6 .ntire ta0le must sum to Hero.
2.M%- + 4 2.M %-
2.M Ta0le %- 8 4+ 5or the .m0edded Controller Ta0le, the ta0le %- is the
manufacturer model %-.
2.M 3evision " 2" 2.M revision of .m0edded Controller Ta0le for supplied 2.M
Ta0le %-.
Creator %- " 28 Dendor %- of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the %- for the A!1 Compiler.
Creator 3evision " 32 3evision of utilit( that created the ta0le. 5or ta0les containing
-efinition ;locks, this is the revision for the A!1 Compiler.
.CCC2NT321 42 3+ Contains the processor relative address, represented in $eneric
Address !tructure format, of the .m0edded Controller
CommandF!tatus register.
0ote< 2nl( !(stem %F2 space and !(stem Memor( space are
valid for values for AddressC!paceC%-.
.CC-ATA 42 "8 Contains the processor&relative address, represented in $eneric
Address !tructure format, of the .m0edded Controller -ata
register.
0ote< 2nl( !(stem %F2 space and !(stem Memor( space are
valid for values for AddressC!paceC%-.
,%- " + ,ni:ue %-I!ame as the value returned 0( the C,%- under the
device in the namespace that represents this em0edded
controller.
$'.C;%T 4 +" The 0it assignment of the !C% interrupt within the $'./C!T!
register of a $'. 0lock descri0ed in the 5A-T that the
em0edded controller triggers.
.CC%- Daria0le +* A!C%%, null terminated, string that contains a full( :ualified
reference to the name space o0#ect that is this em0edded
controller device =for e/ample, JBBC!;.'C%.%!A..CL>. Guotes
are omitted in the data field.
AC'% 2!'M implementations supporting .m0edded Controller devices must also support the .C-T. AC'%
4. 2!'M implementation will not recogniHe or make use of the .C-T. The following e/ample code
shows how to detect whether the .m0edded Controller operation regions are availa0le in a manner that is
0ackward compati0le with prior versions of AC'%F2!'M.
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Device(%)()
!ame(R%:)$0ne2)
;ethod(_R%:$3)
#f(6e8ual(&r,($ F))
Store(&r,4$ R%:))
/
/
/
;ethod(%)&@$()
#f(6e8ual(R%:)$0ne2))
#f(6,reater%8ual(_R%@$3))
Return(0ne)
/
%l2e
Return(7ero)
/
Return(R%:))
/
/
To detect the availa0ilit( of the region, call the .CAD method. 5or e/ample<
#f (\_SB.P)#(.%)(.%)&@())
...re,ion2 are available...
/
el2e
...re,ion2 are not available...
/
6.2.15 System Resource Afnity Table (SRAT)
This optional ta0le provides information that allows 2!'M to associate processors and memor( ranges,
including ranges of memor( provided 0( hot&added memor( devices, with s(stem localities F pro/imit(
domains. 2n N,MA platforms, !3AT information ena0les 2!'M to optimall( configure the operating
s(stem during a point in 2! initialiHation when evaluation of o0#ects in the AC'% Namespace is not (et
possi0le. 2!'M evaluates the !3AT onl( during 2! initialiHation.
Ta!le A-#( Static "esource Affinit) Ta!le 6or%at
6ield <)te
Length
<)te
3ffset
5escription
@eader
!ignature " O!3ATM. !ignature for the !(stem 3esource Affinit( Ta0le.
1ength " " 1ength, in 0(tes, of the entire !3AT. The length implies the
num0er of .ntr( fields at the end of the ta0le
3evision 4 8 2
Checksum 4 6 .ntire ta0le must sum to Hero.
2.M%- + 4 2.M %-.
2.M Ta0le %- 8 4+ 5or the !(stem 3esource Affinit( Ta0le, the ta0le %- is the
manufacturer model %-.
2.M 3evision " 2" 2.M revision of !(stem 3esource Affinit( Ta0le for supplied
2.M Ta0le %-.
Creator %- " 28 Dendor %- of utilit( that created the ta0le.
Creator 3evision " 32 3evision of utilit( that created the ta0le.
3eserved " 3+ 3eserved to 0e 4 for 0ackward compati0ilit(
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
22 Advanced Configuration and 'ower %nterface !pecification
6ield <)te
Length
<)te
3ffset
5escription
3eserved 8 " 3eserved
!tatic 3esource
Allocation
!tructureVnW
&&& "8 A list of static resource allocation structures for the platform. !ee
section *.2.4*.4,L'rocessor 1ocal A'%CF!A'%C Affinit(
!tructureL and section *.2.4*.2 Memor( Affinit( !tructureL.
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6.2.15.1
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
222 Advanced Configuration and 'ower %nterface !pecification
Processor Local APIC/SAPIC Afnity Structure
The 'rocessor 1ocal A'%CF!A'%C Affinit( structure provides the association 0etween the A'%C %- or
!A'%C %-F.%- of a processor and the pro/imit( domain to which the processor 0elongs. Ta0le *&3*
provides the details of the 'rocessor 1ocal A'%CF!A'%C Affinit( structure.
Ta!le A-#A Processor Local APIC@SAPIC Affinit) Structure
6ield <)te
Length
<)te
3ffset
5escription
T(pe 4 'rocessor 1ocal A'%CF!A'%C Affinit( !tructure
1ength 4 4 4+
'ro/imit( -omain
V9<W
4 2 ;itV9<W of the pro/imit( domain to which the processor 0elongs.
A'%C %- 4 3 The processor local A'%C %-.
5lags " " 5lags I 'rocessor 1ocal A'%CF!A'%C Affinit( !tructure. !ee
Ta0le *&3+ for a description of this field.
1ocal !A'%C .%- 4 8 The processor local !A'%C .%-.
'ro/imit( -omain
V34<8W
3 6 ;itV34<8W of the pro/imit( domain to which the processor 0elongs.
3eserved " 42 3eserved
Ta!le A-#- 6lags M Processor Local APIC@SAPIC Affinit) Structure
6ield <it
Length
<it
3ffset
5escription
.na0led 4 %f clear, the 2!'M ignores the contents of the 'rocessor 1ocal
A'%CF!A'%C Affinit( !tructure. This allows s(stem firmware to
populate the !3AT with a static num0er of structures 0ut onl(
ena0le them as necessar(.
3eserved 34 4 Must 0e Hero.
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6.2.15.2
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
22" Advanced Configuration and 'ower %nterface !pecification
Memory Afnity Structure
The Memor( Affinit( structure provides the following topolog( information staticall( to the operating
s(stem<
The association 0etween a range of memor( and the pro/imit( domain to which it 0elongs
%nformation a0out whether the range of memor( can 0e hot&plugged.
Ta0le *&39 provides the details of the Memor( Affinit( structure.
Ta!le A-#. Me%or) Affinit) Structure
6ield <)te
Length
<)te
3ffset
5escription
T(pe 4 4 Memor( Affinit( !tructure
1ength 4 4 "
'ro/imit( -omain " 2 %nteger that represents the pro/imit( domain to which the
processor 0elongs
3eserved 2 + 3eserved
;ase Address 1ow " 8 1ow 32 ;its of the ;ase Address of the memor( range
;ase Address @igh " 42 @igh 32 ;its of the ;ase Address of the memor( range
1ength 1ow " 4+ 1ow 32 ;its of the length of the memor( range.
1ength @igh " 2 @igh 32 ;its of the length of the memor( range.
3eserved " 2" 3eserved.
5lags " 28 5lags I Memor( Affinit( !tructure. %ndicates whether the region
of memor( is ena0led and can 0e hot plugged. -etails in !ee
Ta0le *&38.
3eserved 8 32 3eserved.
Ta!le A-#/ 6lags M Me%or) Affinit) Structure
6ield <it
Length
<it
3ffset
5escription
.na0led 4 %f clear, the 2!'M ignores the contents of the Memor( Affinit(
!tructure. This allows s(stem firmware to populate the !3AT with
a static num0er of structures 0ut onl( ena0le then as necessar(.
@ot 'lugga0le
*
4 4 The information conve(ed 0( this 0it depends on the value of the
.na0led 0it.
%f the .na0led 0it is set and the @ot 'lugga0le 0it is also set. The
s(stem hardware supports hot&add and hot&remove of this memor(
region
%f the .na0led 0it is set and the @ot 'lugga0le 0it is clear, the
s(stem hardware does not support hot&add or hot&remove of this
memor( region.
%f the .na0led 0it is clear, the 2!'M will ignore the contents of
the Memor( Affinit( !tructure
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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6ield <it
Length
<it
3ffset
5escription
NonDolatile 4 2 %f set, the memor( region represents Non&Dolatile memor(
3eserved 26 3 Must 0e Hero.
6.2.16 System Locality Distance Information Table (SLIT)
This optional ta0le provides a matri/ that descri0es the relative distance =memor( latenc(> 0etween all
!(stem 1ocalities, which are also referred to as 'ro/imit( -omains. !(stems emplo(ing a Non ,niform
Memor( Access =N,MA> architecture contain collections of hardware resources including for e/ample,
processors, memor(, and %F2 0uses, that comprise what is known as a JN,MA nodeL. 'rocessor accesses
to memor( or %F2 resources within the local N,MA node is generall( faster than processor accesses to
memor( or %F2 resources outside of the local N,MA node.
The value of each .ntr(Vi,:W in the !1%T ta0le, where i represents a row of a matri/ and : represents a
column of a matri/, indicates the relative distances from !(stem 1ocalit( F 'ro/imit( -omain i to ever(
other !(stem 1ocalit( : in the s(stem =including itself>.
The i,: row and column values correlate to the value returned 0( the C'AM o0#ect in the AC'% namespace.
!ee section +.2.42, JC'AM ='ro/imit(>L for more information.
The entr( value is a one&0(te unsigned integer. The relative distance from !(stem 1ocalit( i to !(stem
1ocalit( : is the iD; E : entr( in the matri/, where N is the num0er of !(stem 1ocalities. ./cept for the
relative distance from a !(stem 1ocalit( to itself, each relative distance is stored twice in the matri/. This
provides the capa0ilit( to descri0e the scenario where the relative distances for the two directions 0etween
!(stem 1ocalities is different.
The diagonal elements of the matri/, the relative distances from a !(stem 1ocalit( to itself are normaliHed
to a value of 4. The relative distances for the non&diagonal elements are scaled to 0e relative to 4. 5or
e/ample, if the relative distance from !(stem 1ocalit( i to !(stem 1ocalit( : is 2.", a value of 2" is stored
in ta0le entr( iD;E : and in :D;E i, where N is the num0er of !(stem 1ocalities.
%f one localit( is unreacha0le from another, a value of 2** =/55> is stored in that ta0le entr(. -istance
values of &6 are reserved and have no meaning.
Ta!le A-#, SLIT 6or%at
6ield <)te
Length
<)te
3ffset
5escription
@eader
!ignature " O!1%TM. !ignature for the !(stem 1ocalit( -istance
%nformation Ta0le.
1ength " " 1ength, in 0(tes, of the entire !(stem 1ocalit( -istance
%nformation Ta0le.
3evision 4 8 4
Checksum 4 6 .ntire ta0le must sum to Hero.
2.M%- + 4 2.M %-.
2.M Ta0le %- 8 4+ 5or the !(stem 1ocalit( %nformation Ta0le, the ta0le %- is the
manufacturer model %-.
*
2n /8+&0ased platforms, the 2!'M uses the @ot 'lugga0le 0it to determine whether it should shift into
'A. mode to allow for insertion of hot&plug memor( with ph(sical addresses over " $;.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
22+ Advanced Configuration and 'ower %nterface !pecification
6ield <)te
Length
<)te
3ffset
5escription
2.M 3evision " 2" 2.M revision of !(stem 1ocalit( %nformation Ta0le for
supplied 2.M Ta0le %-.
Creator %- " 28 Dendor %- of utilit( that created the ta0le. 5or the -!-T,
3!-T, !!-T, and '!-T ta0les, this is the %- for the A!1
Compiler.
Creator 3evision " 32 3evision of utilit( that created the ta0le. 5or the -!-T,
3!-T, !!-T, and '!-T ta0les, this is the revision for the
A!1 Compiler.
Num0er of !(stem
1ocalities
8 3+ %ndicates the num0er of !(stem 1ocalities in the s(stem.
.ntr(VWVW 4 "" Matri/ entr( =,>, contains a value of 4.
N
.ntr(VWVNum0er of
!(stem 1ocalities&4W
4 Matri/ entr( =, Num0er of !(stem 1ocalities&4>
.ntr(V4WVW 4 Matri/ entr( =4,>
NN NN
.ntr(VNum0er of
!(stem 1ocalities&4W
VNum0er of !(stem
1ocalities&4W
4 Matri/ entr( =Num0er of !(stem 1ocalities&4, Num0er of
!(stem 1ocalities&4>, contains a value of 4
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6.3 ACPI Namespace
5or all -efinition ;locks, the s(stem maintains a single hierarchical namespace that it uses to refer to
o0#ects. All -efinition ;locks load into the same namespace. Although this allows one -efinition ;lock to
reference o0#ects and data from another =thus ena0ling interaction>, it also means that 2.Ms must take care
to avoid an( naming collisions
+
. 2nl( an unload operation of a -efinition ;lock can remove names from
the namespace, so a name collision in an attempt to load a -efinition ;lock is considered fatal. The
contents of the namespace changes onl( on a load or unload operation.
The namespace is hierarchical in nature, with each name allowing a collection of names J0elowL it. The
following naming conventions appl( to all names<
All names are a fi/ed 32 0its.
The first 0(te of a name is inclusive of< OAMIO?M, OCM, =/"4I/*A, /*5>.
The remaining three 0(tes of a name are inclusive of< OAMIO?M, OMIO6M, OCM, =/"4I/*A, /3I
/36, /*5>.
;( convention, when an A!1 compiler pads a name shorter than " characters, it is done so with
trailing underscores =OCM>. !ee the language definition for AM1 Name!eg in !ection 4+, JAC'%
!ource 1anguage 3eference.L
Names 0eginning with OCM are reserved 0( this specification. -efinition ;locks can onl( use names
0eginning with OCM as defined 0( this specification.
A name proceeded with OBM causes the name to refer to the root of the namespace =OBM is not part of
the 32&0it fi/ed&length name>.
A name proceeded with O^M causes the name to refer to the parent of the current namespace =O^M is
not part of the 32&0it fi/ed&length name>.
./cept for names preceded with a OBM, the current namespace determines where in the namespace hierarch(
a name 0eing created goes and where a name 0eing referenced is found. A name is located 0( finding the
matching name in the current namespace, and then in the parent namespace. %f the parent namespace does
not contain the name, the search continues recursivel( upwards until either the name is found or the
namespace does not have a parent =the root of the namespace>. This indicates that the name is not found
9
.
An attempt to access names in the parent of the root will result in the name not 0eing found.
There are two t(pes of namespace paths< an a0solute namespace path =that is, one that starts with a OBM
prefi/>, and a relative namespace path =that is, one that is relative to the current namespace>. The
namespace search rules discussed a0ove, onl( appl( to single Name!eg paths, which is a relative
namespace path. 5or those relative name paths that contain multiple Name!egs or 'arent 'refi/es, O^M, the
search rules do not appl(. %f the search rules do not appl( to a relative namespace path, the namespace
o0#ect is looked up relative to the current namespace. 5or e/ample<
ABCD FFsearch rules appl(
^ABCD FFsearch rules do not appl(
XYZ.ABCD FFsearch rules do not appl(
\XYZ.ABCD FFsearch rules do not appl(
+
5or the most part, since the name space is hierarchical, t(picall( the 0ulk of a d(namic definition file will
load into a different part of the hierarch(. The root of the name space and certain locations where
interaction is 0eing designed are the areas in which e/tra care must 0e taken.
9
,nless the operation 0eing performed is e/plicitl( prepared for failure in name resolution, this is
considered an error and ma( cause the s(stem to stop working.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
228 Advanced Configuration and 'ower %nterface !pecification
All name references use a 32&0it fi/ed&length name or use a Name ./tension prefi/ to concatenate multiple
32&0it fi/ed&length name components together. This is useful for referring to the name of an o0#ect, such as
a control method, that is not in the scope of the current namespace.
The figure 0elow shows a sample of the AC'% namespace after a -ifferentiated -efinition ;lock has 0een
loaded.
P
$
d
d
Root
G%PR
CP*1
GPI'1
%STA
%O&
%O..
G%SB
PCI1
%7I'
%CRS
I'$1
%A'R
%PR1
G%5P$
%-1!
%$1"
%-1(
H Processor Tree
H Processor 1 o0Iect
H Power resource for I'$1
H Method to return status of power resourse
H Method to turn on power resourse
H Method to turn off power resourse
H S,stem 0us tree
H PCI 0us
H 'e9ice I'
H Current resources )PCI 0us num0er+
H I'$1 de9ice
H PCI de9ice 83 function 8
H Power resource reJuirements for '1
H 5eneral purpose e9ents )5P%STS+
H Method to handle le9el 5P%STS4!
H Method to handle edge 5P%STS4"
H Method to handle le9el 5P%STS4(
P
$
d
Pac:age
Processor O0Iect
Power Resource
O0Iect
Bus/'e9ice O0Iect
'ata O0Iect
Control Method )AM- code+
#e,
6igure A-A 1xa%ple ACPI 0a%eSpace
Care must 0e taken when accessing namespace o0#ects using a relative single segment name 0ecause of the
namespace search rules. An attempt to access a relative o0#ect recurses toward the root until the o0#ect is
found or the root is encountered. This can cause unintentional results. 5or e/ample, using the namespace
descri0ed in 5igure *.*, attempting to access a CC3! named o0#ect from within the BC!;C.'C%.%-. will
have different results depending on if an a0solute or relative path name is used. %f an a0solute pathname is
specified =BC!;C.'C%.%-..CC3!> an error will result since the o0#ect does not e/ist. Access using a
single segment name =CC3!> will actuall( access the BC!;C.'C%.CC3! o0#ect. Notice that the access will
occur successfull( with no errors.
6.3.1 Predefned Root Namespaces
The following namespaces are defined under the namespace root.
Ta!le A-($ 0a%espaces 5efined 2nder the 0a%espace "oot
0a%e 5escription
GD;P1 $eneral events in $'. register 0lock.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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0a%e 5escription
GDP" AC'% 4. 'rocessor Namespace. AC'% 4. re:uires all 'rocessor o0#ects to 0e defined
under this namespace. AC'% allows 'rocessor o0#ect definitions under the BC!;
namespace. 'latforms ma( maintain the BC'3 namespace for compati0ilit( with AC'% 4.
operating s(stems. An AC'%&compati0le namespace ma( define 'rocessor o0#ects in either
the BC!; or BC'3 scope 0ut not 0oth.
5or more information a0out defining 'rocessor o0#ects, see section 8, J'rocessor 'ower
and 'erformance !tate Configuration and Control.L
GDS< All -eviceF;us 20#ects are defined under this namespace.
GDSI !(stem indicator o0#ects are defined under this namespace. 5or more information a0out
defining s(stem indicators, see section 6.4, BC!4 !(stem %ndicators.L
GDTI AC'% 4. Thermal ?one namespace. AC'% 4. re:uires all Thermal ?one o0#ects to 0e
defined under this namespace. Thermal ?one o0#ect definitions ma( now 0e defined under
the BC!; namespace. AC'%&compati0le s(stems ma( maintain the BCT? namespace for
compati0ilit( with AC'% 4. operating s(stems. An AC'%&compati0le namespace ma(
define Thermal ?one o0#ects in either the BC!; or BCT? scope 0ut not 0oth.
5or more information a0out defining Thermal ?one o0#ects, see section 44, JThermal
Management.L
6.3.2 Objects
All o0#ects, e/cept locals, have a glo0al scope. 1ocal data o0#ects have a per&invocation scope and lifetime
and are used to process the current invocation from 0eginning to end.
The contents of o0#ects var( greatl(. Nevertheless, most o0#ects refer to data varia0les of an( supported
data t(pe, a control method, or s(stem software&provided functions.
6.4 Defnition Block Encoding
This section specifies the encoding used in a -efinition ;lock to define names =load time onl(>, o0#ects,
and packages. The -efinition ;lock is encoded as a stream from 0eginning to end. The lead 0(te in the
stream comes from the AM1 encoding ta0les shown in section 49, JAC'% !ource 1anguage =A!1>
3eference,L and signifies how to interpret some num0er of following 0(tes, where each following 0(te can
in turn signif( how to interpret some num0er of following 0(tes. 5or a full specification of the AM1
encoding, see section 49, JAC'% !ource 1anguage =A!1> 3eference.L
Within the stream there are two levels of data 0eing defined. 2ne is the packaging and o0#ect declarations
=load time>, and the other is an o0#ect reference =package contentsFrun&time>.
All encodings are such that the lead 0(te of an encoding signifies the t(pe of declaration or reference 0eing
made. The t(pe either has an implicit or e/plicit length in the stream. All e/plicit length declarations take
the form shown 0elow, where P3g,engt1 is the length of the inclusive length of the data for the operation.
+ea"Byte P/g+ength data444 +ea"Byte ...
Pkg#ength
6igure A-- AML 1ncoding
.ncodings of implicit length o0#ects either have fi/ed length encodings or allow for nested encodings that,
at some point, either result in an e/plicit or implicit fi/ed length.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
23 Advanced Configuration and 'ower %nterface !pecification
The P3g,engt1 is encoded as a series of 4 to " 0(tes in the stream with the most significant two 0its of 0(te
Hero, indicating how man( following 0(tes are in the P3g,engt1 encoding. The ne/t two 0its are onl( used
in one&0(te encodings, which allows for one&0(te encodings on a length up to /35. 1onger encodings,
which do not use these two 0its, have a ma/imum length of the following< two&0(te encodings of /555,
three&0(te encodings of /55555, and four&0(te length encodings of /555555555.
%t is fatal for a package length to not fall on a logical 0oundar(. 5or e/ample, if a package is contained in
another package, then 0( definition its length must 0e contained within the outer package, and similarl( for
a datum of implicit length.
At some point, the s(stem software decides to JloadL a -efinition ;lock. 1oading is accomplished when
the s(stem makes a pass over the data and populates the AC'% namespace and initialiHes o0#ects
accordingl(. The namespace for which population occurs is either from the c'rrent namespace location, as
defined 0( all nested packages or from the root if the name is preceded with OBM.
The first o0#ect present in a -efinition ;lock must 0e a named control method. This is the -efinition
;lockMs initialiHation control.
'ackages are o0#ects that contain an ordered reference to one or more o0#ects. A package can also 0e
considered a verte/ of an arra(, and an( o0#ect contained within a package can 0e another package. This
permits multidimensional arra(s of fi/ed or d(namic depths and vertices.
,nnamed o0#ects are used to populate the contents of named o0#ects. ,nnamed o0#ects cannot 0e created in
the Jroot.L ,nnamed o0#ects can 0e used as arguments in control methods.
Control method e/ecution ma( generate errors when creating o0#ects. This can occur if a Method that
creates named o0#ects 0locks and is reentered while 0locked. This will happen 0ecause all named o0#ects
have an a0solute path. This is true even if the o0#ect name specified is relative. 5or e/ample, the following
A!1 code segments are functionall( identical.
=4>
;ethod (D%&D$)
Scope (\_SB_.500)
!ame (B&R$) // Run time definition
/
/
=2>
Scope (\_SB_)
!ame (\_SB_. 500.B&R$) // 6oad time definition
/
Notice that in the a0ove e/ample the e/ecution of the -.A- method will alwa(s fail 0ecause the o0#ect
BC!;C.522.;A3 is created at load time.
6.5 Using the ACPI Control Method Source Language
2.Ms and ;%2! vendors write definition 0locks using the AC'% Control Method !ource language =A!1>
and use a translator to produce the 0(te stream encoding descri0ed in section *.", J-efinition ;lock
.ncodingL. 5or e/ample, the A!1 statements that produce the e/ample 0(te stream shown in that earlier
section are shown in the following A!1 e/ample. 5or a full specification of the A!1 statements, see section
49, JAC'% !ource 1anguage =A!1> 3eference.L
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 234
// &S6 %-ample
DefinitionBloc+ (
Pforboo+.amlP$ // 0utput 5ilename
PDSD<P$ // Si,nature
(-(3$ // DSD< )ompliance Revi2ion
P0%;P$ // 0%;#D
Pforboo+P$ // <&B6% #D
(-4((( // 0%; Revi2ion
)
// 2tart of definition bloc+
0perationRe,ion(\:#0$ S12tem#0$ (-43G$ (-4)
5ield(\:#0$ B1te&cc$ !o6oc+$ Pre2erve)
)<(4$ 4$
/
Scope(\_SB) // 2tart of 2cope
Device(P)#() // 2tart of device
PowerRe2ource(5%<($ ($ () // 2tart of pwr
;ethod (_0!)
Store (0ne2$ )<(4) // a22ert power
Sleep (F() // wait F(m2
/
;ethod (_055)
Store (7ero$ )<(4) // a22ert re2etQ
/
;ethod (_S<&)
Return ()<(4)
/
/ // end of power
/ // end of device
/ // end of 2cope
/ // end of definition bloc+
6.5.1 ASL Statements
A!1 is principall( a declarative language. A!1 statements declare o0#ects. .ach o0#ect has three parts, two
of which can 0e null<
0b9ect >L 0b9ect<1pe 5i-ed6i2t @ariable6i2t
&ixed,ist refers to a list of known length that supplies data that all instances of a given =b:ectType must
have. %t is written as =a, 0, c,>, where the num0er of arguments depends on the specific 20#ectT(pe, and
some elements can 0e nested o0#ects, that is =a, 0, =:, r, s, t>, d>. Arguments to a &ixed,ist can have default
values, in which case the( can 0e skipped. !ome 20#ectT(pes can have a null &ixed,ist.
Aariable,ist refers to a list, not of predetermined length, of child o0#ects that help define the parent. %t is
written as _/, (, H, aa, 00, cc`, where an( argument can 0e a nested o0#ect. 20#ectT(pe determines what
terms are legal elements of the Aariable,ist. !ome 20#ectT(pes can have a null varia0le list.
5or a detailed specification of the A!1 language, see section 49, JAC'% !ource 1anguage =A!1>
3eference.L 5or a detailed specification of the AC'% Control Method Machine 1anguage =AM1>, upon
which the output of the A!1 translator is 0ased, see section 48, JAC'% Machine 1anguage =AM1>
!pecification.L
6.5.2 Control Method Execution
The operating software will initiate well&defined control methods as necessar( to either interrogate or
ad#ust s(stem&level hardware state. This is called an invocation.
A control method can use other internal, or well defined, control methods to accomplish the task at hand,
which can include defined control methods provided 0( the operating software. %nterpretation of a Control
Method is not preemptive, 0ut it can 0lock. When a control method does 0lock, the operating software can
initiate or continue the e/ecution of a different control method. A control method can onl( assume that
access to glo0al o0#ects is e/clusive for an( period the control method does not 0lock.
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$lo0al o0#ects are those Name!pace o0#ects created at ta0le load time.
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Access to Objects and Operation Regions
Control Methods can reference an( o0#ects an(where in the Namespace as well as address spaces defined
in operation regions. Control methods must have e/clusive access to the an( address accessed via
2p3egions. Control methods do not directl( access an( other hardware registers, including the AC'%&
defined register 0locks. !ome of the AC'% registers, in the defined AC'% registers 0locks, are maintained on
0ehalf of control method e/ecution. 5or e/ample, the $'./C;1E is not directl( accessed 0( a control
method 0ut is used to provide an e/tensi0le interrupt handling model for control method invocation.
0oteH Accessing an 2p3egion ma( 0lock, even if the 2p3egion is not protected 0( a mute/. 5or e/ample,
0ecause of the slow nature of the em0edded controller, an em0edded controller 2p3egion field access ma(
0lock.
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6.5.2.2
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6.5.2.2
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Arguments
,p to seven arguments can 0e passed to a control method. .ach argument is an o0#ect which in turn could
0e a JpackageL st(le o0#ect that refers to other o0#ects. Access to the argument o0#ects is provided via the
A!1 ArgTer% =Arg+) language elements. The num0er of arguments passed to an( control method is fi/ed
and is defined when the control method package is created.
Method arguments can take one of the following forms<
4> An AC'% name or namepath that refers to a named o0#ect. This includes the 1ocalA and ArgA names.
%n this case, the o0#ect associated with the name is passed as the argument.
2> An AC'% name or namepath that refers to another control method. %n this case, the method is invoked
and the return value of the method is passed as the argument. A fatal error occurs if no o0#ect is
returned from the method. %f the o0#ect is not used after the method invocation it is automaticall(
deleted.
3> A valid A!1 e/pression. %n the case, the e/pression is evaluated and the o0#ect that results from this
evaluation is passed as the argument. %f this o0#ect is not used after the method invocation it is
automaticall( deleted.
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6.5.2.3
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Method Calling Convention
The calling convention for control methods can 0est 0e descri0ed as call-by-reference-constant. %n this
convention, o0#ects passed as arguments are passed 0( JreferenceL, meaning that the( are not copied to new
o0#ects as the( are passed to the called control method =A calling convention that copies o0#ects or o0#ect
wrappers during a call is known as call-by-2al'e or call-by-copy>.
This call-by-reference-constant convention allows internal o0#ects to 0e shared across each method
invocation, therefore reducing the num0er of o0#ect copies that must 0e performed as well as the num0er of
0uffers that must 0e copied. This calling convention is appropriate to the low&level nature of the AC'%
su0s(stem within the kernel of the host operating s(stem where non&paged d(namic memor( is t(picall( at
a premium. The A!1 programmer must 0e aware of the calling convention and the related side effects.
@owever, unlike a pure call-by-reference convention, the a0ilit( of the called control method to modif(
arguments is e/tremel( limited. This reduces aliasing issues such as when a called method une/pectedl(
modifies a o0#ect or varia0le that has 0een passed as an argument 0( the caller. %n effect, the arguments that
are passed to control methods are passed as constants that cannot 0e modified e/cept under specific
controlled circumstances.
$enerall(, the o0#ects passed to a control method via the ArgA terms cannot 0e directl( written or modified
0( the called method. %n other words, when an ArgA term is used as a target operand in an A!1 statement,
the e/isting ArgA o0#ect is not modified. %nstead, the new o0#ect replaces the e/isting o0#ect and the ArgA
term effectivel( 0ecomes a 1ocalA term.
The onl( e/ception to the read&onl( argument rule is if an ArgA term contains an 20#ect 3eference created
via the $ef=f A!1 operator. %n this case, the use of the ArgA term as a target operand will cause an(
e/isting o0#ect stored at the AC'% name referred to 0( the $ef=f operation to 0e overwritten.
%n some limited cases, a new, writa0le o0#ect ma( 0e created that will allow a control method to change the
value of an ArgA o0#ect. These cases are limited to ;uffer and 'ackage o0#ects where the JvalueL of the
o0#ect is represented indirectl(. 5or ;uffers, a writa0le %nde/ or 5ield can 0e created that refers to the
original 0uffer data and will allow the called method to read or modif( the data. 5or 'ackages, a writa0le
%nde/ can 0e created to allow the called method to modif( the contents of individual elements of the
'ackage.
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6.5.2.4
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Local Variables and Locally Created Data Objects
Control methods can access up to eight local data o0#ects. Access to the local data o0#ects have shorthand
encodings. 2n initial control method e/ecution, the local data o0#ects are N,11. Access to local o0#ects is
via the A!1 1ocalTerm language elements.
,pon control method e/ecution completion, one o0#ect can 0e returned that can 0e used as the result of the
e/ecution of the method. The JcallerL must either use the result or save it to a different o0#ect if it wants to
preserve it. !ee the description of the 3eturn A!1 operator for additional details
Name!pace o0#ects created within the scope of a method are d(namic. The( e/ist onl( for the duration of
the method e/ecution. The( are created when specified 0( the code and are destro(ed on e/it. A method
ma( create d(namic o0#ects outside of the current scope in the Name!pace using the scope operator or
using full path names. These o0#ects will still 0e destro(ed on method e/it. 20#ects created at load time
outside of the scope of the method are static. 5or e/ample<
Scope (\RS7)
!ame (B&R$ G) // )reate2 \RS7.B&R
;ethod (500$ 4)
Store (B&R$ )R%:) // 2ame effect a2 Store (\RS7.B&R$ )R%:)
!ame (B&R$ T) // )reate2 \RS7.500.B&R
Store (B&R$ DR%:) // 2ame effect a2 Store (\RS7.500.B&R$ DR%:
!ame (\RS7.500B$ F) // )reate2 \RS7.500B
/ // end method
/ // end 2cope
The o0#ect BAS?.;A3 is a static o0#ect created when the ta0le that contains the a0ove A!1 is loaded. The
o0#ect BAS?.522.;A3 is a d(namic o0#ect that is created when the Name (BAR, 7) statement in the 522
method is e/ecuted. The o0#ect BAS?.522; is a d(namic o0#ect created 0( the BAS?.522 method when
the Name (\XYZ.FOOB, 3) statement is e/ecuted. Notice that the BAS?.522; o0#ect is destro(ed after
the BAS?.522 method e/its.
6.6 ACPI Event Programming Model
The AC'% event programming model is 0ased on the !C% interrupt and $eneral&'urpose .vent =$'.>
register. AC'% provides an e/tensi0le method to raise and handle the !C% interrupt, as descri0ed in this
section.
6.6.1 ACPI Event Programming Model Components
The components of the AC'% event programming model are the following<
2!'M
5A-T
'M4aC!T!, 'M40C!T! and 'M4aC.N, 'M40C.N fi/ed register 0locks
$'.C;1E and $'.4C;1E register 0locks
$'. register 0locks defined in $'. 0lock devices
!C% interrupt
AC'% AM1 code general&purpose event model
AC'% device&specific model events
AC'% .m0edded Controller event model
The role of each component in the AC'% event programming model is descri0ed in the following ta0le.
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Ta!le A-(+ ACPI 1vent Progra%%ing Model Co%ponents
Co%ponent 5escription
2!'M 3eceives all !C% interrupts raised =receives all !C% events>. .ither handles the
event or masks the event off and later invokes an 2.M&provided control method
to handle the event. .vents handled directl( 0( 2!'M are fi/ed AC'% eventsK
interrupts handled 0( control methods are general&purpose events.
5A-T !pecifies the 0ase address for the following fi/ed register 0locks on an AC'%&
compati0le platform< 'M4/C!T! and 'M4/C.N fi/ed registers and the
$'./C!T! and $'./C.N fi/ed registers.
'M4xC!T! and
'M4xC.N fi/ed
registers
'M4/C!T! 0its raise fi/ed AC'% events. While a 'M4/C!T! 0it is set, if the
matching 'M4/C.N 0it is set, the AC'% !C% event is raised.
$'.xC!T! and
$'.xC.N fi/ed
registers
$'./C!T! 0its that raise general&purpose events. 5or ever( event 0it implemented
in $'./C!T!, there must 0e a compara0le 0it in $'./C.N. ,p to 2*+
$'./C!T! 0its and matching $'./C.N 0its can 0e implemented. While a
$'./C!T! 0it is set, if the matching $'./C.N 0it is set, then the general&purpose
!C% event is raised.
!C% interrupt A level&sensitive, sharea0le interrupt mapped to a declared interrupt vector. The
!C% interrupt vector can 0e shared with other low&priorit( interrupts that have a
low fre:uenc( of occurrence.
AC'% AM1 code
general&purpose event
model
A model that allows 2.M AM1 code to use $'./C!T! events. This includes
using $'./C!T! events as JwakeL sources as well as other general service events
defined 0( the 2.M =J0utton pressed,L Jthermal event,L Jdevice presentFnot
present changed,L and so on>.
AC'% device&specific
model events
-evices in the AC'% namespace that have AC'%&specific device %-s can provide
additional event model functionalit(. %n particular, the AC'% em0edded controller
device provides a generic event model.
AC'% .m0edded
Controller event model
A model that allows 2.M AM1 code to use the response from the .m0edded
Controller Guer( command to provide general&service event defined 0( the 2.M.
6.6.2 Types of ACPI Events
At the direct AC'% hardware level, two t(pes of events can 0e signaled 0( an !C% interrupt<
5i/ed AC'% events
$eneral&purpose events
%n turn, the general&purpose events can 0e used to provide further levels of events to the s(stem. And, as in
the case of the em0edded controller, a well&defined second&level event dispatching is defined to make a
third t(pe of t(pical AC'% event. 5or the fle/i0ilit( common in toda(Ms designs, two first&level general&
purpose event 0locks are defined, and the em0edded controller construct allows a large num0er of
em0edded controller second&level event&dispatching ta0les to 0e supported. Then if needed, the 2.M can
also 0uild additional levels of event dispatching 0( using AM1 code on a general&purpose event to su0&
dispatch in an 2.M defined manner.
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Fixed ACPI Event Handling
When 2!'M receives a fi/ed AC'% event, it directl( reads and handles the event registers itself. The
following ta0le lists the fi/ed AC'% events. 5or a detailed specification of each event, see section ", JAC'%
@ardware !pecification.L
Ta!le A-(& 6ixed ACPI 1vents
1vent Co%%ent
'ower
management
timer carr( 0it
set.
5or more information, see the description of the TM3C!T! and TM3C.N 0its of the
'M4/ fi/ed register 0lock in section ".9.3.4, J'M4 .vent $rouping,L as well as the
TM3CDA1 register in the 'MCTM3C;1E in section ".9.3.3, J'ower Management
Timer.L
'ower 0utton
signal
A power 0utton can 0e supplied in two wa(s. 2ne wa( is to simpl( use the fi/ed status
0it, and the other uses the declaration of an AC'% power device and AM1 code to
determine the event. 5or more information a0out the alternate&device 0ased power
0utton, see section ".9.2.2.4.2, Control Method 'ower ;utton.L
Notice that during the ! state, 0oth the power and sleep 0uttons merel( notif( 2!'M
that the( were pressed.
%f the s(stem does not have a sleep 0utton, it is recommended that 2!'M use the
power 0utton to initiate sleep operations as re:uested 0( the user.
!leep 0utton
signal
A sleep 0utton can 0e supplied in one of two wa(s. 2ne wa( is to simpl( use the fi/ed
status 0utton. The other wa( re:uires the declaration of an AC'% sleep 0utton device
and AM1 code to determine the event.
3TC alarm AC'%&defines an 3TC wake alarm function with a minimum of one&month granularit(.
The AC'% status 0it for the device is optional. %f the AC'% status 0it is not present, the
3TC status can 0e used to determine when an alarm has occurred. 5or more
information, see the description of the 3TCC!T! and 3TCC.N 0its of the 'M4/ fi/ed
register 0lock in section ".9.3.4, J'M4 .vent $rouping.L
Wake status The wake status 0it is used to determine when the sleeping state has 0een completed.
5or more information, see the description of the WAEC!T! and WAEC.N 0its of the
'M4/ fi/ed register 0lock in section ".9.3.4, J'M4 .vent $rouping.L
Ta!le A-(& 6ixed ACPI 1vents (continued)
1vent Co%%ent
!(stem 0us
master re:uest
The 0us&master status 0it provides feed0ack from the hardware as to when a 0us master
c(cle has occurred. This is necessar( for supporting the processor C3 power savings
state. 5or more information, see the description of the ;MC!T! 0it of the 'M4/ fi/ed
register 0lock in section ".9.3.4, J'M4 .vent $rouping.L
$lo0al release
status
This status is raised as a result of the $lo0al 1ock protocol, and is handled 0( 2!'M as
part of $lo0al 1ock s(nchroniHation. 5or more information, see the description of the
$;1C!T! 0it of the 'M4/ fi/ed register 0lock in section ".9.3.4, J'M4 .vent
$rouping.L 5or more information on $lo0al 1ock, see section *.2.4.4, J$lo0al 1ock.L
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General-Purpose Event Handling
When 2!'M receives a general&purpose event, it either passes control to an AC'%&aware driver, or uses an
2.M&supplied control method to handle the event. An 2.M can implement up to 428 general&purpose
event inputs in hardware per $'. 0lock, each as either a level or edge event. %t is also possi0le to
implement a single 2*+&pin 0lock as long as itMs the onl( 0lock defined in the s(stem.
An e/ample of a general&purpose event is specified in section ", JAC'% @ardware !pecification,L where
.CC!T! and .CC.N 0its are defined to ena0le 2!'M to communicate with an AC'%&aware em0edded
controller device driver. The .CC!T! 0it is set when either an interface in the em0edded controller space
has generated an interrupt or the em0edded controller interface needs servicing. Notice that if a platform
uses an em0edded controller in the AC'% environment, then the em0edded controllerMs !C% output must 0e
directl( and e/clusivel( tied to a single $'. input 0it.
@ardware can cascade other general&purpose events from a 0it in the $'./C;1E through status and ena0le
0its in 2perational 3egions =%F2 space, memor( space, 'C% configuration space, or em0edded controller
space>. 5or more information, see the specification of the $eneral&'urpose .vent ;locks =$'./C;1E> in
section ".9.".4, J$eneral&'urpose .vent 3egister ;locks.L
2!'M manages the 0its in the $'./ 0locks directl(, although the source to those events is not directl(
known and is connected into the s(stem 0( control methods. When 2!'M receives a general&purpose event
=the event is from a $'./C;1E !T! 0it>, 2!'M does the following<
4. -isa0les the interrupt source =$'./C;1E .N 0it>.
2. %f an edge event, clears the status 0it.
3. 'erforms one of the following<
-ispatches to an AC'%&aware device driver.
Gueues the matching control method for e/ecution.
Manages a wake event using device C'3W o0#ects.
". %f a level event, clears the status 0it.
*. .na0les the interrupt source.
The 2.M AM1 code can perform 2.M&specific functions custom to each event the particular platform
might generate 0( e/ecuting a control method that matches the event. 5or $'. events, 2!'M will e/ecute
the control method of the name BC$'..CT++ where ++ is the he/ value format of the event that needs to 0e
handled and T indicates the event handling t(pe =T must 0e either O.M for an edge event or O1M for a le2el
event>. The event values for status 0its in $'.C;1E start at Hero =CT> and end at the =$'.C;1EC1.N
F 2> & 4. The event values for status 0its in $'.4C;1E start at $'.4C;A!. and end at $'.4C;A!. Z
=$'.4C;1EC1.N F 2> & 4. $'.C;1EC1.N, $'.4C;A!., and $'.4C;1EC1.N are all defined in the
5A-T.
5or 2!'M to manage the 0its in the $'./C;1E 0locks directl(<
.na0le 0its must 0e readFwrite.
!tatus 0its must 0e latching.
!tatus 0its must 0e readFclear, and cleared 0( writing a J4L to the status 0it.
6.6.2.2.1 Wake Events
An important use of the general&purpose events is to implement device wake events. The components of the
AC'% event programming model interact in the following wa(<
When a device asserts its wake signal, the general&purpose status event 0it used to track that
device is set.
While the corresponding general&purpose ena0le 0it is ena0led, the !C% interrupt is asserted.
%f the s(stem is sleeping, this will cause the hardware, if possi0le, to transition the s(stem into the
! state.
2nce the s(stem is running, 2!'M will dispatch the corresponding $'. handler.
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The handler needs to determine which device o0#ect has signaled wake and performs a wake
Notif( command on the corresponding device o0#ect=s> that have asserted wake.
%n turn 2!'M will notif( 2!'M native driver=s> for each device that will wake its device to
service it.
.vents that wake ma( not 0e intermi/ed with non&wake =runtime> events on the same $'. input. The onl(
e/ception to this rule is made for the special devices 0elow. 2nl( the following devices are allowed to
utiliHe a single $'. for 0oth wake and runtime events<
4> ;utton -evices
'N'CC P 'ower ;utton -evice
'N'C- P 1id -evice
'N'C. P !leep ;utton -evice
2> 'C% ;us Wakeup .vent 3eporting ='M.>
'N'A3 P 'C% @ost ;ridge
All wake events that are not e/clusivel( tied to a $'. input =for e/ample, one input is shared for multiple
wake events> must have individual ena0le and status 0its in order to properl( handle the semantics used 0(
the s(stem.
6.6.2.2.2 Dispatching to an ACPI-Aware Device Driver
Certain device support, such as an em0edded controller, re:uires a dedicated $'. to service the device.
!uch $'.s are dispatched to native 2! code to 0e handled and not to the corresponding $'.&specific
control method.
%n the case of the em0edded controller, an 2!&native, AC'%&aware driver is given the $'. event for its
device. This driver services the em0edded controller device and determines when events are to 0e reported
0( the em0edded controller 0( using the Guer( command. When an em0edded controller event occurs, the
AC'%&aware driver dispatches the re:uests to other AC'%&aware drivers that have registered to handle the
em0edded controller :ueries or :ueues control methods to handle each event. %f there is no device driver to
handle specific :ueries, 2.M AM1 code can perform 2.M&specific functions that are customiHed to each
event on the particular platform 0( including specific control methods in the namespace to handle these
events. 5or an em0edded controller event, 2!'M will :ueue the control method of the name CG++. where
++ is the he/ format of the :uer( code. Notice that each em0edded controller device can have :uer( event
control methods.
!imilarl(, for an !M;us driver, if no driver registers for !M;us alarms, the !M;us driver will :ueue
control methods to handle these. Methods must 0e placed under the !M;us device with the name CGAA
where AA is the he/ format of the !M;us address of the device sending the alarm.
6.6.2.2.3 Queuing the Matching Control Method for Execution
When a general&purpose event is raised, 2!'M uses a naming convention to determine which control
method to :ueue for e/ecution and how the $'. .2% is to 0e handled. The $'./C!T! 0its in the
$'./C;1E are inde/ed with a num0er from through 55. The name of the control method to :ueue for an
event raised from an ena0le status 0it is alwa(s of the form BC$'..CTxx where xx is the event value and T
indicates the event .2% protocol to use =either edge or level>. The event values for status 0its in
$'.C;1E start at Hero =CT>, end at the =$'.C;1EC1.N F 2> & 4, and correspond to each status 0it
inde/ within $'.C;1E. The event values for status 0its in $'.4C;1E are offset 0( $'.C;A!. and
therefore start at $'.4C;A!. and end at $'.4C;A!. Z =$'.4C;1EC1.N F 2> & 4.
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2"8 Advanced Configuration and 'ower %nterface !pecification
5or e/ample, suppose an 2.M supplies a wake event for a communications port and uses 0it " of the
$'.C!T! 0its to raise the wake event status. %n an 2.M&provided -efinition ;lock, there must 0e a
Method declaration that uses the name BC$'..C1" or B$'..C." to handle the event. An e/ample of a
control method declaration using such a name is the following<
;ethod (\_:P%._6(.) // :P% . level wa+e handler
!otif1 (\_SB.P)#0.)0;($ 3)
/
The control method performs whatever action is appropriate for the event it handles. 5or e/ample, if the
event means that a device has appeared in a slot, the control method might acknowledge the event to some
other hardware register and signal a change notif( re:uest of the appropriate device o0#ect. 2r, the cause of
the general&purpose event can result from more then one source, in which case the control method for that
event determines the source and takes the appropriate action.
When a general&purpose event is raised from the $'. 0it tied to an em0edded controller, the em0edded
controller driver uses another naming convention defined 0( AC'% for the em0edded controller driver to
determine which control method to :ueue for e/ecution. The :ueries that the em0edded controller driver
e/changes with the em0edded controller are num0ered from through 55, (ielding event codes 4 through
55. =A :uer( response of from the em0edded controller is reserved for Jno outstanding events.L> The
name of the control method to :ueue is alwa(s of the form CGxx where xx is the num0er of the :uer(
acknowledged 0( the em0edded controller. An e/ample declaration for a control method that handles an
em0edded controller :uer( is the following<
;ethod(_JF.) // embedded controller event for thermal
!otif1 (\_SB.<7(.<";4$ (-=()
/
When an !M;us alarm is handled 0( the !M;us driver, the !M;us driver uses a similar naming
convention defined 0( AC'% for the driver to determine the control method to :ueue for e/ecution. When
an alarm is received 0( the !M;us host controller, it generall( receives the !M;us address of the device
issuing the alarm and one word of data. 2n implementations that use !M;A1.3TY for notifications, onl(
the device address will 0e received. The name of the control method to :ueue is alwa(s of the form CGxx
where xx is the !M;us address of the device that issued the alarm. The !M;us address is 9 0its long
corresponding to he/ values through 95, although some addresses are reserved and will not 0e used. The
control method will alwa(s 0e :ueued with one argument that contains the word of data received with the
alarm. An e/ception is the case of an !M;us using !M;A1.3TY for notifications, in this case the
argument will 0e . An e/ample declaration for a control method that handles a !M;us alarm follows<
;ethod(_J4=$ 4) // <hermal 2en2or device at addre22 ((44 (((
// &r,( contain2 notification value (if an1)
// &r,( L ( if device 2upport2 onl1 S;B&6%R<Q
!otif1 (\_SB.<7(.<";4$ (-=()
/
6.6.2.2.4 Managing a Wake Event Using Device _PRW Objects
A deviceMs C'3W o0#ect provides the Hero&0ased 0it inde/ into the general&purpose status register 0lock to
indicate which general&purpose status 0it from either $'.C;1E or $'.4C;1E is used as the specific
deviceMs wake mask. Although the hardware must maintain individual device wake ena0le 0its, the s(stem
can have multiple devices using the same general&purpose event 0it 0( using 2.M&specific hardware to
provide second&level status and ena0le 0its. %n this case, the 2.M AM1 code is responsi0le for the second&
level ena0le and status 0its.
2!'M ena0les or disa0les the device wake function 0( ena0ling or disa0ling its corresponding $'. and 0(
e/ecuting its C'!W control method =which is used to take care of the second&level ena0les>. When the $'.
is asserted, 2!'M still e/ecutes the corresponding $'. control method that determines which device
wakes are asserted and notifies the corresponding device o0#ects. The native 2! driver is then notified that
its device has asserted wake, for which the driver powers on its device to service it.
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%f the s(stem is in a sleeping state when the ena0led $'. 0it is asserted the hardware will transition the
s(stem into the ! state, if possi0le.
6.6.2.2.5 Determining the System Wake Source Using _Wxx Control
Methods
After a transition to the ! state, 2!'M ma( evaluate the C!W! o0#ect in the BC$'. scope to determine the
inde/ of the $'. that was the source of the transition event. When a single $'.s is shared among multiple
devices, the platform provides a CW// control method, where // is $'. inde/ as descri0ed in !ection
*.+.2.2.3, that allows the source device of the transition to 0e determined . %f implemented, the CW//
control method must e/ist in the BC$'. scope or in the scope of a $'. 0lock device.
%f CW// is implemented, either hardware or firmware must detect and save the source device as descri0ed
in !ection 9.3.*, JC!W! =!(stem Wake !ource>L. -uring invocation, the CW// control method determines
the source device and issues a 0otif)=Tdevice),/2> on the device that caused the s(stem to transition to
the ! state. %f the device uses a 0us&specific method of arming for wakeup, then the 0otif) must 0e issued
on the parent of the device that has a C'3W method. The CW// method must issue a
Notif(=Tdevice),/2> onl( to devices that contain a C'3W method within their device scope. 2!'MMs
evaluation of the C!W! and CW// o0#ects is indeterminate. As such, the platform must not rel( on C!W!
or CW// evaluation to clear an( hardware state, including $'./C!T! 0its, or to perform an( wakeup&
related actions.
%f the $'. inde/ returned 0( the C!W! o0#ect is onl( referenced 0( a single C'3W o0#ect in the s(stem, it
is implied that the device containing that C'3W is the wake source. %n this case, it is not necessar( for the
platform to provide a CW// method.
6.6.3 Device Object Notifcations
-uring normal operation, the platform needs to notif( 2!'M of various device&related events. These
notifications are accomplished using the Notif( operator, which indicates a target device, thermal Hone, or
processor o0#ect and a notification value that signifies the purpose of the notification. Notification values
from through /95 are common across all device o0#ect t(pes. Notification values of /C and a0ove are
reserved for definition 0( hardware vendors for hardware specific notifications. Notification values from
/8 to /;5 are device&specific and defined 0( each such device. 5or more information on the Notif(
operator, see section 49.*.8*, JNotif( =Notif(>.L
Ta!le A-(# 5evice 3!Cect 0otification 7alues
7alue 5escription
<us Check This notification is performed on a device o0#ect to indicate to 2!'M that it
needs to perform the 'lug and 'la( re&enumeration operation on the device tree starting
from the point where it has 0een notified. 2!'M will onl( perform this operation at 0oot,
and when notified. %t is the responsi0ilit( of the AC'% AM1 code to notif( 2!'M at an(
other times that this operation is re:uired. The more accuratel( and closer to the actual
device tree change the notification can 0e done, the more efficient the operating s(stemMs
response will 0eK however, it can also 0e an issue when a device change cannot 0e
confirmed. 5or e/ample, if the hardware cannot notice a device change for a particular
location during a s(stem sleeping state, it issues a ;us Check notification on wake to
inform 2!'M that it needs to check the configuration for a device change.
4 5evice Check ,sed to notif( 2!'M that the device either appeared or disappeared. %f
the device has appeared, 2!'M will re&enumerate from the parent. %f the device has
disappeared, 2!'M will invalidate the state of the device. 2!'M ma( optimiHe out re&
enumeration. %f C-CE is present, then Notif(=ob:ect,4> is assumed to indicate an undock
re:uest.
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7alue 5escription
2 5evice :ake ,sed to notif( 2!'M that the device has signaled its wake event, and that
2!'M needs to notif( 2!'M native device driver for the device. This is onl( used for
devices that support C'3W.
3 1Cect "eJuest ,sed to notif( 2!'M that the device should 0e e#ected, and that 2!'M
needs to perform the 'lug and 'la( e#ection operation. 2!'M will run the C.7/ method.
" 5evice Check Light ,sed to notif( 2!'M that the device either appeared or
disappeared. %f the device has appeared, 2!'M will re&enumerate from the device itself,
not the parent. %f the device has disappeared, 2!'M will invalidate the state of the
device.
* 6reJuenc) Mis%atch ,sed to notif( 2!'M that a device inserted into a slot cannot 0e
attached to the 0us 0ecause the device cannot 0e operated at the current fre:uenc( of the
0us. 5or e/ample, this would 0e used if a user tried to hot&plug a 33 M@H 'C% device into
a slot that was on a 0us running at greater than 33 M@H.
+ <us Mode Mis%atch ,sed to notif( 2!'M that a device has 0een inserted into a slot or
0a( that cannot support the device in its current mode of operation. 5or e/ample, this
would 0e used if a user tried to hot&plug a 'C% device into a slot that was on a 0us
running in 'C%&A mode.
9 Power 6ault ,sed to notif( 2!'M that a device cannot 0e moved out of the -3 state
0ecause of a power fault.
8 Capa!ilities Check This notification is performed on a device o0#ect to indicate to
2!'M that it needs to re&evaluate the C2!C control method associated with the device.
6 5evice DPL5 Check ,sed to notif( 2!'M to reevaluate the C'1- o0#ect, as the
-eviceMs connection point has changed.
/A "eserved
/; S)ste% Localit) Infor%ation 2pdate -(namic reconfiguration of the s(stem ma(
cause e/isting relative distance information to change. The platform sends the !(stem
1ocalit( %nformation ,pdate notification to a point on a device tree to indicate to 2!'M
that it needs to invoke the C!1% o0#ects associated with the !(stem 1ocalities on the
device tree starting from the point notified.
/C&/95 "eserved
;elow are the notification values defined for specific AC'% devices. 5or more information concerning the
o0#ect&specific notification, see the section on the corresponding deviceFo0#ect.
Ta!le A-(( Control Method <atter) 5evice 0otification 7alues
Hex value 5escription
/8 <atter) Status Changed ,sed to notif( 2!'M that the Control Method ;atter( device
status has changed.
/84 <atter) Infor%ation Changed ,sed to notif( 2!'M that the Control Method ;atter(
device information has changed. This onl( occurs when a 0atter( is replaced.
/82 <atter) Maintenance 5ata Status 6lags Check ,sed to notif( 2!'M that the Control
Method ;atter( device 0atter( maintenance data status flags should 0e checked.
/83&/;5 "eserved
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Ta!le A-(A Power Source 3!Cect 0otification 7alues
Hex value 5escription
/8 Power Source Status Changed. ,sed to notif( 2!'M that the power source status has
changed.
/84&/;5 "eserved
Ta!le A-(- Ther%al Ione 3!Cect 0otification 7alues
Hex value 5escription
/8 Ther%al Ione Status Changed ,sed to notif( 2!'M that the thermal Hone
temperature has changed.
/84 Ther%al Ione Trip points Changed ,sed to notif( 2!'M that the thermal Hone trip
points have changed.
/82 5evice Lists Changed ,sed to notif( 2!'M that the thermal Hone device lists =CA1/,
C'!1, CT?-> have changed.
/83 Ther%al "elationship Ta!le Changed ,sed to notif( 2!'M that values in the thermal
relationship ta0le have changed.
/8"&/;5 "eserved
Ta!le A-(. Control Method Power <utton 0otification 7alues
Hex value 5escription
/8 S$ Power <utton Pressed ,sed to notif( 2!'M that the power 0utton has 0een pressed
while the s(stem is in the ! state. Notice that when the 0utton is pressed while the
s(stem is in the !4&!" state, a -evice Wake notification must 0e issued instead.
/84&/;5 "eserved
Ta!le A-(/ Control Method Sleep <utton 0otification 7alues
Hex value 5escription
/8 S$ Sleep <utton Pressed ,sed to notif( 2!'M that the sleep 0utton has 0een pressed
while the s(stem is in the ! state. Notice that when the 0utton is pressed while the
s(stem is in the !4&!" state, a -evice Wake notification must 0e issued instead.
/84&/;5 "eserved
Ta!le A-(, Control Method Lid 0otification 7alues
Hex value 5escription
/8
Lid Status Changed ,sed to notif( 2!'M that the control method lid device status has
changed.
/84&/;5 "eserved
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Ta!le A-A$ Processor 5evice 0otification 7alues
Hex value 5escription
/8
Perfor%ance Present Capa!ilities Changed. ,sed to notif( 2!'M that the num0er of
supported processor performance states has changed. This notification causes 2!'M to
re&evaluate the C''C o0#ect. !ee section 8, J'rocessor 'ower and 'erformance !tate
Configuration and Control,L for more information.
/84
C States Changed ,sed to notif( 2!'M that the num0er or t(pe of supported processor
C !tates has changed. This notification causes 2!'M to re&evaluate the CC!T o0#ect. !ee
section 8, J'rocessor 'ower and 'erformance !tate Configuration and Control,L for more
information.
/82 Throttling Present Capa!ilities Changed. ,sed to notif( 2!'M that the num0er of
supported processor throttling states has changed. This notification causes 2!'M to re&
evaluate the CT'C o0#ect. !ee section 8, J'rocessor 'ower and 'erformance !tate
Configuration and Control,L for more information.
/83&/;5 "eserved
Ta!le A-A+ 2ser Presence 5evice 0otification 7alues
Hex value 5escription
/8
2ser Presence Changed ,sed to notif( 2!'M that a meaningful change in user
presence has occurred, causing 2!'M to re&evaluate the C,'- o0#ect.
/84&/;5 "eserved
Ta!le A-A& A%!ient Light Sensor 5evice 0otification 7alues
Hex value 5escription
/8
ALS Illu%inance Changed ,sed to notif( 2!'M that a meaningful change in am0ient
light illuminance has occurred, causing 2!'M to re&evaluate the CA1% o0#ect.
/84
ALS Color Te%perature Changed ,sed to notif( 2!'M that a meaningful change in
am0ient light color temperature or chromacit( has occurred, causing 2!'M to re&
evaluate the CA1T andFor CA1C o0#ects.
/82 ALS "esponse Changed ,sed to notif( 2!'M that the set of points used to conve( the
am0ient light response has changed, causing 2!'M to re&evaluate the CA13 o0#ect.
/83&/;5 "eserved
6.6.4 Device Class-Specifc Objects
Most device o0#ects are controlled through generic o0#ects and control methods and the( have generic
device %-s. These generic o0#ects, control methods, and device %-s are specified in sections +, 9, 8, 6, 4,
and 44. !ection *.+.*, J-efined $eneric 20#ects and Control Methods,L lists all the generic o0#ects and
control methods defined in this specification.
@owever, certain integrated devices re:uire support for some device&specific AC'% controls. This section
lists these devices, along with the device&specific AC'% controls that can 0e provided.
!ome of these controls are for AC'%&aware devices and as such have 'lug and 'la( %-s that represent these
devices. The following ta0le lists the 'lug and 'la( %-s defined 0( the AC'% specification.
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Ta!le A-A# ACPI 5evice I5s
Plug and
Pla) I5
5escription
'N'C8 ACPI Not declared in AC'% as a device. This %- is used 0( 2!'M for the hardware
resources consumed 0( the AC'% fi/ed register spaces, and the operation regions used 0(
AM1 code. %t represents the core AC'% hardware itself.
'N'A* ;eneric Container 5evice A device whose settings are totall( controlled 0( its AC'%
resource information, and otherwise needs no device or 0us&specific driver support. This
was originall( known as $eneric %!A ;us -evice. This %- should onl( 0e used for
containers that do not produce resources for consumption 0( child devices. An( s(stem
resources claimed 0( a 'N'A* deviceMs CC3! o0#ect must 0e consumed 0( the
container itself.
'N'A+ ;eneric Container 5evice This device 0ehaves e/actl( the same as the 'N'A*
device. This was originall( known as ./tended %F2 ;us. This %- should onl( 0e used for
containers that do not produce resources for consumption 0( child devices. An( s(stem
resources claimed 0( a 'N'A+ deviceMs CC3! o0#ect must 0e consumed 0( the
container itself.
'N'C6 1%!edded Controller 5evice A host em0edded controller controlled through an AC'%&
aware driver.
'N'CA Control Method <atter) A device that solel( implements the AC'% Control Method
;atter( functions. A device that has some other primar( function would use its normal
device %-. This %- is used when the devices primar( function is that of a 0atter(.
'N'C; 6an A device that causes cooling when JonL =- device state>.
Ta!le A-A# ACPI 5evice I5s (continued)
Plug and
Pla) I5
5escription
'N'CC Power <utton 5evice A device controlled through an AC'%&aware driver that provides
power 0utton functionalit(. This device is onl( needed if the power 0utton is not
supported using the fi/ed register space.
'N'C- Lid 5evice A device controlled through an AC'%&aware driver that provides lid status
functionalit(. This device is onl( needed if the lid state is not supported using the fi/ed
register space.
'N'C. Sleep <utton 5evice A device controlled through an AC'%&aware driver that provides
power 0utton functionalit(. This device is optional.
'N'C5 PCI Interrupt Link 5evice A device that allocates an interrupt connected to a 'C%
interrupt pin. !ee section +., JConfiguration,L for more details.
'N'C8 Me%or) 5evice This device is a memor( su0s(stem.
AC'%4 SM<us +$ Host Controller An !M;us host controller =!M;&@C> compati0le with the
em0edded controller&0ased !M;&@C interface =as specified in section 42.6, J!M;us
@ost Controller %nterface via .m0edded ControllerL> and implementing the !M;us 4.
!pecification.
AC'%2 S%art <atter) Su!s)ste% The !mart 0atter( !u0s(stem specified in section 4,
J'ower !ource -evices.L
AC'%3 AC 5evice The AC adapter specified in section 4, J'ower !ource -evices.L
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Plug and
Pla) I5
5escription
AC'%" Module 5evice This device is a container o0#ect that acts as a 0us node in a namespace.
A Module -evice without an( of the CC3!, C'3! and C!3! methods 0ehaves the same
wa( as the $eneric Container -evices ='N'A* or 'N'A+>. %f the Module -evice
contains a CC3! method, onl( these resources descri0ed in the CC3! are availa0le for
consumption 0( its child devices. Also, the Module -evice can support C'3! and C!3!
methods if CC3! is supported.
AC'%* SM<us &$ Host Controller An !M;us host controller =!M;&@C compati0le with the
em0edded controller&0ased !M;&@C interface =as specified in section 42.6, J!M;us
@ost Controller %nterface via .m0edded ControllerL> and implementing the !M;us 2.
!pecification.
AC'%+ ;P1 <lock 5evice This device allows a s(stem designer to descri0e $'. 0locks
0e(ond the two that are descri0ed in the 5A-T.
AC'%9 Processor 5evice This device provides an alternative to declaring processors using the
Processor A!1 statement. !ee section 8.", J-eclaring 'rocessorsL, for more details.
AC'%8 A%!ient Light Sensor 5evice This device is an am0ient light sensor. !ee section 6.2,
JControl Method Am0ient 1ight !ensor -eviceL.
AC'%6 I@3xAPIC 5evice This device is an %F2 unit that complies with 0oth the A'%C and
!A'%C interrupt models.
AC'%A I@3 APIC 5evice This device is an %F2 unit that complies with the A'%C interrupt
model.
AC'%; I@3 SAPIC 5evice This device is an %F2 unit that complies with the !A'%C interrupt
model.
6.6.5 Defned Generic Objects and Control Methods
The following ta0le lists all of the AC'% namespace o0#ects defined in this specification and provides a
reference to the defining section of the specification. 20#ect names reserved 0( AC'% 0ut defined 0( other
specifications are also listed along with their corresponding specification reference.
Ta!le A-A( 5efined ;eneric 3!Cect and Control Methods
3!Cect 5escription "eference
CAC/ Thermal ?one o0#ect that returns active cooling polic( threshold values
in tenths of degrees Eelvin.
44.3.4
CA-3 -evice o0#ect that evaluates to a deviceMs address on its parent 0us. 5or
the displa( output device, this o0#ect returns a uni:ue %-. =;.*.4,
JCA-3 & 3eturn the ,ni:ue %- for this -evice.L>
+.4.4
CA1C 20#ect evaluates to current Am0ient 1ight Color Chromacit( 6.2."
CA1% The current am0ient light 0rightness in lu/ =lumen per s:uare meter>. 6.2.2
CA1N 3esource data t(pe reserved field name 49.4.8
CA1' Am0ient light sensor polling fre:uenc( in tenths of seconds. 6.2.+
CA13 3eturns a set of am0ient light 0rightness to displa( 0rightness mappings
that can 0e used 0( an 2! to cali0rate its am0ient light polic(.
6.2.*
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Ta!le A-A( 5efined ;eneric 3!Cect and Control Methods
3!Cect 5escription "eference
CA1T The current am0ient light color temperature in degrees Eelvin. 6.2.3
CA1x Thermal Hone o0#ect containing a list of cooling device o0#ects. 44.3.2
CA!% 3esource data t(pe reserved field name 49.4.8
C;A! 3esource data t(pe reserved field name 49.4.8
C;;N 'C% 0us num0er setup 0( the ;%2! +.*.*
C;C1 3eturns a 0uffer of 0(tes indicating list of 0rightness control levels
supported.
;.+.2
C;CM !ets the 0rightness level of the 0uilt&in displa( output device. ;.+.3
C;-N Correlates a docking station 0etween AC'% and legac( interfaces. +.*.3
C;5! Control method e/ecuted immediatel( following a wake event. 9.3.4
C;%5 Control Method ;atter( information o0#ect 4.2.2.4
C;1T 20#ect that conve(s userMs 0atter( level threshold preferences to
platform.
6.4.3
C;M 3esource data t(pe reserved field name 49.4.8
C;MC 'owers source o0#ect used to initiate 0atter( cali0ration c(cles or to
control the charger and whether or not a 0atter( is powering the s(stem.
4.2.2.9
C;M- 'ower source o0#ect that returns information a0out the 0atter(Ms
capa0ilities and current state in relation to 0atter( cali0ration and
charger control features.
4.2.2.+
C;GC 20#ect that returns current displa( 0rightness level. ;.+."
C;!T Control Method ;atter( status o0#ect 4.2.2.3
C;TM 3eturns estimated runtime at the present average rate of drain, or the
runtime at a specified rate.
4.2.2.*
C;T' !ets Control Method ;atter( trip point 4.2.2."
CC;A 'rovides the Configuration ;ase Address for a 'C% ./press host 0ridge 'C% 5irmware
!pecification,
3evision 3.
http<FFpcisig.com
CC%- -evice identification o0#ect that evaluates to a deviceMs 'lug and 'la(
Compati0le %- list.
+.4.2
CC3! -evice configuration o0#ect that specifies a deviceMs c'rrent resource
settings, or a control method that generates such an o0#ect.
+.2.4
CC3T Thermal Hone o0#ect that returns critical trip point in tenths of degrees
Eelvin.
44.3.3
CC!- 20#ect that conve(s C&!tate dependencies 8.".2.2
CC!T 'rocessor power state declaration o0#ect 8.".2.4
C-CE %ndicates that the device is a docking station. +.*.2
C-C! 3eturns the status of the displa( output device. ;.+.+
C--C 3eturns the .-%- for the displa( output device ;.+.*
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2*+ Advanced Configuration and 'ower %nterface !pecification
Ta!le A-A( 5efined ;eneric 3!Cect and Control Methods
3!Cect 5escription "eference
C--N 20#ect that associates a logical software name =for e/ample, C2M4>
with a device.
+.4.3
C-.C 3esource data t(pe reserved field name 49.4.8
C-$! Control method used to :uer( the state of the output device. ;.+.9
C-%! -evice configuration control method that disa0les a device. +.2.2
C-MA 20#ect that specifies a deviceMs c'rrent resources for -MA transactions. +.2.3
C-2- Control method used to enumerate devices attached to the displa(
adapter.
;.".2
C-2! Control method used to ena0leFdisa0le displa( output switching. ;.".4
C-!M $eneric device control method o0#ect 6.4*.4
C-!! Control method used to set displa( device state. ;.+.8
C-!W !et up a device for device&onl( wake 9.2.4
C.// Control method e/ecuted as a result of a general&purpose event. *.+.2.2,
*.+.2.2.3
C.C Control Method used to define the offset address and Guer( value of an
!M;&@C defined within an em0edded controller device.
42.42
C.-1 -evice removal o0#ect that returns a packaged list of devices that are
dependent on a device.
+.3.4
C.7/ -evice insertionFremoval control method that e#ects a device. +.3.3
C.7- -evice removal o0#ect that evaluates to the name of a device o0#ect
upon which a device is dependent. Whenever the named device is
e#ected, the dependent device must receive an e#ection notification.
+.3.2
C5-. 20#ect that indicates the presence or a0sence of flopp( disks. 6.4.4
C5-% 20#ect that returns flopp( drive information. 6.4.2
C5-M Control method that changes the mode of flopp( drives. 6.4.3
C5%A 20#ect used to provide correlation 0etween the fi/ed hardware register
0locks defined in the 5A-T and the devices that implement these fi/ed
hardware registers.
+.2."
C$1 2!&defined $lo0al 1ock mute/ o0#ect *.9.4
C $1E %ndicates the need to ac:uire the $lo0al 1ock, must 0e ac:uired when
accessing the device.
+.*.9
C$'- Control method that returns which D$A device will 0e posted at 0oot ;."."
C$'. 4. $eneral&'urpose .vents root name space
2. 20#ect that returns the !C% interrupt within the $'/C!T! register
that is connected to the .C.
*.3.4
42.44
C$3A 3esource data t(pe reserved field name. 49.4.8
C$T5 %-. device control method to get the Advanced Technolog( Attachment
=ATA> task file needed to re&initialiHe the drive to 0oot up defaults.
6.6.4.4
C$TM %-. device control method to get the %-. controller timing information. 6.6.2.4.4
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Ta!le A-A( 5efined ;eneric 3!Cect and Control Methods
3!Cect 5escription "eference
C$!; 20#ect that provides the $lo0al !(stem %nterrupt ;ase for a hot&plugged
%F2 A'%C device.
+.2.*
C$T! Control method e/ecuted #ust prior to setting the sleep ena0le
=!1'C.N> 0it.
9.3.3
C@. 3esource data t(pe reserved field name 49.4.8
C@%- -evice identification o0#ect that evaluates to a deviceMs 'lug and 'la(
@ardware %-.
+.4."
C@2T 20#ect returns critical temperature when 2!'M enters !" 44.3."
C@'' An o0#ect that specifies the Cache&line siHe, 1atenc( timer, !.33
ena0le, and '.33 ena0le values to 0e used when configuring a 'C%
device inserted into a hot&plug slot or initial configuration of a 'C%
device at s(stem 0oot.
+.2.+
C@'A 20#ect that provides device parameters when configuring a 'C% device
inserted into a hot&plug slot or initial configuration of a 'C% device at
s(stem 0oot. !upersedes C@''.
+.2.9
C%5T %'M% %nterface T(pe %ntelligent 'latform
Management
%nterface
!pecification.
http<FFwww.intel.com
FdesignFserversFipmiF
inde/.htm
C%N% -evice initialiHation method that performs device specific initialiHation. +.*.4
C%NT 3esource data t(pe reserved field name 49.4.8
C%3C 'ower management o0#ect that signifies the device has a significant
inrush current draw.
9.2.42
C1// Control method e/ecuted as a result of a general&purpose event. *.+.2.2,
*.+.2.2.3
C1CE -evice insertionFremoval control method that locks or unlocks a device. +.3."
C1.N 3esource data t(pe reserved field name 49.4.8
C1%- 20#ect that returns the status of the 1id on a mo0ile s(stem. 6.".4
C11 3esource data t(pe reserved field name 49.4.8
CMA5 3esource data t(pe reserved field name 49.4.8
CMAT 20#ect evaluates to a 0uffer of MA-T A'%C !tructure entries. +.2.8
CMAA 3esource data t(pe reserved field name 49.4.8
CM.M 3esource data t(pe reserved field name 49.4.8
CM%5 3esource data t(pe reserved field name 49.4.8
CM%N 3esource data t(pe reserved field name 49.4.8
CM!$ !(stem indicator control that indicates messages are waiting. 6.4.2
CM1! 20#ect that provides a human reada0le description of a device in
multiple languages.
+.4.*
C255 'ower resource o0#ect that sets the resource off. 9.4.2
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
2*8 Advanced Configuration and 'ower %nterface !pecification
Ta!le A-A( 5efined ;eneric 3!Cect and Control Methods
3!Cect 5escription "eference
C2N 'ower resource o0#ect that sets the resource on. 9.4.3
C2! 20#ect that evaluates to a string that identifies the operating s(stem. *.9.2
C2!C Conve( specific software support F capa0ilities to the platform allowing
the platform to configure itself appropriatel(.
+.2.6
C2!T 2!'M !tatus %ndication +.3.*
C'C1 'ower source o0#ect that contains a list of devices powered 0( a power
source.
4.3.2
C'CT 'rocessor performance control o0#ect 8.".".4
C'-C 'rocessor -river Capa0ilities 8.".4
C'%C Control method that conve(s interrupt model in use to the s(stem
firmware.
*.8.4
C'1- 20#ect that provides ph(sical location description information. +.4.+
C''C Control method used to determine num0er of performance states
currentl( supported 0( the platform.
8.".".3
C''. 20#ect provides polling interval to retrieve Corrected 'latform .rror
information
-%$+" Corrected
'latform .rror
'olling
!pecification.
http<FFwww.dig+".org
Fspecifications
C'3 AC'% 4. 'rocessor Namespace *.3.4
C'3 'ower management o0#ect that evaluates to the deviceMs power
re:uirements in the - device state =device full( on>.
9.2.9
C'34 'ower management o0#ect that evaluates to the deviceMs power
re:uirements in the -4 device state. 2nl( devices that can achieve the
defined -4 device state according to its given device class would suppl(
this level.
9.2.8
C'32 'ower management o0#ect that evaluates to the deviceMs power
re:uirements in the -2 device state. 2nl( devices that can achieve the
defined -2 device state according to its given device class would suppl(
this level.
9.2.6
C'3! -evice configuration o0#ect that specifies a deviceMs possible resource
settings, or a control method that generates such an o0#ect.
+.2.4
C'3T An o0#ect that specifies the 'C% interrupt 3outing Ta0le. +.2.44
C'3W 'ower management o0#ect that evaluates to the deviceMs power
re:uirements in order to wake the s(stem from a s(stem sleeping state.
9.2.4
C'! 'ower management control method that puts the device in the -
device state. =device full( on>.
9.2.2
C'!4 'ower management control method that puts the device in the -4
device state.
9.2.3
C'!2 'ower management control method that puts the device in the -2
device state.
9.2."
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 2*6
Ta!le A-A( 5efined ;eneric 3!Cect and Control Methods
3!Cect 5escription "eference
C'!3 'ower management control method that puts the device in the -3
device state =device off>.
9.2.*
C'!C 'ower management o0#ect that evaluates to the deviceMs current power
state.
9.2.+
C'!- 20#ect that conve(s '&!tate dependencies 8.".".*
C'!1 Thermal Hone o0#ect that returns list of passive cooling device o0#ects. 44.3.*
C'!3 'ower source o0#ect that returns present power source device. 4.3.4
C'!! 20#ect indicates the num0er of supported processor performance states. 8.".".2
C'!D Thermal Hone o0#ect that returns 'assive trip point in tenths of degrees
Eelvin.
44.3.+
C'!W 'ower management control method that ena0les or disa0les the deviceMs
wake function.
9.2.44
C'TC 20#ect used to define a processor throttling control register. 8.".3.4
C'T! Control method used to notif( the platform of impending sleep
transition.
9.3.2
C'AM 20#ect used to descri0e pro/imit( domains within a machine. +.2.42
CGxx .m0edded Controller Guer( and !M;us Alarm control method *.+.2.2.3
C3;2 3esource data t(pe reserved field name 49.4.8
C3;W 3esource data t(pe reserved field name 49.4.8
C3.$ Notifies AM1 code of a change in the availa0ilit( of an operation
region.
+.*."
C3.D 3evision of the AC'% specification that 2!'M implements. *.9."
C3MD -evice insertionFremoval o0#ect that indicates that the given device is
remova0le.
+.3.+
C3N$ 3esource data t(pe reserved field name 49.4.8
C32M Control method used to get a cop( of the displa( devicesM 32M data. ;.".3
C3T 3esource T(pe field of the GWord!pace, -Word!pace or Word!pace
address descriptors
49.4.8
C3TD 20#ect indicates whether temperature values are relative or a0solute. 44.3.9
C3W 3esource data t(pe reserved field name 49.4.8
C! 'ower management package that defines s(stem BC! state mode. 9.3.".4
C!4 'ower management package that defines s(stem BC!4 state mode. 9.3.".2
C!2 'ower management package that defines s(stem BC!2 state mode. 9.3.".3
C!3 'ower management package that defines s(stem BC!3 state mode. 9.3."."
C!" 'ower management package that defines s(stem BC!" state mode. 9.3.".*
C!* 'ower management package that defines s(stem BC!* state mode. 9.3.".+
C!4- @ighest -&state supported 0( the device in the !4 state. 9.2.43
C!2- @ighest -&state supported 0( the device in the !2 state. 9.2.4"
C!3- @ighest -&state supported 0( the device in the !3 state. 9.2.4*
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
2+ Advanced Configuration and 'ower %nterface !pecification
Ta!le A-A( 5efined ;eneric 3!Cect and Control Methods
3!Cect 5escription "eference
C!"- @ighest -&state supported 0( the device in the !" state. 9.2.4+
C!W 1owest -&state supported 0( the device in the ! state which can wake
the device
9.2.49
C!4W 1owest -&state supported 0( the device in the !4 state which can wake
the s(stem
9.2.48
C!2W 1owest -&state supported 0( the device in the !2 state which can wake
the s(stem
9.2.46
C!3W 1owest -&state supported 0( the device in the !3 state which can wake
the s(stem
9.2.2
C!"W 1owest -&state supported 0( the device in the !" state which can wake
the s(stem
9.2.24
C!; !(stem 0us scope *.3.4
C!;! !mart ;atter( o0#ect that returns !mart ;atter( configuration. 4.4.2
C!C' Thermal Hone o0#ect that sets user cooling polic( =Active or 'assive>. 44.3.8
C!-- Control method that informs the platform of the t(pe of device attached
to a !ATA port.
6.6.3.3.4
C!.$ .valuates to the 'C% !egment $roup num0er. +.*.+
C!@3 3esource data t(pe reserved field name 49.4.8
C!% !(stem indicators scope 6.4
C!%? 3esource data t(pe reserved field name 49.4.8
C!1% 20#ect that provides updated distance information for a s(stem localit(. +.2.43
C!'- Control method used to update which video device will 0e posted at
0oot.
;.".*
C!3! -evice configuration control method that sets a deviceMs settings. +.2.4"
C!3D %'M% !pec 3evision %ntelligent 'latform
Management
%nterface
!pecification.
http<FFwww.intel.com
FdesignFserversFipmiF
inde/.htm
C!!T !(stem indicator control method that indicates the s(stem status. 6.4.4
C!TA 4. -evice insertionFremoval control method that returns a deviceMs
status.
2. 'ower resource o0#ect that evaluates to the current on or off state of
the 'ower 3esource.
+.3.9
9.4."
C!TM %-. device control method used to set the %-. controller transfer
timings.
6.6.2.4.2
C!T3 20#ect evaluates to a ,nicode string to descri0e a device. +.4.9
C!,N 20#ect that evaluates to the slot uni:ue %- num0er for a slot. +.4.8
C!W! 20#ect that returns the source event that caused the s(stem to wake. 9.3.*
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 2+4
Ta!le A-A( 5efined ;eneric 3!Cect and Control Methods
3!Cect 5escription "eference
CTC/ 3eserved for use 0( the A!1 compiler. 49.2.4.4
CTC4 Thermal Hone o0#ect that contains thermal constant for 'assive cooling. 44.3.6
CTC2 Thermal Hone o0#ect that contains thermal constant for 'assive cooling. 44.3.4
CTM' Thermal Hone o0#ect that returns current temperature in tenths of
degrees Eelvin.
44.3.44
CT'C 20#ect evaluates to the current num0er of supported throttling states. 8.".3.3
CT'T Control method invoked when a devicesM em0edded temperature sensor
crosses a temperature trip point.
44.3.42
CT3A 3esource data t(pe reserved field name 49.4.8
CT3! 3esource data t(pe reserved field name 49.4.8
CT3T 20#ect provides thermal relationship information 0etween platform
devices.
44.3.43
CT!- 20#ect that conve(s Throttling !tate dependencies 8.".3."
CT!5 T(pe&!pecific 5lags fields in a Word, -Word or GWord address space
descriptor
49.4.8
CT!' Thermal Hone o0#ect that contains thermal sampling period for 'assive
cooling.
44.3.4"
CT!T 20#ect returns minimum temperature separation for deviceMs
programma0le temperature trip points.
44.3.4*
CT!! 20#ect evaluates to a ta0le of support throttling states. 8.".3.2
CTT' 3esource data t(pe reserved field name 49.4.8
BCTT! Control method used to prepare to sleep and run once awakened 9.3.+
CTS' 3esource data t(pe reserved field name 49.4.8
CT? AC'% 4. thermal Hone scope *.3.4
CT?- 20#ect evaluates to a package of device names associated with a
Thermal ?one.
44.3.4+
CT?M 20#ect indicates the thermal Hone of which a device is a mem0er. 44.3.49
CT?' Thermal Hone polling fre:uenc( in tenths of seconds. 44.3.48
C,%- -evice identification o0#ect that specifies a deviceMs uni:ue persistent
%-, or a control method that generates it.
+.4.6
C,'C 20#ect provides ,!; port capa0ilities information.. 6.4"
C,'- 20#ect that returns user presence information. 6.49.4
C,'' 20#ect evaluates to user presence polling interval. 6.49.2
CD'2 3eturns 32&0it integer indicating the video post options. ;.".+
BCWAE 'ower management control method run once s(stem is awakened. 9.3.9
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
2+2 Advanced Configuration and 'ower %nterface !pecification
6.7 Predefned Objects
The AM1 interpreter of an AC'% compati0le operating s(stem supports the evaluation of a num0er of
predefined o0#ects. The o0#ects are considered J0uilt inL to the AM1 interpreter on the target operating
s(stem.
A list of predefined o0#ect names are shown in the following ta0le.
Ta!le A-AA Predefined 3!Cect 0a%es
0a%e 5escription
BC$1 $lo0al 1ock
BC2! Name of the operating s(stem
BC2!% 2perating !(stem %nterface support
BC3.D 3evision of the AC'% specification that 2!'M implements.
6.7.1 \_GL (Global Lock Mutex)
This predefined o0#ect is a Mute/ o0#ect that 0ehaves like a Mute/ as defined in section 49.*.96, JMute/
=-eclare !(nchroniHationFMute/ 20#ect>,L with the added 0ehavior that ac:uiring this Mute/ also ac:uires
the shared environment $lo0al 1ock defined in section *.2.4.4, J$lo0al 1ock.L This allows Control
Methods to e/plicitl( s(nchroniHe with the $lo0al 1ock if necessar(.
6.7.2 \_OSI (Operating System Interfaces)
This o0#ect provides the platform with the a0ilit( to :uer( 2!'M to determine the set of AC'% related
interfaces, 0ehaviors, or features that the operating s(stem supports.
The C2!% method has one argument and one return value. The argument is an 2! vendor defined string
representing a set of 2! interfaces and 0ehaviors or an AC'% defined string representing an operating
s(stem and an AC'% feature group of the form, J=SAendorString&&eat're4ro'pStringL.
S)ntax
_0S# (Interface)LB BooleanResult
Argu%ents
Interface< Strin, U Strin, 'E' Strin,
!pecifies the 2! interface F 0ehavior compati0ilit( string or the 5eature $roup !tring, as defined
in Ta0le *&*9, or the 2! Dendor !tring 'refi/&2! Dendor !pecific !tring. 2! Dendor !tring
'refi/es are defined in Ta0le *&*+.
"eturn 7alue
BooleanResult< DWord)on2t
A return value of / indicates that interface, 0ehavior, feature, is not supported.
A return value of /55555555 indicates that interface, 0ehavior, feature, is supported.
2!'M ma( indicate support for multiple 2! interface F 0ehavior strings if the operating s(stem supports
the 0ehaviors. 5or e/ample, a newer version of an operating s(stem ma( indicate support for strings from
all or some of the prior versions of that operating s(stem.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 2+3
C2!% provides the platform with the a0ilit( to support new operating s(stem versions and their associated
features when the( 0ecome availa0le. 2!'M can choose to e/pose new functionalit( 0ased on the C2!%
argument string. That is, 2!'M can use the strings passed into C2!% to ensure compati0ilit( 0etween older
platforms and newer operating s(stems 0( maintaining known compati0le 0ehavior for a platform. As such,
it is recommended that C2!% 0e evaluated 0( the BC!;.%N% control method so that platform compati0le
0ehavior or features are availa0le earl( in operating s(stem initialiHation.
!ince feature group functionalit( ma( 0e dependent on 2!'M implementation, it ma( 0e re:uired that 2!
vendor&defined strings 0e checked 0efore feature group strings.
'latform developers should consult 2! vendor specific information for 2! vendor defined strings
representing a set of 2! interfaces and 0ehaviors. AC'% defined strings representing an operating s(stem
and an AC'% feature group are listed in the following ta0les.
Ta!le A-A- 3perating S)ste% 7endor Strings
3perating S)ste% 7endor String Prefix 5escription
J5ree;!-L 5ree ;!-
J@'&,AL @' ,ni/ 2perating .nvironment
J1inu/L $N,F1inu/ 2perating s(stem
J2penDM!L @' 2penDM! 2perating .nvironment
JWindowsL Microsoft Windows
Ta!le A-A. 6eature ;roup Strings
6eature ;roup String 5escription
JModule -eviceL 2!'M supports the declaration of module device =AC'%"> in the
namespace and will enumerate o0#ects under the module device scope.
J'rocessor -eviceL 2!'M supports the declaration of processors in the namespace using the
AC'%9 processor device @%-.
J3. Thermal ModelL 2!'M supports the e/tensions to the AC'% thermal model in 3evision
3..
J./tended Address !pace
-escriptorL
2!'M supports the ./tended Address !pace -escriptor
J3. C!C' ./tensionsL 2!'M evaluates C!C' with the additional acoustic limit and power limit
arguments defined in AC'% 3..
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
2+" Advanced Configuration and 'ower %nterface !pecification
C2!% ./ample A!1 using 2! vendor defined string<
Scope (_SB) //Scope

!ame (<00S$ () // :lobal variable for t1pe of 0S.


// <hi2 method2 2et2 the P<00SP variable dependin, on the t1pe of 0S
// in2talled on the 212tem.
// <00S L 4 // Window2 H= V S%
// <00S L 3 // Window2 ;e.
// <00S L F // Window2 3((( 0S or above ver2ion.
// <00S L . // Window2 RP 0S or above ver2ion.
;ethod (_#!#)

#f ()ondRef0f (_0S#$6ocal())

#f (\_0S# (PWindow2 3((4P))

Store(.$ <00S)
/
/
%l2e

Store (\_0S$ local()


#f (6%8ual (local($ P;icro2oft Window2 !<P))

Store (F$ <00S)


/
%l2e#f (6%8ual (6ocal($ P;icro2oft Window2P))

Store (4$ <00S)


/
%l2e#f (6%8ual (6ocal($ P;icro2oft Window2;%>;illennium %ditionP))

Store (3$ <00S)


/
/
/
/
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 2+*
C2!% ./ample A!1 using an AC'% defined string<
Scope (_SB)
;ethod (_#!#)
#f ()ondRef0f (_0S#$6ocal())
#f (\_0S# (P;odule DeviceP))
//%-po2e P)# Root Brid,e under ;odule Device
6oad<able('0%;4P$ '0%;#DP$ '<able4P$$$)/
%l2e
// %-po2e P)# Root Brid,e under \_SB W 0S doe2 not 2upport ;odule Device
6oad<able('0%;4P$ '0%;#DP$ '<able3P$$$)/
/
%l2e
// Default Behavior
6oad<able('0%;4P$ '0%;#DP$ '<able3P$$$)/
/ //_#!# ;ethod
/ //_SB 2cope
DefinitionBloc+ (';D4SSD<.amlP$'0%;4P$(-(3$
'0%;#DP$ P<able4P$ ()
Scope(\_SB)
Device (\_SB.!0D()
!ame (_"#D$ P&)P#(((.P) // ;odule device
!ame (_X#D$ ()
!ame (_PRS$ Re2ource<emplate() ... /)
;ethod (_SRS$ 4) ... /
;ethod (_)RS$ () ... /
Device (P)#() // P)# Root Brid,e
!ame (_"#D$ %#S&#D(PP!P(&(FP))
!ame (_X#D$ ()
!ame (_BB!$ (-(()
!ame (_PRS$ Re2ource<emplate () .../)
/ // end of P)# Root Brid,e
/ // end of ;odule device
/ // end of \_SB Scope
/ // end of Definition Bloc+
DefinitionBloc+ (';D4SSD<.amlP$'0%;4P$(-(3$
'0%;#DP$ P<able3P$ ()
Scope(\_SB)
Device (P)#() // P)# Root Brid,e
!ame (_"#D$ %#S&#D(PP!P(&(FP))
!ame (_X#D$ ()
!ame (_BB!$ (-(()
!ame (_PRS$ Re2ource<emplate () .../)
/ // end of P)# Root Brid,e
/ // end of \_SB Scope
/ // end of Definition Bloc+
6.7.3 \_OS (OS Name Object)
This predefined o0#ect evaluates to a string that identifies the operating s(stem. %n ro0ust 2!'M
implementations, BC2! evaluates differentl( for each 2! release. This ma( allow AM1 code to
accommodate differences in 2!'M implementations. This value does not change with different revisions of
the AM1 interpreter.
6.7.4 \_REV (Revision Data Object)
This predefined o0#ect evaluates to the revision of the AC'% !pecification that the specified BC2!
implements as a -W23-. 1arger values are newer revisions of the AC'% specification.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
2++ Advanced Configuration and 'ower %nterface !pecification
6.8 System Confguration Objects
6.8.1 _PIC Method
The BC'%C optional method is to report to the ;%2! the current interrupt model used 0( the 2!. This control
method returns nothing. The argument passed into the method signifies the interrupt model 2!'M has
chosen, '%C mode, A'%C mode, or !A'%C mode. Notice that calling this method is optional for 2!'M. %f
the method is never called, the ;%2! must assume '%C mode. %t is important that the ;%2! save the value
passed in 0( 2!'M for later use during wake operations.
DPIC>x?H
C'%C=> \) '%C Mode
C'%C=4> \) A'%C Mode
C'%C=2> \) !A'%C Mode
C'%C=3&n> \) 3eserved
7 Confguration
This section specifies the o0#ects 2!'M uses to configure devices. There are three t(pes of configuration
o0#ects<
-evice identification o0#ects associate platform devices with 'lug and 'la( %-s.
-evice configuration o0#ects declare and configure hardware resources and characteristics for
devices enumerated via AC'%.
-evice insertion and removal o0#ects provide mechanisms for handling d(namic insertion and
removal of devices.
This section also defines the AC'% deviceIresource descriptor formats. -eviceIresource descriptors are
used as parameters 0( some of the device configuration o0#ects.
7.1 Device Identifcation Objects
-evice identification o0#ects associate each platform device with a 'lug and 'la( device %- for each
device. All the device identification o0#ects are listed Ta0le +&4<
Ta!le --+ 5evice Identification 3!Cects
3!Cect 5escription
CA-3 20#ect that evaluates to a deviceMs address on its parent 0us.
CC%- 20#ect that evaluates to a deviceMs 'lug and 'la(&compati0le %- list.
C--N 20#ect that associates a logical software name =for e/ample, C2M4> with a device.
C@%- 20#ect that evaluates to a deviceMs 'lug and 'la( hardware %-.
CM1! 20#ect that provides a human reada0le description of a device in multiple languages.
C'1- 20#ect that provides ph(sical location description information.
C!,N 20#ect that evaluates to the slot&uni:ue %- num0er for a slot.
C!T3 20#ect that contains a ,nicode identifier for a device.
C,%- 20#ect that specifies a deviceMs uni:ue persistent %-, or a control method that generates it.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 2+9
5or an( device that is not on an enumera0le t(pe of 0us =for e/ample, an %!A 0us>, 2!'M enumerates the
devicesM 'lug and 'la( %-=s> and the AC'% ;%2! must suppl( an C@%- o0#ect =plus an optional CC%-
o0#ect> for each device to ena0le 2!'M to do that. 5or devices on an enumera0le t(pe of 0us, such as a 'C%
0us, the AC'% s(stem must identif( which device on the enumera0le 0us is identified 0( a particular 'lug
and 'la( %-K the AC'% ;%2! must suppl( an CA-3 o0#ect for each device to ena0le this. A device o0#ect
must contain either an C@%- o0#ect or an CA-3 o0#ect, 0ut can contain 0oth.
%f an( of these o0#ects are implemented as control methods, these methods ma( depend on operation
regions. !ince the control methods ma( 0e evaluated 0efore an operation region provider 0ecomes
availa0le, the control method must 0e structured to e/ecute in the a0sence of the operation region provider.
=C3.$ methods notif( the ;%2! of the presence of operation region providers.> When a control method
cannot determine the current state of the hardware due to a lack of operation region provider, it is
recommended that the control method should return the condition that was true at the time that control
passed from the ;%2! to the 2!. =The control method should return a default, 0oot value>.
7.1.1 _ADR (Address)
This o0#ect is used to suppl( 2!'M with the address of a device on its parent 0us. An CA-3 o0#ect must
0e used when specif(ing the address of an( device on a 0us that has a standard enumeration algorithm =see
".9, JConfiguration and 'lug and 'la(L, for the situations when these devices do appear in the AC'% name
space>.
An CA-3 o0#ect can 0e used to provide capa0ilities to the specified address even if a device is not present.
This allows the s(stem to provide capa0ilities to a slot on the parent 0us.
2!'M infers the parent 0us from the location of the CA-3 o0#ectMs device package in the AC'%
namespace. 5or more information a0out the positioning of device packages in the AC'% namespace, see
section 49.*.28, J-eviceI-eclare ;usF-evice 'ackage.L
CA-3 o0#ect information must 0e static and can 0e defined for the following 0us t(pes listed in Ta0le +&2.
Ta!le --& DA5" 3!Cect <us T)pes
<2S Address encoding
.%!A .%!A slot num0er I5
5lopp( ;us -rive select values used for programming the flopp( controller to access the specified
%NT43 unit num0er. The CA-3 20#ects should 0e sorted 0ased on drive select encoding
from &3.
%-. Controller I'rimar( Channel, 4I!econdar( Channel
%-. Channel IMaster drive, 4I!lave drive
%ntel] @igh
-efinition Audio
@igh word I !-% =!erial -ata %n> %- of the codec that contains the function group.
1ow word I Node %- of the function group.
'C% @igh wordI-evice Y, 1ow wordI5unction Y. =for e/ample, device 3, function 2 is
/32>. To refer to all the functions on a device Y, use a function num0er of
5555>.
'CMC%A !ocket YK I5irst !ocket
'C CA3- !ocket YK I5irst !ocket
!erial ATA !ATA 'ort< @igh wordP3oot port Y, 1ow wordPport num0er off of a !ATA port
multiplier, or /5555 if no port multiplier attached. =5or e/ample, root port 2 would 0e
/25555. %f instead a port multiplier had 0een attached to root port 2, the ports
connected to the multiplier would 0e encoded /2, /24, etc.> The
value /55555555 is reserved.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
2+8 Advanced Configuration and 'ower %nterface !pecification
<2S Address encoding
!M;us 1owest !lave Address
,!; 3oot @,; 2nl( one child of the host controller. %t must have an CA-3 of . No other children or
values of CA-3 are allowed.
,!; 'orts 'ort num0er
7.1.2 _CID (Compatible ID)
This optional o0#ect is used to suppl( 2!'M with a deviceMs 'lug and 'la(&Compati0le -evice %-. ,se
CC%- o0#ects when a device has no other defined hardware standard method to report its compati0le %-s.
A CC%- o0#ect evaluates to either<
A single Compati0le -evice %-
A package of Compati0le -evice %-s for the device P in the order of preference, highest preference
first.
.ach Compati0le -evice %- must 0e either<
A valid @%- value =a 32&0it compressed .%!A t(pe %- or a string such as JAC'%"L>.
A string that uses a 0us&specific nomenclature. 5or e/ample, CC%- can 0e used to specif( the 'C% %-.
The format of a 'C% %- string is one of the following<
PCI\CC_ccss
PCI\CC_ccsspp
PCI\VEN_!DEV_""""!#$B#Y#_ssssssss!REV_rr
PCI\VEN_!DEV_""""!#$B#Y#_ssssssss
PCI\VEN_!DEV_""""!REV_rr
PCI\VEN_!DEV_""""
Where<
cc I he/adecimal representation of the Class Code 0(te
ss I he/adecimal representation of the !u0class Code 0(te
pp I he/adecimal representation of the 'rogramming %nterface 0(te
vvvv I he/adecimal representation of the Dendor %-
dddd I he/adecimal representation of the -evice %-
ssssssss I he/adecimal representation of the !u0s(stem %-
rr I he/adecimal representation of the 3evision 0(te
A compati0le %- retrieved from a CC%- o0#ect is onl( meaningful if it is a non&N,11 value.
./ample A!1<
Device (RS7)
!ame (_"#D$ %#S&#D (PP!P(F(FP)) // P) Ae1board )ontroller
!ame (_)#D$ %#S&#D (PP!P(F(BP))
/
7.1.3 _DDN (DOS Device Name)
This o0#ect is used to associate a logical name =for e/ample, C2M4> with a device. This name can 0e used
0( applications to connect to the device.
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7.1.4 _HID (Hardware ID)
This o0#ect is used to suppl( 2!'M with the deviceMs 'lug and 'la( hardware %-.
8
When descri0ing a
platform, use of an( C@%- o0#ects is optional. @owever, a C@%- o0#ect must 0e used to descri0e an( device
that will 0e enumerated 0( 2!'M. 2!'M onl( enumerates a device when no 0us enumerator can detect the
device %-. 5or e/ample, devices on an %!A 0us are enumerated 0( 2!'M. ,se the CA-3 o0#ect to descri0e
devices enumerated 0( 0us enumerators other than 2!'M.
A C@%- o0#ect evaluates to either a numeric 32&0it compressed .%!A t(pe %- or a string. %f a string, the
format must 0e an alphanumeric 'N' or AC'% %- with no asterisk or other leading characters.
A valid 'N' %- must 0e of the form '&&&QQQQ* where A is an uppercase letter and Y is a he/ digit. A
valid AC'% %- must 0e of the form '&)P#QQQQ* where Y is a he/ digit.
./ample A!1<
!ame (_"#D$ %#S&#D (PP!P()()P)) // )ontrolE;ethod Power Button
!ame (_"#D$ %#S&#D (P#!<(=((P)) // 5irmware "ub
!ame (_"#D$ P&)P#(((FP) // &) adapter device
7.1.5 _MLS (Multiple Language String)
The CM1! o0#ect provides 2!'M a human reada0le description of a device in multiple languages. This
information ma( 0e provided to the end user when the 2!'M is una0le to get an( other information a0out
this device. Although this functionalit( is also provided 0( the C!T3 o0#ect, CM1! e/pands that
functionalit( and provides vendors with the capa0ilit( to provide multiple strings in multiple languages.
The CM1! o0#ect evaluates to a package of packages. .ach su0&package consists of a 1anguage identifier
and corresponding unicode string for a given locale. !pecif(ing a language identifier allows 2!'M to
easil( determine if support for displa(ing the ,nicode string is availa0le. 2!'M can use this information
to determine whether or not to displa( the device string, or which string is appropriate for a userMs preferred
locale.
%t is assumed that 2!'M will alwa(s support the primar( .nglish locale to accommodate .nglish
em0edded in a non&.nglish string, such as a 0rand name.
%f 2!'M doesnMt support the specific su0&language %- it ma( choose to use the primar( language %- for
displa(ing device te/t.
The package is of the following format<
'ackage=> _ 'ackage=>_1anguage %-, ,nicode device description string`,
'ackage=>_1anguage %-, ,nicode device description string`,
N
`
1anguage %- <\ string <\ a string identif(ing the language. This string follows the format specified in
35C 3++. Additionall(, the following strings are supported<
,nicode device description string <\ ,nicode =,T5&4+> string . The ,nicode device description string
contains the language&specific description of the device corresponding to the 1anguage%-.
./ample A!1<
8
A 'lug and 'la( =.%!A> %- can 0e o0tained 0( sending e&mail to pnpidamicrosoft.com.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
29 Advanced Configuration and 'ower %nterface !pecification
Device (RS7)
!ame (_&DR$ (-(((3(((4)
!ame ( _;6S$ Pac+a,e() Pac+a,e(3)'en*$ Xnicode(P&);% 2uper D@D
controllerP)//)
/
%n addition to supporting the e/isting strings in 35C 3++, Ta0le +&3 lists aliases that are also supported.
Ta!le --# Additional Alias Strings
35C !tring !upported Alias !tring
Hh&@ans Hh&chs
Hh&@ant Hh&cht
7.1.6 _PLD (Physical Device Location)
This optional o0#ect is a method that conve(s to 2!'M a general description of the ph(sical location of a
deviceMs e/ternal connection point. The C'1- ma( 0e child o0#ect for an( AC'% Namespace o0#ect the
s(stem wants to descri0e. This information can 0e used 0( s(stem software to descri0e to the user which
specific connector or device input mechanism ma( 0e used for a given task or ma( need user intervention
for correct operation. The C'1- should onl( 0e evaluated when its parent device is present as indicated 0(
the deviceMs presence mechanism =i.e. C!TA or other>
An e/ternall( e/pose device connection point can reside on an( surface of a s(stemMs housing. The C'1-
method returns data to descri0e the general location of where the deviceMs connection point resides. 2ne
ph(sical device ma( have several connection points. A C'1- descri0es a single device connection point.
All data 0its are interpreted as though the user is facing the front of the s(stem. The data 0its also assume
that if the s(stem is capa0le of opening up like a laptop that the device ma( e/ist on the 0ase of the laptop
s(stem or on the lid. %n the case of the latter, the J1idL 0it =descri0ed 0elow> should 0e set indicating the
device connection point is on the lid. %f the device is on the lid, the description descri0es the deviceMs
connection point location when the s(stem is opened with the lid up. %f the device connection point is not
on the lid, then the description descri0es the deviceMs connection point location when the s(stem with the
lid closed.
The location of a device connection point ma( change as a result of the s(stem connecting or disconnecting
to a docking station or a port replicator. As such, Notif( event of t(pe /8 will cause 2!'M to re&evaluate
the C'1- o0#ect residing under the particular device notified. %f a platform is una0le to detect the change
of connecting or disconnecting to a docking station or port replicator, a C'1- o0#ect should not 0e used to
descri0e the device connection points that will change location after such an event.
This method returns a package containing, a single or multiple 0uffer entries. At least one 0uffer entr(
must 0e returned using the 0it definitions 0elow.
Arguments<
None

;uffer 3esult Code<
;it +< I 3evision. The current revision is /4K all other values are reserved.
;it 9 I %gnore Color. %f this 0it is set, the Color field is ignored, as the color is unknown.
;it 34<8 I Color I 2"0it 3$; value for the color of the device connection point.
;it "9<32 I Width< -escri0es, in millimeters, the width =widest point> of the device connection point.
;it +3<"8 I @eight< -escri0es, in millimeters, the height of the device connection.
;it +" I ,ser Disi0le< !et if the device connection point can 0e seen 0( the user.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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;it +* I -ock< !et if the device connection point resides in a docking station or port replicator.
;it ++ I 1id< !et if this device connection point resides on the lid of laptop s(stem.
;it +6<+9 I 'anel< -escri0es which panel surface of the s(stemMs housing the device connection point
resides on.
I Top
4 I ;ottom
2 I 1eft
3 I 3ight
" I 5ront
* I ;ack
+ I ,nknown =Dertical 'osition and @oriHontal 'osition will 0e ignored>
;it 94<9 I Dertical 'osition on the panel where the device connection point resides.
I ,pper
4 I Center
2 I 1ower
;it 93<92 I @oriHontal 'osition on the panel where the device connection point resides.
I 1eft
4 I Center
2 I 3ight
;it 99<9" I !hape< -escri0es the shape of the device connection point.
I 3ound
4 I 2val
2 I !:uare
3 I Dertical 3ectangle
" I @oriHontal 3ectangle
* I Dertical TrapeHoid
+ I @oriHontal TrapeHoid
9 I ,nknown
;it 98 I $roup 2rientation< if !et, indicates vertical grouping, otherwise horiHontal is assumed.
;it 8+<96 I $roup Token< ,ni:ue numerical value identif(ing a group.
;it 6"<89 I $roup 'osition< %dentifies this device connection pointMs position in the group =i.e. 4
st
, 2
nd
>
;it 6* I ;a(< !et if descri0ing a device in a 0a( or if device connection point is a 0a(.
;it 6+ I .#ecta0le< !et if the device is e#ecta0le. %ndicates e#ecta0ilit( in the a0sence of C.7/ o0#ects.
;it 69 I 2!'M .#ection re:uired< !et if 2!'M needs to 0e involved with e#ection process. ,ser&
operated ph(sical hardware e#ection is not possi0le. ;it 4*<68 I Ca0inet Num0er. 5or single ca0inet
s(stem, this field is alwa(s .
;it 443<4+ I Card cage Num0er. 5or single card cage s(stem, this field is alwa(s .
;it 429<44" I 3eserved, must contain a value of .
All additional 0uffer entries returned, ma( contain 2.M specific data, 0ut must 0egin in a _$,%-, data`
pair. These additional data ma( provide complimentar( ph(sical location information specific to certain
s(stems or class of machines.
;uffers 4 I N 3esult Code =2ptional><
;uffer 4 ;it 429< I $,%- 4
;uffer 2 ;it 429< I -ata 4
;uffer 3 ;it 429< I $,%- 2
;uffer " ;it 429< I -ata 2
NN
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292 Advanced Configuration and 'ower %nterface !pecification
7.1.7 _STR (String)
The C!T3 o0#ect evaluates to a ,nicode string that ma( 0e used 0( an 2! to provide information to an end
user descri0ing the device. This information is particularl( valua0le when no other information is availa0le.
./ample A!1<
Device (RS7)
!ame (_&DR$ (-(((3(((4)
!ame (_S<R$ Xnicode (P&);% 2uper D@D controllerP))
/
Then, when all else fails, an 2! can use the info included in the C!T3 o0#ect to descri0e the hardware to
the user.
7.1.8 _SUN (Slot User Number)
C!,N is an o0#ect that evaluates to the slot&uni:ue %- num0er for a slot. C!,N is used 0( 2!'M ,% to
identif( slots for the user. 5or e/ample, this can 0e used for 0atter( slots, 'C% slots, 'CMC%A slots, or
swappa0le 0a( slots to inform the user of what devices are in each slot. C!,N evaluates to an integer that is
the num0er to 0e used in the user interface. This num0er is re:uired to 0e uni:ue among the slots of the
same t(pe. %t is also recommended that this num0er match the slot num0er printed on the ph(sical slot
whenever possi0le.
7.1.9 _UID (Unique ID)
This o0#ect provides 2!'M with a logical device %- that does not change across re0oots. This o0#ect is
optional, 0ut is re:uired when the device has no other wa( to report a persistent uni:ue device %-. The
C,%- must 0e uni:ue across all devices with either a common C@%- or CC%-. This is 0ecause a device
needs to 0e uni:uel( identified to the 2!'M, which ma( match on either a C@%- or a CC%- to identif( the
device. The uni:ueness match must 0e true regardless of whether the 2!'M uses the C@%- or the CC%-.
2!'M t(picall( uses the uni:ue device %- to ensure that the device&specific information, such as network
protocol 0inding information, is remem0ered for the device even if its relative location changes. 5or most
integrated devices, this o0#ect contains a uni:ue identifier.
A C,%- o0#ect evaluates to either a numeric value or a string.
7.2 Device Confguration Objects
This section descri0es o0#ects that provide 2!'M with device specific information and allow 2!'M to
configure device operation and resource utiliHation.
2!'M uses device configuration o0#ects to configure hardware resources for devices enumerated via AC'%.
-evice configuration o0#ects provide information a0out current and possi0le resource re:uirements, the
relationship 0etween shared resources, and methods for configuring hardware resources.
0oteH these o0#ects must onl( 0e provided for devices that cannot 0e configured 0( an( other hardware
standard such as 'C%, 'CMC%A, and so on.
When 2!'M enumerates a device, it calls C'3! to determine the resource re:uirements of the device. %t
ma( also call CC3! to find the current resource settings for the device. ,sing this information, the 'lug and
'la( s(stem determines what resources the device should consume and sets those resources 0( calling the
deviceMs C!3! control method.
%n AC'%, devices can consume resources =for e/ample, legac( ke(0oards>, provide resources =for e/ample,
a proprietar( 'C% 0ridge>, or do 0oth. ,nless otherwise specified, resources for a device are assumed to 0e
taken from the nearest matching resource a0ove the device in the device hierarch(.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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!ome resources, however, ma( 0e shared amongst several devices. To descri0e this, devices that share a
resource =resource consumers> must use the e/tended resource descriptors =/9&/A> descri0ed in section
+.".3, J1arge 3esource -ata T(pe.L These descriptors point to a single device o0#ect =resource producer>
that claims the shared resource in its C'3!. This allows 2!'M to clearl( understand the resource
dependencies in the s(stem and move all related devices together if it needs to change resources.
5urthermore, it allows 2!'M to allocate resources onl( to resource producers when devices that consume
that resource appear.
The device configuration o0#ects are listed in Ta0le +&".
Ta!le --( 5evice Configuration 3!Cects
3!Cect 5escription
CC3! 20#ect that specifies a deviceMs c'rrent resource settings, or a control method that generates
such an o0#ect.
C-%! Control method that disa0les a device.
C-MA 20#ect that specifies a deviceMs c'rrent resources for -MA transactions.
C5%A 20#ect used to provide correlation 0etween the fi/ed&hardware register 0locks defined in the
5A-T and the devices that implement these fi/ed&hardware registers.
C$!; 20#ect that provides the $lo0al !(stem %nterrupt ;ase for a hot&plugged %F2 A'%C device.
C@'' 20#ect that specifies the cache&line siHe, latenc( timer, !.33 ena0le, and '.33 ena0le values
to 0e used when configuring a 'C% device inserted into a hot&plug slot or initial configuration
of a 'C% device at s(stem 0oot.
C@'A 20#ect that provides device parameters when configuring a 'C% device inserted into a hot&plug
slot or initial configuration of a 'C% device at s(stem 0oot. !upersedes C@''.
CMAT 20#ect that evaluates to a 0uffer of MA-T A'%C !tructure entries.
C2!C An o0#ect 2!'M evaluates to conve( specific software support F capa0ilities to the platform
allowing the platform to configure itself appropriatel(.
C'3! An o0#ect that specifies a deviceMs possible resource settings, or a control method that generates
such an o0#ect.
C'3T 20#ect that specifies the 'C% interrupt routing ta0le.
C'AM 20#ect that specifies a pro/imit( domain for a device.
C!1% 20#ect that provides updated distance information for a s(stem localit(.
C!3! Control method that sets a deviceMs settings.
7.2.1 _CRS (Current Resource Settings)
This re:uired o0#ect evaluates to a 0(te stream that descri0es the s(stem resources currentl( allocated to a
device. Additionall(, a 0us device must suppl( the resources that it decodes and can assign to its children
devices. %f a device is disa0led, then CC3! returns a valid resource template for the device, 0ut the actual
resource assignments in the return 0(te stream are ignored. %f the device is disa0led when CC3! is called, it
must remain disa0led.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
29" Advanced Configuration and 'ower %nterface !pecification
The format of the data contained in a CC3! o0#ect follows the formats defined in section +.", J3esource
-ata T(pes for AC'%,L a compati0le e/tension of the formats specified in the 'N';%2! specification.
6
The
resource data is provided as a series of data structures, with each of the resource data structures having a
uni:ue tag or identifier. The resource descriptor data structures specif( the standard 'C s(stem resources,
such as memor( address ranges, %F2 ports, interrupts, and -MA channels.
Arguments<
None
3esult Code<
;(te stream
7.2.2 _DIS (Disable)
This control method disa0les a device. When the device is disa0led, it must not 0e decoding an( hardware
resources. 'rior to running this control method, 2!'M will have alread( put the device in the -3 state.
When a device is disa0led via the C-%!, the C!TA control method for this device must return with the
-isa0led 0it set.
Arguments<
None
3esult Code<
None
7.2.3 _DMA (Direct Memory Access)
This optional o0#ect returns a 0(te stream in the same format as a CC3! o0#ect. C-MA is onl( defined
under devices that represent 0uses. %t specifies the ranges the 0us controller =0ridge> decodes on the child&
side of its interface. =This is analogous to the CC3! o0#ect, which descri0es the resources that the 0us
controller decodes on the parent&side of its interface.> An( ranges descri0ed in the resources of a C-MA
o0#ect can 0e used 0( child devices for -MA or 0us master transactions.
The C-MA o0#ect is onl( valid if a CC3! o0#ect is also defined. 2!'M must re&evaluate the C-MA o0#ect
after an C!3! o0#ect has 0een e/ecuted 0ecause the C-MA ranges resources ma( change depending on
how the 0ridge has 0een configured.
%f the C-MA o0#ect is not present for a 0us device, the 2! assumes that an( address placed on a 0us 0( a
child device will 0e decoded either 0( a device on the 0us or 0( the 0us itself, =in other words, all address
ranges can 0e used for -MA>.
5or e/ample, if a platform implements a 'C% 0us that cannot access all of ph(sical memor(, it has a C-MA
o0#ect under that 'C% 0us that descri0es the ranges of ph(sical memor( that can 0e accessed 0( devices on
that 0us.
A C-MA o0#ect is not meant to descri0e an( Jmap registerL hardware that is set up for each -MA
transaction. %t is meant onl( to descri0e the -MA properties of a 0us that cannot 0e changed without
reevaluating the C!3! method.
Arguments<
None
3esult Code<
;(te stream
C-MA ./ample A!1<
6
'lug and 'la( ;%2! !pecification Dersion 4.A, Ma( *, 466", Compa: Computer Corp., %ntel Corp.,
'hoeni/ Technologies 1td.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 29*
Device(BXS()

//
// <he _D;& method return2 a re2ource template de2cribin, the
// addre22e2 that are decoded on the child 2ide of thi2
// brid,e. <he contained re2ource de2criptor2 thu2 indicate
// the addre22 ran,e2 that bu2 ma2ter2 livin, below thi2
// brid,e can u2e to 2end acce22e2 throu,h the brid,e toward a
// de2tination el2ewhere in the 212tem (e.,. main memor1).
//
// #n our ca2e$ an1 bu2 ma2ter addre22e2 need to fall between
// ( and (-=((((((( and will have (-3(((((((( added a2 the1
// cro22 the brid,e. 5urthermore$ an1 childE2ide acce22e2
// fallin, into the ran,e claimed in our _)RS will be
// interpreted a2 a peerEtoEpeer traffic and will not be
// forwarded up2tream b1 the brid,e.
//
// 0ur up2tream addre22 decoder will onl1 claim one ran,e from
// (-3((((((( to (-Gfffffff in the _)RS. <herefore _D;&
// 2hould return two JW0RD;emor1 de2criptor2$ one de2cribin,
// the ran,e below and one de2cribin, the ran,e above thi2
// PpeerEtoEpeerP addre22 ran,e.
//
;ethod(_D;&$ Re2ource<emplate()

JW0RD;emor1(
Re2ource)on2umer$
Po2Decode$ // _D%)
;in5i-ed$ // _;#5
;a-5i-ed$ // _;&5
Prefetchable$ // _;%;
ReadWrite$ // _RW
($ // _:R&
($ // _;#!
(-4fffffff$ // _;&R
(-3(((((((($ // _<R&
(-3((((((($ // _6%!
$
$
$
)
JW0RD;emor1(
Re2ource)on2umer$
Po2Decode$ // _D%)
;in5i-ed$ // _;#5
;a-5i-ed$ // _;&5
Prefetchable$ // _;%;
ReadWrite$ // _RW
($ // _:R&
(-I((((((($ // _;#!
(-Tfffffff$ // _;&R
(-3(((((((($ // _<R&
(-3((((((($ // _6%!
$
$
$
)
/)
/
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
29+ Advanced Configuration and 'ower %nterface !pecification
7.2.4 _FIX (Fixed Register Resource Provider)
This optional o0#ect is used to provide a correlation 0etween the fi/ed&hardware register 0locks defined in
the 5A-T and the devices in the AC'% namespace that implement these fi/ed&hardware registers. This
o0#ect evaluates to a package of 'lug and 'la(&compati0le %-s =32&0it compressed .%!A t(pe %-s> that
correlate to the fi/ed&hardware register 0locks defined in the 5A-T. The device under which C5%A appears
pla(s a role in the implementation of the fi/ed&hardware =for e/ample, implements the hardware or decodes
the hardwareMs address>. C5%A conve(s to 2!'M whether a given device can 0e disa0led, powered off, or
should 0e treated speciall( 0( conve(ing its role in the implementation of the AC'% fi/ed&hardware register
interfaces. This o0#ect takes no arguments.
The CC3! o0#ect descri0es a deviceMs resources. That CC3! o0#ect ma( contain a superset of the resources
in the 5A-T, as the device ma( actuall( decode resources 0e(ond what the 5A-T re:uires. 5urthermore, in
a machine that performs translation of resources within %F2 0ridges, the processor&relative resources in the
5A-T ma( not 0e the same as the 0us&relative resources in the CC3!.
.ach of fields in the 5A-T has its own corresponding 'lug and 'la( %-, as shown 0elow<
'N'C2 & !M%CCM-
'N'C24 & 'M4aC.DTC;1E F AC 'M4aC.DTC;1E
'N'C22 & 'M40C.DTC;1E F AC'M40C.DTC;1E
'N'C23 & 'M4aCCNTC;1E F AC'M4aCCNTC;1E
'N'C2" & 'M40CCNTC;1E F AC 'M40CCNTC;1E
'N'C2* & 'M2CCNTC;1E F AC 'M2CCNTC;1E
'N'C2+ & 'MCTM3C;1E F AC 'MCTM3C;1E
'N'C29 & $'.C;1E F AC$'.C;1E
'N'C28 & $'.4C;1E F AC $'.4C;1E
'N'; I 5%A.-C3TC
'N';4 I 5%A.-C3TC
'N';2 I 5%A.-C3TC
./ample A!1 for C5%A usage<
Scope(\_SB)
Device(P)#() // Root P)# Bu2
!ame(_"#D$ %#S&#D(PP!P(&(FP)) // !eed _"#D for root device
!ame(_&DR$() // Device ( on thi2 bu2
;ethod (_)RS$() // !eed current re2ource2 for root device
// Return current re2ource2 for root brid,e (
/
!ame(_PR<$ Pac+a,e() // !eed P)# #RJ routin, for P)# brid,e
// Pac+a,e with P)# #RJ routin, table information
/)
!ame(_5#R$ Pac+a,e(4)
%#S&#D(PP!P()3GP)/ // P;3 control #D
)
Device (PR.() // #S&
!ame(_&DR$(-(((T(((()
!ame(_5#R$ Pac+a,e(4)
%#S&#D(PP!P()3(P)/ // S;# command port
)
Device (!S4T) // !S4T (!at. Semi F4T$ an &)P# part)
!ame(_"#D$ %#S&#D(PP!P()(3P))
!ame(_5#R$ Pac+a,e(F)
%#S&#D(PP!P()33P)$ // P;4b event #D
%#S&#D(PP!P()3.P)$ // P;4b control #D
%#S&#D(PP!P()3=P)/ // :P%4 #D
/
/ // end PR.(
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Device (PR.F) // P; )ontrol
!ame(_&DR$(-(((T(((F)
!ame(_5#R$ Pac+a,e(.)
%#S&#D(PP!P()34P)$ // P;4a event #D
%#S&#D(PP!P()3FP)$ // P;4a control #D
%#S&#D(PP!P()3IP)$ // P; <imer #D
%#S&#D(PP!P()3TP)/ // :P%( #D
)
/ // end PR.F
/ // end P)#(
/ // end 2cope SB
7.2.5 _GSB (Global System Interrupt Base)
C$!; is an optional o0#ect that evaluates to an integer that corresponds to the $lo0al !(stem %nterrupt ;ase
for the corresponding %F2 A'%C device. The %F2 A'%C device ma( either 0e 0us enumerated =e.g. as a 'C%
device> or enumerated in the name space as descri0ed in !ection 6.48,L%F2 A'%C -eviceL. An( %F2 A'%C
device that either supports hot&plug or is not descri0ed in the MA-T must contain a C$!; o0#ect.
%f the %F2 A'%C device also contains a CMAT o0#ect, 2!'M evaluates the C$!; o0#ect first 0efore
evaluating the CMAT o0#ect. ;( providing the $lo0al !(stem %nterrupt ;ase of the %F2 A'%C, this o0#ect
ena0les 2!'M to process onl( the CMAT entries that correspond to the %F2 A'%C device. !ee section +.2.8,
JCMAT =Multiple A'%C Ta0le .ntr(>L. !ince CMAT is allowed to potentiall( return all the MA-T entries
for the entire platform, C$!; is needed in the %F2 A'%C device scope to ena0le 2!'M to identif( the
entries that correspond to that device.
%f an %F2 A'%C device is activated 0( a device&specific driver, the ph(sical address used to access the %F2
A'%C will 0e e/posed 0( the driver and cannot 0e determined from the CMAT o0#ect. %n this case, 2!'M
cannot use the CMAT o0#ect to determine the $lo0al !(stem %nterrupt ;ase corresponding to the %F2 A'%C
device and hence re:uires the C$!; o0#ect.
Arguments<
None
3esults<
+"&0it value representing the $lo0al !(stem %nterrupt ;ase for the corresponding %F2A'%C device
as defined in !ection *.2.42, J$lo0al !(stem %nterruptsL.
./ample A!1 for C$!; usage for a non&'C% 0ased %F2 A'%C -evice<
Scope(\_SB)
Y
Device(&P#)) // #/0 &P#) Device
!ame(_"#D$ '&)P#(((H*) // &)P# #D for #/0 &P#)
!ame(_)RS$ Re2ource<emplate()
Y/) // onl1 one re2ource pointin, to #/0 &P#) re,i2ter ba2e
;ethod(_:SB)
Return ((-4() // :lobal S12tem #nterrupt Ba2e for #/0 &P#) 2tart2 at 4I
/
/ // end &P#)
/ // end 2cope SB
./ample A!1 for C$!; usage for a 'C%&0ased %F2 A'%C -evice<
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Scope(\_SB)
Device(P)#() // "o2t brid,e
!ame(_"#D$ %#S&#D(PP!P(&(FP)) // !eed _"#D for root device
!ame(_&DR$ ()
Device(P)#4) // #/0 &P#) P)# Device
!ame(_&DR$(-(((T(((()
;ethod(_:SB)
Return ((-4=) // :lobal S12tem #nterrupt Ba2e for #/0 &P#) 2tart2 at 3.
/
/ // end P)#4
/ // end P)#(
/ // end 2cope SB
7.2.6 _HPP (Hot Plug Parameters)
This optional o0#ect evaluates to the cache&line siHe, latenc( timer, !.33 ena0le, and '.33 ena0le values
to 0e used when configuring a 'C% device inserted into a hot&plug slot or for performing configuration of a
'C% devices not configured 0( the ;%2! at s(stem 0oot. The o0#ect is placed under a 'C% 0us where this
0ehavior is desired, such as a 0us with hot&plug slots. C@'' provided settings appl( to all child 0uses, until
another C@'' o0#ect is encountered.
Arguments<
None
3esult Code<
;ethod (_"PP$ ()
Return (Pac+a,e(.)
(-(=$ // )ache6ineSiCe in DW0RDS
(-.($ // 6atenc1<imer in P)# cloc+2
(-(4$ // %nable S%RR (Boolean)
(-(( // %nable P%RR (Boolean)
/)
/
Ta!le --A DHPP
6ield 6or%at 5efinition
Cache&line siHe %NT.$.3 Cache&line siHe reported in num0er of -W23-s.
1atenc( timer %NT.$.3 1atenc( timer value reported in num0er of 'C% clock c(cles.
.na0le !.33 %NT.$.3 When set to 4, indicates that action must 0e performed to ena0le !.33
in the command register.
.na0le '.33 %NT.$.3 When set to 4, indicates that action must 0e performed to ena0le '.33
in the command register.
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7.2.6.1
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Example: Using _HPP
Scope(\_SB)
Device(P)#() // Root P)# Bu2
!ame(_"#D$ %#S&#D(PP!P(&(FP)) // _"#D for root device
!ame(_&DR$() // Device ( on thi2 bu2
;ethod (_)RS$() // !eed current re2ource2 for root dev
// Return current re2ource2 for root brid,e (
/
!ame(_PR<$ Pac+a,e() // !eed P)# #RJ routin, for P)# brid,e
// Pac+a,e with P)# #RJ routin, table information
/)
Device (P3P4) // 5ir2t P)#EtoEP)# brid,e (!o "ot Plu, 2lot2)
!ame(_&DR$(-((()(((() // DeviceQ)h$ 5uncQ( on bu2 P)#(
!ame(_PR<$ Pac+a,e() // !eed P)# #RJ routin, for P)# brid,e
// Pac+a,e with P)# #RJ routin, table information
/)
/ // end P3P4
Device (P3P3) // Second P)#EtoEP)# brid,e (Bu2 contain2 "ot plu, 2lot2)
!ame(_&DR$(-(((%(((() // DeviceQ%h$ 5uncQ( on bu2 P)#(
!ame(_PR<$ Pac+a,e() // !eed P)# #RJ routin, for P)# brid,e
// Pac+a,e with P)# #RJ routin, table information
/)
!ame(_"PP$ Pac+a,e()(-(=$(-.($ (-(4$ (-((/)
// Device definition2 for Slot 4E "0< P6X: S60<
Device (S45() // Slot 4$ 5uncQ( on bu2 P3P3
!ame(_&DR$(-(((3(((()
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S454) // Slot 4$ 5uncQ4 on bu2 P3P3
!ame(_&DR$(-(((3(((4)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S453) // Slot 4$ 5uncQ3 on bu2 P3P3
!ame(_&DR$(-(((3(( (3)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S45F) // Slot 4$ 5uncQF on bu2 P3P3
!ame(_&DR$(-(((3(((F)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S45.) // Slot 4$ 5uncQ. on bu2 P3P3
!ame(_&DR$(-(((3(((.)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S45G) // Slot 4$ 5uncQG on bu2 P3P3
!ame(_&DR$(-(((3(((G)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S45I) // Slot 4$ 5uncQI on bu2 P3P3
!ame(_&DR$(-(((3(((I)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S45T) // Slot 4$ 5uncQT on bu2 P3P3
!ame(_&DR$(-(((3(((T)
;ethod(_%Z($ 4) // Remove all power to device/
/
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// Device definition2 for Slot 3E "0< P6X: S60<
Device (S35() // Slot 3$ 5uncQ( on bu2 P3P3
!ame(_&DR$(-(((F(((()
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S354) // Slot 3$ 5uncQ4 on bu2 P3P3
!ame(_&DR$(-(((F(((4)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S353) // Slot 3$ 5uncQ3 on bu2 P3P3
!ame(_&DR$(-(((F(((3)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S35F) // Slot 3$ 5uncQF on bu2 P3P3
!ame(_&DR$(-(((F(((F)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S35.) // Slot 3$ 5uncQ. on bu2 P3P3
!ame(_&DR$(-(((F(((.)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S35G) // Slot 3$ 5uncQG on bu2 P3P3
!ame(_&DR$(-(((F(((G)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S35I) // Slot 3$ 5uncQI on bu2 P3P3
!ame(_&DR$(-(((F(((I)
;ethod(_%Z($ 4) // Remove all power to device/
/
Device (S35T) // Slot 3$ 5uncQT on bu2 P3P3
!ame(_&DR$(-(((F(((T)
;ethod(_%Z($ 4) // Remove all power to device/
/
/ // end P3P3
/ // end P)#(
/ // end Scope (\_SB)
2!'M will configure a 'C% device on a card hot&plugged into slot 4 or slot 2, with a cache line siHe of 32
=Notice this field is in -W23-s>, latenc( timer of +", ena0le !.33, 0ut leave '.33 alone.
7.2.7 _HPX (Hot Plug Parameter Extensions)
This optional o0#ect provides settings that appl( to all child 0uses until another such o0#ect is encountered.
These settings are used when configuring a device inserted into a hot&plug slot or for performing
configuration of devices not configured 0( the ;%2! at s(stem 0oot. The o0#ect is placed under a 0us where
this 0ehavior is desired, such as a 0us with hot&plug slots. %t returns a package that contains one or more
setting records. .ach setting record contains a setting t(pe =%NT.$.3>, a revision num0er =%NT.$.3> and
t(peFrevision specific contents.
The C@'A method is e/tensi0le. The setting t(pe and revision num0er determine the format of the setting
record. %f 2!'M does not understand the setting t(pe of a setting record, it shall ignore the setting record. A
setting record with higher revision num0er supersedes that with lower revision num0er, however, the C@'A
method can return 0oth together, 2!'M shall use the one with highest revision num0er that it understands.
Arguments<
None
3esult Code<
A package of one or more 'C%=&A> !ettings packages defined 0elow.
The C@'A method supersedes the C@'' method.
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PCI Setting Record (Type 0)
The 'C% setting record contains the setting t(pe , the current revision 4 and the t(peFrevision specific
content< cache&line siHe, latenc( timer, !.33 ena0le, and '.33 ena0le values.
Ta!le --- PCI Setting "ecord Content
6ield 6or%at 5efinition
Cache&line siHe %NT.$.3 Cache&line siHe reported in num0er of -W23-s.
1atenc( timer %NT.$.3 1atenc( timer value reported in num0er of 'C% clock c(cles.
.na0le !.33 %NT.$.3 When set to 4, indicates that action must 0e performed to ena0le !.33 in
the command register.
.na0le '.33 %NT.$.3 When set to 4, indicates that action must 0e performed to ena0le '.33 in
the command register.
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7.2.7.2
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7.2.7.2
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PCI-X Setting Record (Type 1)
The 'C%&A setting record contains the setting t(pe 4, the current revision 4 and the t(peFrevision specific
content< the ma/imum memor( read 0(te count setting, the average ma/imum outstanding split
transactions setting and the total ma/imum outstanding split transactions to 0e used when configuring 'C%&
A command registers for 'C%&A 0uses andFor devices.
Ta!le --. PCI-= Setting "ecord Content
6ield 6or%at 5efinition
Ma/imum memor( read
0(te count
%NT.$.3 ma/imum memor( read 0(te count reported<
Dalue < Ma/imum 0(te count *42,
Dalue 4< Ma/imum 0(te count 42",
Dalue 2< Ma/imum 0(te count 2"8,
Dalue 3< Ma/imum 0(te count "6+
Average ma/imum
outstanding split
transactions
%NT.$.3 The following values are defined,
Dalue < Ma/imum outstanding split transaction 4,
Dalue 4< Ma/imum outstanding split transaction 2,
Dalue 2< Ma/imum outstanding split transaction 3,
Dalue 3< Ma/imum outstanding split transaction ",
Dalue "< Ma/imum outstanding split transaction 8,
Dalue *< Ma/imum outstanding split transaction 42,
Dalue +< Ma/imum outstanding split transaction 4+,
Dalue 9< Ma/imum outstanding split transaction 32,
Total ma/imum outstanding
split transactions
%NT.$.3 !ee the definition for the average ma/imum outstanding split
transactions.
5or simplicit(, 2!'M could use the Average Ma/imum 2utstanding !plit Transactions value as the
Ma/imum 2utstanding !plit Transactions register value in the 'C%&A command register for each 'C%&A
device. Another alternative is to use a more sophisticated polic( and the Total Ma/imum 2utstanding !plit
Transactions Dalue to gain even more performance. %n this case, the 2! would e/amined each 'C%&A
device that is directl( attached to the host 0ridge, determine the num0er of outstanding split transactions
supported 0( each device, and configure each device accordingl(. The goal is to ensure that the aggregate
num0er of concurrent outstanding split transactions does not e/ceed the Total Ma/imum 2utstanding !plit
Transactions Dalue< an integer denoting the num0er of concurrent outstanding split transactions the host
0ridge can support =the minimum value is 4>.
This does not address providing additional information that would 0e used to configure registers in 0ridge
devices, 0e the( standard registers or device specific registers. %t is 0elieved that a driver for a 0ridge would
0e the 0est wa( to address 0oth of those issues. @owever, such a 0ridge driver should have access to the
C@'A method information to use in optimiHing its decisions on how to configure the 0ridge. Configuration
of a 0ridge is dependent on 0oth s(stem specific information such as these provided 0( the C@'A method,
as well as 0ridge specific information.
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7.2.7.3
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PCI Express Setting Record (Type 2)
The 'C% ./press setting record contains the setting t(pe 2, the current revision 4 and the t(peFrevision
specific content< ,ncorrecta0le .rror Mask 3egister setting, ,ncorrecta0le .rror !everit( 3egister setting
and the Correcta0le .rror Mask 3egister setting to 0e used when configuring 'C% ./press registers in the
Advanced .rror 3eporting ./tended Capa0ilit( !tructure for the 'C% ./press devices. 2!'M will onl(
evaluate C@'A with !etting 3ecord I T(pe 2 if 2!'M is not controlling the 'C% ./press Advanced .rror
3eporting capa0ilit(.
Ta!le --/ PCI 1xpress Setting "ecord Content
6ield 6or%at 5efinition
,ncorrecta0le
error mask
register setting
%NT.$.3 ;it to 34 contains the setting that the 2!'M uses to set the ,ncorrecta0le
.rror Mask 3egister in the Advanced .rror 3eporting ./tended Capa0ilit(
!tructure for the 'C% ./press devices.
,ncorrecta0le
error severit(
register setting
%NT.$.3 ;it to 34 contains the setting that the 2!'M uses to set the ,ncorrecta0le
.rror !everit( 3egister in the Advanced .rror 3eporting ./tended
Capa0ilit( !tructure for the 'C% ./press devices.
Correcta0le error
mask register
setting
%NT.$.3 ;it to 34 contains the setting that the 2!'M uses to set the Correcta0le
.rror Mask 3egister in the Advanced .rror 3eporting ./tended Capa0ilit(
!tructure for the 'C% ./press devices.
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7.2.7.4
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_HPX Example
;ethod (_"PR$ ()
Return (Pac+a,e(3)
Pac+a,e(I) // P)# Settin, Record
(-(($ // <1pe (
(-(4$ // Revi2ion 4
(-(=$ // )ache6ineSiCe in DW0RDS
(-.($ // 6atenc1<imer in P)# cloc+2
(-(4$ // %nable S%RR (Boolean)
(-(( // %nable P%RR (Boolean)
/$
Pac+a,e(G) // P)#ER Settin, Record
(-(4$ // <1pe 4
(-(4$ // Revi2ion 4
(-(F$ // ;a-imum ;emor1 Read B1te )ount
(-(.$ // &vera,e ;a-imum 0ut2tandin, Split <ran2action2
(-(T // <otal ;a-imum 0ut2tandin, Split <ran2action2
/
/)
/
7.2.8 _MAT (Multiple APIC Table Entry)
This optional o0#ect evaluates to a 0uffer returning data in the format of a series of Multiple A'%C
-escription Ta0le =MA-T> A'%C !tructure entries. This o0#ect can appear under an %F2 A'%C or processor
o0#ect definition as processors ma( contain 1ocal A'%Cs. !pecific t(pes of MA-T entries are meaningful
to =in other words, is processed 0(> 2!'M when returned via the evaluation of this o0#ect as descri0ed
0elow. 2ther entr( t(pes returned 0( the evaluation of CMAT are ignored 0( 2!'M.
When CMAT appears under a 'rocessor o0#ect, 2!'M processes 1ocal A'%C =section *.2.44.*, J'rocessor
1ocal A'%CL>, 1ocal !A'%C =section *.2.44.43, J1ocal !A'%C !tructureL>, and local A'%C NM% =section
*.2.44.4, J1ocal A'%C NM%L> entries returned from the o0#ectMs evaluation. 2ther entr( t(pes are ignored
0( 2!'M. 2!'M uses the AC'% processor %- in the entries returned from the o0#ectMs evaluation to
identif( the entries corresponding to either the AC'% processor %- of the 'rocessor o0#ect or the value
returned 0( the C,%- o0#ect under a 'rocessor device.
When CMAT appears under an %F2 A'%C, 2!'M processes %F2 A'%C =section *.2.44.+, J%F2 A'%CL>, %F2
!A'%C =section *.2.44.42, J%F2 !A'%C !tructureL>, non&maska0le interrupt sources =section *.2.44.6, JNon&
Maska0le %nterrupt !ources =NM%s>L>, interrupt source overrides =section *.2.44.8, J%nterrupt !ource
2verridesL>, and platform interrupt source structure =section *.2.44.4", J'latform %nterrupt !ource
!tructureL> entries returned from the o0#ectMs evaluation. 2ther entr( t(pes are ignored 0( 2!'M.
Arguments<
None
3esult Code<
A 0uffer
./ample A!1 for CMAT usage<
Scope(\_SB)
Device(P)#() // Root P)# Bu2
!ame(_"#D$ %#S&#D(PP!P(&(FP)) // !eed _"#D for root device
!ame(_&DR$() // Device ( on thi2 bu2
;ethod (_)RS$() // !eed current re2ource2 for root device
// Return current re2ource2 for root brid,e (
/
!ame(_PR<$ Pac+a,e() // !eed P)# #RJ routin, for P)# brid,e
// Pac+a,e with P)# #RJ routin, table information
/)
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Device (PI.&) // PI.& &)P#
!ame(_&DR$()
0perationRe,ion(<&BD$ S12tem;emor1$ //Ph12ical addre22 of fir2t
// data b1te of multiple &)P# table$ 6en,th of table2)
5ield (<&BD$ B1te&cc$ !o6oc+$ Pre2erve)
;&<D$ 6en,th of table2 x =
/
;ethod(_;&<$ ()
Return (;&<D)
/
/ // end PI.&
/ // end P)#(
/ // end 2cope SB
7.2.9 _OSC (Operating System Capabilities)
This optional o0#ect is a control method that is used 0( 2!'M to communicate to the platform the feature
support or capa0ilities provided 0( a deviceMs driver. This o0#ect is a child o0#ect of a device and ma( also
e/ist in the BC!; scope, where it can 0e used to conve( platform wide 2!'M capa0ilities. When supported,
C2!C is invoked 0( 2!'M immediatel( after placing the device in the - power state. -evice specific
o0#ects are evaluated after C2!C invocation. This allows the values returned from other o0#ects to 0e
predicated on the 2!'M feature support F capa0ilit( information conve(ed 0( C2!C. 2!'M ma( evaluate
C2!C multiple times to indicate changes in 2!'M capa0ilit( to the device 0ut this ma( 0e precluded 0(
specific device re:uirements. As such, C2!C usage descriptions in section 6, JAC'%&!pecific -evice
20#ectsL, or other governing specifications descri0e superseding device specific C2!C capa0ilities and F or
preclusions.
C2!C ena0les the platform to configure its AC'% namespace representation and o0#ect evaluations to match
the capa0ilities of 2!'M. This ena0les legac( operating s(stem support for platforms with new features
that make use of new namespace o0#ects that if e/posed would not 0e evaluated when running a legac( 2!.
C2!C provides the capa0ilit( to transition the platform to native operating s(stem support of new features
and capa0ilities when availa0le through d(namic namespace reconfiguration. C2!C also allows devices
with Compati0le %-s to provide superset functionalit( when controlled 0( their native =5or e/ample, C@%-
matched> driver as appropriate o0#ects can 0e e/posed accordingl( as a result of 2!'MMs evaluation of
C2!C.
Argu%entsH
Arg =;uffer>< ,,%-
Arg4 =%nteger>< 3evision %-
Arg2 =%nteger>< Count
Arg3 =;uffer>< Capa0ilities ;uffer,
,,%- I ,niversal ,ni:ue %dentifier =4+ ;(te ;uffer> used 0( the platform in con#unction with 3evision %-
to ascertain the format of the Capa0ilities 0uffer.
3evision %- I The revision of the Capa0ilities ;uffer format. The revision level is specific to the ,,%-.
Count & Num0er of -W23-s in the Capa0ilities ;uffer in Arg3
Capa0ilities ;uffer I ;uffer containing the num0er of -W23-s indicated 0( Count. The first -W23- of
this 0uffer contains standard 0it definitions as descri0ed 0elow. !u0se:uent -W23-s contain ,,%-&
specific 0its that conve( to the platform the capa0ilities and features supported 0( 2!'M. !uccessive
revisions of the Capa0ilities ;uffer must 0e 0ackwards compati0le with earlier revisions. ;it ordering
cannot 0e changed.
Capa0ilities ;uffers are device&specific and as such are descri0ed under specific device definitions. !ee
section 6, JAC'% -evices and -evice !pecific 20#ectsL for an( C2!C definitions for AC'% devices. The
format of the Capa0ilities ;uffer and 0ehavior rules ma( also 0e specified 0( 2.Ms and %@Ds for custom
devices and other interface or device governing 0odies for e/ample, the 'C% !%$.
The first -W23- in the capa0ilities 0uffer is used to return errors defined 0( C2!C. This -W23- must
alwa(s 0e present and ma( not 0e redefinedFreused 0( uni:ue interfaces utiliHing C2!C.
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;it & Guer( !upport 5lag. the C2!C invocation is a :uer( 0( 2!'M to determine which
capa0ilities 2!'M ma( take control of. %n this case, C2!C sets 0its for those capa0ilities of which
2!'M ma( take control and clears 0its for those capa0ilities of which 2!'M ma( not take
control. %f Hero, 2!'M is attempting to take control of the capa0ilities corresponding to the 0its
set.
;it 4& Alwa(s clear=>.
;it 2& Alwa(s clear=>.
;it 3& Alwa(s clear=>.
All others& reserved.
"esult CodeH
Capa0ilities ;uffer =;uffer> I The platform acknowledges the Capa0ilities ;uffer 0( returning a 0uffer of
-W23-s of the same length. !et 0its indicate acknowledgement and cleared 0its indicate that the
platform does not support the capa0ilit(.
The first -W23- in the capa0ilities 0uffer is used to return errors defined 0( C2!C. This -W23- must
alwa(s 0e present and ma( not 0e redefinedFreused 0( uni:ue interfaces utiliHing C2!C.
;it & 3eserved =not used>
;it 4& C2!C failure. 'latform 5irmware was una0le to process the re:uest or :uer(. Capa0ilities
0its ma( have 0een masked.
;it 2& ,nrecogniHed ,,%-. This 0it is set to indicate that the platform firmware does not
recogniHe the ,,%- passed in via Arg. Capa0ilities 0its are preserved.
;it 3& ,nrecogniHed 3evision. This 0it is set to indicate that the platform firmware does not
recogniHe the 3evision %- passed in via Arg4. Capa0ilities 0its 0e(ond those comprehended 0( the
firmware will 0e masked.
;it "& Capa0ilities Masked. This 0it is set to indicate that capa0ilities 0its set 0( driver software
have 0een cleared 0( platform firmware.
All others& reserved.
At this time, platform&wide Capa0ilities ;uffer -W23- 0it definitions are not defined. As such, 2!'M
implementations are not e/pected to evaluate BC!;.C2!C until a future revision of the AC'% specification
specifies platform&wide Capa0ilities ;uffer -W23- 0it definitions.
Note< 2!'M must not use the results of C2!C evaluation to choose a compati0le device driver. 2!'M
must use C@%-, CC%-, or native enumera0le 0us device identification mechanisms to select an appropriate
driver for a device.
The platform ma( issue a 0otif)=device, /8> to inform 2!'M to re&evaluate C2!C when the availa0ilit(
of feature control changes. 'latforms must not rel(, however, on 2!'M to evaluate C2!C after issuing a
0otif) for proper operation as 2!'M cannot guarantee the presence of a target entit( to receive and
process the 0otif) for the device. 5or e/ample, a device driver for the device ma( not 0e loaded at the time
the 0otif) is signaled. 5urther, the issuance and processing rules for notification of changes in the
Capa0ilities ;uffer is device specific. As such, the allowa0le 0ehavior is governed 0( device specifications
either in section 6, J AC'%&!pecific -evice 20#ectsL, for AC'%&define devices, or other 2.M, %@D, or
device governing 0od(MsM device specifications.
%t is permitted for C2!C to return all 0its in the Capa0ilities ;uffer cleared. An e/ample of this is when
significant time is re:uired to disa0le platform&0ased feature support. The platform ma( then later issue a
Notif( to tell 2!'M to re&evaluate C2!C to take over native control. This 0ehavior is also device specific
0ut ma( also rel( on specific 2! capa0ilit(.
%n general, platforms should support 0oth 2!'M taking and relin:uishing control of specific feature
support via multiple invocations of C2!C 0ut the re:uired 0ehavior ma( var( on a per device 0asis.
!ince platform conte/t is lost when the platform enters the !" sleeping state, 2!'M must re&evaluate C2!C
upon wake from !" to restore the previous platform state. This re:uirement will var( depending on the
device specific C2!C functionalit(.
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7.2.9.1
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_OSC Implementation Example for PCI Host Bridge Devices
The following section is an e/cerpt from the 'C% 5irmware !pecification 3evision 3. and is reproduced
with the permission of the 'C% !%$. 0oteH The PCI SI; owns the definition of D3SC !ehavior and
para%eter !it definitions for PCI devices In the event of a discrepanc) !etween the following
exa%ple and the PCI 6ir%ware Specification' the latter has precedence
The C2!C interface defined in this section applies onl( to J@ost ;ridgeL AC'% devices that originate 'C%,
'C%&A or 'C% ./press hierarchies. These AC'% devices must have a C@%- of =or CC%- including> either
.%!A%-=J'N'A3L> or .%!A%-=J'N'A8L>. 5or a host 0ridge device that originates a 'C% ./press
hierarch(, the C2!C interface defined in this section is re:uired. 5or a host 0ridge device that originates a
'C%F'C%&A 0us hierarch(, inclusion of an C2!C o0#ect is optional.
The C2!C interface for a 'C%F'C%&AF'C% ./press hierarch( is identified 0( the ,niversal ,niform
%dentifier =,,%-> ##d!(dA!-+ff.-($+c-,-A.-.((+c$#dd.--. A revision %- of 4 encompasses fields
defined in this section of this revision of this specification, comprised of 3 -W23-s, including the first
-W23- descri0ed 0( the generic AC'% definition of C2!C.
The first -W23- in the C2!C Capa0ilities ;uffer contain 0its are generic to C2!C and include status and
error information.
The second -W23- in the C2!C capa0ilities 0uffer is the !upport 5ield. ;its defined in the !upport 5ield
provide information regarding 2! supported features. Contents in the !upport 5ield are passed one&wa(K
the 2! will disregard an( changes to this field when returned. !ee Ta0le +&8 for descriptions of capa0ilities
0its in this field passed as a parameter into the C2!C control method.
The third -W23- in the C2!C Capa0ilities ;uffer is the Control 5ield. ;its defined in the Control 5ield
are used to su0mit re:uest 0( the 2! for controlFhandling of the associated feature, t(picall( =0ut not
e/cluded to> those features that utiliHe native interrupts or events handled 0( an 2!&level driver. !ee Ta0le
+&4 for descriptions of capa0ilities 0its in this field passed as a parameter into the C2!C control
method. %f an( 0its in the Control 5ield are returned cleared =masked to Hero> 0( the C2!C control method,
the respective feature is designated unsupported 0( the platform and must not 0e ena0led 0( the 2!. !ome
of these features ma( 0e controlled 0( platform firmware prior to 2! 0oot or during runtime for a legac(
2!, while others ma( 0e disa0ledFinoperative until native 2! support is availa0le. !ee Ta0le +&44 for
descriptions of capa0ilities 0its in this returned field.
%f the C2!C control method is a0sent from the scope of a host 0ridge device, then the 2! must not ena0le
or attempt to use an( features defined in this section for the hierarch( originated 0( the host 0ridge. -oing
so could contend with platform firmware operations, or produce undesired results. %t is recommended that a
machine with multiple host 0ridge devices should report the same capa0ilities for all host 0ridges, and also
negotiate control of the features descri0ed in the Control 5ield in the same wa( for all host 0ridges.
Ta!le --, Interpretation of D3SC Support 6ield
Support 6ield
!it offset
Interpretation
./tended 'C% Config operation regions supported
The 2! sets this 0it to 4 if it supports A!1 accesses through 'C% Config operation
regions to e/tended configuration space =offsets greater than /55>. 2therwise, the
2! sets this 0it to .
4 Active !tate 'ower Management supported
The 2! sets this 0it to 4 if it nativel( supports configuration of Active !tate 'ower
Management registers in 'C% ./press devices. 2therwise, the 2! sets this 0it to .
2 Clock 'ower Management Capa0ilit( supported
The 2! sets this 0it to 4 if it supports the Clock 'ower Management Capa0ilit(, and
will ena0le this feature during a native hot plug insertion event if supported 0( the
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
26+ Advanced Configuration and 'ower %nterface !pecification
newl( added device. 2therwise, the 2! sets this 0it to .
;ote# T1e Cloc3 Power (anagement Capability is defined in an errata to t1e PCI
*xpress )ase Specification. 1!5!
3 'C% !egment $roups supported
The 2! sets this 0it to 4 if it supports 'C% !egment $roups as defined 0( the C!.$
o0#ect, and access to the configuration space of devices in 'C% !egment $roups as
descri0ed 0( this specification. 2therwise, the 2! sets this 0it to .
" M!% supported
The 2! sets this 0it to 4 if it supports configuration of devices to generate message&
signaled interrupts, either through the M!% Capa0ilit( or the M!%&A Capa0ilit(.
2therwise, the 2! sets this 0it to .
*&34 3eserved
Ta!le --+$ Interpretation of D3SC Control 6ield' Passed in via Arg#
Control 6ield
!it offset
Interpretation
PCI Express Native Hot Plug control
The 2! sets this 0it to 4 to re:uest control over 'C% ./press native hot plug. %f the
2! successfull( receives control of this feature, it must track and update the status of
hot plug slots and handle hot plug events as descri0ed in the 'C% ./press ;ase
!pecification.
4 SHPC Native Hot Plug control
The 2! sets this 0it to 4 to re:uest control over 'C%F'C%&A !tandard @ot&'lug
Controller =!@'C> hot plug. %f the 2! successfull( receives control of this feature, it
must track and update the status of hot plug slots and handle hot plug events as
descri0ed in the !@'C !pecification.
2 PCI Express Native Power Management Events control
The 2! sets this 0it to 4 to re:uest control over 'C% ./press native power
management event interrupts ='M.s>. %f the 2! successfull( receives control of this
feature, it must handle power management events as descri0ed in the 'C% ./press
;ase !pecification.
3 PCI Express Advanced Error Reporting control
The 2! sets this 0it to 4 to re:uest control over 'C% ./press Advanced .rror
3eporting. %f the 2! successfull( receives control of this feature, it must handle error
reporting through the Advanced .rror 3eporting Capa0ilit( as descri0ed in the 'C%
./press ;ase !pecification.
" PCI Express Capability Structure control
The 2! sets this 0it to 4 to re:uest control over the 'C% ./press Capa0ilit( !tructures
=standard and e/tended> defined in the 'C% ./press ;ase !pecification version 4.4.
These capa0ilit( structures are the 'C% ./press Capa0ilit(, the virtual channel
e/tended capa0ilit(, the power 0udgeting e/tended capa0ilit(, the advanced error
reporting e/tended capa0ilit(, and the serial num0er e/tended capa0ilit(. %f the 2!
successfull( receives control of this feature, it is responsi0le for configuring the
registers in all 'C% ./press Capa0ilities in a manner that complies with the 'C%
./press ;ase !pecification. Additionall(, the 2! is responsi0le for saving and
restoring all 'C% ./press Capa0ilit( register settings across power transitions when
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register conte/t ma( have 0een lost.
*&34 3eserved
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268 Advanced Configuration and 'ower %nterface !pecification
Ta!le --++ Interpretation of D3SC Control 6ield' "eturned 7alue
Control 6ield
!it offset
Interpretation
PCI Express Native Hot Plug control
The firmware sets this 0it to 4 to grant control over 'C% ./press native hot plug
interrupts. %f firmware allows the 2! control of this feature, then in the conte/t of the
C2!C method it must ensure that all hot plug events are routed to device interrupts as
descri0ed in the 'C% ./press ;ase !pecification. Additionall(, after control is
transferred to the 2!, firmware must not update the state of hot plug slots, including
the state of the indicators and power controller. %f control of this feature was
re:uested and denied or was not re:uested, firmware returns this 0it set to .
4 SHPC Native Hot Plug control
The firmware sets this 0it to 4 to grant control over control over 'C%F'C%&A !tandard
@ot&'lug Controller =!@'C>hot plug. %f firmware allows the 2! control of this
feature, then in the conte/t of the C2!C method it must ensure that all hot plug events
are routed to device interrupts as descri0ed in the !@'C !pecification. Additionall(,
after control is transferred to the 2!, firmware must not update the state of hot plug
slots, including the state of the indicators and power controller. %f control of this
feature was re:uested and denied or was not re:uested, firmware returns this 0it set to
.
2 PCI Express Native Power Management Events control
The firmware sets this 0it to 4 to grant control over control over 'C% ./press native
power management event interrupts ='M.s>. %f firmware allows the 2! control of
this feature, then in the conte/t of the C2!C method it must ensure that all 'M.s are
routed to root port interrupts as descri0ed in the 'C% ./press ;ase !pecification.
Additionall(, after control is transferred to the 2!, firmware must not update the
'M. !tatus field in the 3oot !tatus register or the 'M. %nterrupt .na0le field in the
3oot Control register. %f control of this feature was re:uested and denied or was not
re:uested, firmware returns this 0it set to .
3 PCI Express Advanced Error Reporting control
The firmware sets this 0it to 4 to grant control over 'C% ./press Advanced .rror
3eporting. %f firmware allows the 2! control of this feature, then in the conte/t of the
C2!C method it must ensure that error messages are routed to device interrupts as
descri0ed in the 'C% ./press ;ase !pecification. Additionall(, after control is
transferred to the 2!, firmware must not modif( the Advanced .rror 3eporting
Capa0ilit(. %f control of this feature was re:uested and denied or was not re:uested,
firmware returns this 0it set to .
" PCI Express Capability Structure control
The firmware sets this 0it to 4 to grant control over te PCI Express
Capability! I" te #rmware does not grant control o" tis "eature$
#rmware must andle con#guration o" te PCI Express Capability
Structure!
%f firmware grants the 2! control of this feature, an( firmware configuration of the
'C% ./press Capa0ilit( ma( 0e overwritten 0( an 2! configuration, depending on
2! polic(.
*&34 3eserved
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7.2.9.1.1 Rules for Evaluating _OSC
This section defines when and how the 2! must evaluate C2!C, as well as restrictions on firmware
implementation.
7.2.9.1.1.1 Query Flag
%f the Guer( !upport 5lag =Capa0ilities -W23- 4, 0it > is set 0( the 2! when evaluating C2!C, no
hardware settings are permitted to 0e changed 0( firmware in the conte/t of the C2!C call. %t is strongl(
recommended that the 2! evaluate C2!C with the Guer( !upport 5lag set until C2!C returns the
Capa0ilities Masked 0it clear, to negotiate the set of features to 0e granted to the 2! for native supportK a
platform ma( re:uire a specific com0ination of features to 0e supported nativel( 0( an 2! 0efore granting
native control of a given feature.
7.2.9.1.1.2 Evaluation Conditions
The 2! must evaluate C2!C under the following conditions<
-uring initialiHation of an( driver that provides native support for features descri0ed in the section a0ove.
These features ma( 0e supported 0( one or man( drivers, 0ut should onl( 0e evaluated 0( the main 0us
driver for that hierarch(. !econdar( drivers must coordinate with the 0us driver to install support for these
features. -rivers ma( not relin:uish control of features previousl( o0tained. %.e. 0its set in Capa0ilities
-W23-3 after the negotiation process must 0e set on all su0se:uent negotiation attempts.
When a Notif(=Tdevice), 8> is delivered to the 'C% @ost ;ridge device.
,pon resume from !". 'latform firmware will handle conte/t restoration when resuming from !4&!3.
7.2.9.1.1.3 Sequence of _OSC calls
The following rules govern se:uences of calls to C2!C that are issued to the same host 0ridge and occur
within the same 0oot.
The 2! is permitted to evaluate C2!C an ar0itrar( num0er of times.
%f the 2! declares support of a feature in the !tatus 5ield in one call to C2!C, then it must
preserve the set state of that 0it =declaring support for that feature> in all su0se:uent calls.
%f the 2! is granted control of a feature in the Control 5ield in one call to C2!C, then it must
preserve the set state of that 0it =re:uesting that feature> in all su0se:uent calls.
5irmware ma( not re#ect control of an( feature it has previousl( granted control to.
There is no mechanism for the 2! to relin:uish control of a feature previousl( re:uested and
granted..
7.2.9.1.2 ASL Example
A sample C2!C implementation for a mo0ile s(stem incorporating a 'C% ./press hierarch( is shown
0elow<
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3 Advanced Configuration and 'ower %nterface !pecification
Device(P)#() // Root P)# bu2

!ame(_"#D$%#S&#D(PP!P(&(=P)) // P)# %-pre22 Root Brid,e


!ame(_)#D$%#S&#D(PP!P(&(FP)) // )ompatible P)# Root Brid,e
!ame(SXPP$() // P)# _0S) Support 5ield value
!ame()<R6$() // P)# _0S) )ontrol 5ield value
;ethod(_0S)$.)
// )hec+ for proper XX#D
#f(6%8ual(&r,($<oXX#D(PFFDB.DGBE455TE.(4)EHIGTET..4)(FDDTIIP)))

// )reate DWordEadre22able field2 from the )apabilitie2 Buffer


)reateDWord5ield(&r,F$($)DW4)
)reateDWord5ield(&r,F$.$)DW3)
)reateDWord5ield(&r,F$=$)DWF)
// Save )apabilitie2 DWord3 V F
Store()DW3$SXPP)
Store()DWF$)<R6)
// 0nl1 allow native hot plu, control if 0S 2upport2>
// [ &SP;
// [ )loc+ P;
// [ ;S#/;S#ER
#f(6!ot%8ual(&nd(SXPP$ (-4I)$ (-4I))

&nd()<R6$(-4%) // ;a2+ bit ( (and undefined bit2)


/
// &lwa12 allow native P;%$ &%R (no dependencie2)
// !ever allow S"P) (no S"P) controller in thi2 212tem)
&nd()<R6$(-4D$)<R6)
#f(!ot(&nd()DW4$4))) // Juer1 fla, clearO
// Di2able :P%2 for feature2 ,ranted native control.
#f(&nd()<R6$(-(4)) // "ot plu, control ,rantedO

Store(($"P)%) // clear the hot plu, S)# enable bit


Store(4$"P)S) // clear the hot plu, S)# 2tatu2 bit
/
#f(&nd()<R6$(-(.)) // P;% control ,rantedO

Store(($P;)%) // clear the P;% S)# enable bit


Store(4$P;)S) // clear the P;% S)# 2tatu2 bit
/
#f(&nd()<R6$(-4()) // 0S re2torin, P)#e cap 2tructureO
// Set 2tatu2 to not re2tore P)#e cap 2tructure
// upon re2ume from SF
Store(4$SF)R)
/
/
#f(6!ot%8ual(&r,4$0ne))
// Xn+nown revi2ion
0r()DW4$(-(=$)DW4)
/
#f(6!ot%8ual()DWF$)<R6))
// )apabilitie2 bit2 were ma2+ed
0r()DW4$(-4($)DW4)
/
// Xpdate DW0RDF in the buffer
Store()<R6$)DWF)
Return(&r,F)
/ %l2e
0r()DW4$.$)DW4) // Xnreco,niCed XX#D
Return(&r,F)
/
/ // %nd _0S)
/ // %nd P)#(
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7.2.10 _PRS (Possible Resource Settings)
This optional o0#ect evaluates to a 0(te stream that descri0es the possible resource settings for the device.
When descri0ing a platform, specif( a C'3! for all the configura0le devices. !tatic =non&configura0le>
devices do not specif( a C'3! o0#ect. The information in this package is used 0( 2!'M to select a conflict&
free resource allocation without user intervention. This method must not reference an( operation regions
that have not 0een declared availa0le 0( a C3.$ method.
The format of the data in a C'3! o0#ect follows the same format as the CC3! o0#ect =for more information,
see the CC3! o0#ect definition in section +.2.4, JCC3! =Current 3esource !ettings>L>.
%f the device is disa0led when C'3! is called, it must remain disa0led.
Arguments<
None
3esult Code<
;(te stream
7.2.11 _PRT (PCI Routing Table)
'C% interrupts are inherentl( non&hierarchical. 'C% interrupt pins are wired to interrupt inputs of the
interrupt controllers. The C'3T o0#ect provides a mapping from 'C% interrupt pins to the interrupt inputs of
the interrupt controllers. The C'3T o0#ect is re:uired under all 'C% root 0ridges. C'3T evaluates to a
package that contains a list of packages, each of which descri0es the mapping of a 'C% interrupt pin.
0ote< The 'C% function num0er in the Address field of the C'3T packages must 0e /5555, indicating
Jan(L function num0er or Jall functionsL.
The C'3T mapping packages have the fields listed in Ta0le +&42.
Ta!le --+& Mapping 6ields
6ield T)pe 5escription
Address -W23- The address of the device =uses the same format as CA-3>.
'in ;ST. The 'C% pin num0er of the device =I%NTA, 4I%NT;, 2I%NTC, 3I%NT->.
!ource Name'ath
2r
;ST.
Name of the device that allocates the interrupt to which the a0ove pin is
connected. The name can 0e a full( :ualified path, a relative path, or a simple
name segment that utiliHes the namespace search rules. 0ote< This field is a
Name'ath and not a !tring literal, meaning that it should not 0e surrounded 0(
:uotes. %f this field is the integer constant ?ero =or a ;ST. value of >, then the
interrupt is allocated from the glo0al interrupt pool.
!ource
%nde/
-W23- %nde/ that indicates which resource descriptor in the resource template of the
device pointed to in the !ource field this interrupt is allocated from. %f the
Source field is the ;ST. value Hero, then this field is the glo0al s(stem interrupt
num0er to which the pin is connected.
There are two wa(s that C'3T can 0e used. T(picall(, the interrupt input that a given 'C% interrupt is on is
configura0le. 5or e/ample, a given 'C% interrupt might 0e configured for either %3G 4 or 44 on an 82*6
interrupt controller. %n this model, each interrupt is represented in the AC'% namespace as a 'C% %nterrupt
1ink -evice.
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32 Advanced Configuration and 'ower %nterface !pecification
These o0#ects have C'3!, CC3!, C!3!, and C-%! control methods to allocate the interrupt. Then, 2!'M
handles the interrupts not as interrupt inputs on the interrupt controller, 0ut as 'C% interrupt pins. The driver
looks up the deviceMs pins in the C'3T to determine which device o0#ects allocate the interrupts. To move
the 'C% interrupt to a different interrupt input on the interrupt controller, 2!'M uses C'3!, CC3!, C!3!,
and C-%! control methods for the 'C% %nterrupt 1ink -evice.
%n the second model, the 'C% interrupts are hardwired to specific interrupt inputs on the interrupt controller
and are not configura0le. %n this case, the !ource field in C'3T does not reference a device, 0ut instead
contains the value Hero, and the !ource %nde/ field contains the glo0al s(stem interrupt to which the 'C%
interrupt is hardwired.
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7.2.11.1
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3" Advanced Configuration and 'ower %nterface !pecification
Example: Using _PRT to Describe PCI IRQ Routing
The following e/ample descri0es two 'C% slots and a 'C% video chip. Notice that the interrupts on the two
'C% slots are wired differentl( =0ar0er&poled>.
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Scope(\_SB)
Device(6!A&)
!ame(_"#D$ %#S&#D(PP!P()(5P)) // P)# interrupt lin+
!ame(_X#D$ 4)
!ame(_PRS$ Re2ource<emplate()
#nterrupt(Re2ourceProducer$Y) 4($44/ // #RJ2 4($44
/)
;ethod(_D#S) Y/
;ethod(_)RS) Y/
;ethod(_SRS$ 4) Y/
/
Device(6!AB)
!ame(_"#D$ %#S&#D(PP!P()(5P)) // P)# interrupt lin+
!ame(_X#D$ 3)
!ame(_PRS$ Re2ource<emplate()
#nterrupt(Re2ourceProducer$Y) 44$43/ // #RJ2 44$43
/)
;ethod(_D#S) Y/
;ethod(_)RS) Y/
;ethod(_SRS$ 4) Y/
/
Device(6!A))
!ame(_"#D$ %#S&#D(PP!P()(5P)) // P)# interrupt lin+
!ame(_X#D$ F)
!ame(_PRS$ Re2ource<emplate()
#nterrupt(Re2ourceProducer$Y) 43$4./ // #RJ2 43$4.
/)
;ethod(_D#S) Y/
;ethod(_)RS) Y/
;ethod(_SRS$ 4) Y/
/
Device(6!AD)
!ame(_"#D$ %#S&#D(PP!P()(5P)) // P)# interrupt lin+
!ame(_X#D$ .)
!ame(_PRS$ Re2ource<emplate()
#nterrupt(Re2ourceProducer$Y) 4($4G/ // #RJ2 4($4G
/)
;ethod(_D#S) Y/
;ethod(_)RS) Y/
;ethod(_SRS$ 4) Y/
/
Device(P)#()
Y
!ame(_PR<$ Pac+a,e
Pac+a,e(-(((.5555$ ($ \_SB_.6!A&$ (/$ // Slot 4$ #!<& // & full1
Pac+a,e(-(((.5555$ 4$ \_SB_.6!AB$ (/$ // Slot 4$ #!<B // 8ualified
Pac+a,e(-(((.5555$ 3$ \_SB_.6!A)$ (/$ // Slot 4$ #!<) // pathname
Pac+a,e(-(((.5555$ F$ \_SB_.6!AD$ (/$ // Slot 4$ #!<D // can be u2ed$
Pac+a,e(-(((G5555$ ($ 6!AB$ (/$ // Slot 3$ #!<& // or a 2imple
Pac+a,e(-(((G5555$ 4$ 6!A)$ (/$ // Slot 3$ #!<B // name 2e,ment
Pac+a,e(-(((G5555$ 3$ 6!AD$ (/$ // Slot 3$ #!<) // utiliCin, the
Pac+a,e(-(((G5555$ F$ 6!A&$ (/$ // Slot 3$ #!<D // 2earch rule2
Pac+a,e(-(((I5555$ ($ 6!A)$ (/ // @ideo$ #!<&
/)
/
/
7.2.12 _PXM (Proximity)
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3+ Advanced Configuration and 'ower %nterface !pecification
This optional o0#ect is used to descri0e pro/imit( domains within a machine. C'AM evaluates to an integer
that identifies the device as 0elonging to a specific pro/imit( domain. 2!'M assumes that two devices in
the same pro/imit( domain are tightl( coupled. 2!'M could choose to optimiHe its 0ehavior 0ased on this.
5or e/ample, in a s(stem with four processors and si/ memor( devices, there might 0e two separate
pro/imit( domains = and 4>, each with two processors and three memor( devices. %n this case, the 2! ma(
decide to run some software threads on the processors in pro/imit( domain and others on the processors
in pro/imit( domain 4. 5urthermore, for performance reasons, it could choose to allocate memor( for those
threads from the memor( devices inside the pro/imit( domain common to the processor and the memor(
device rather than from a memor( device outside of the processorMs pro/imit( domain. C'AM can 0e used
to identif( an( device 0elonging to a pro/imit( domain. Children of a device 0elong to the same pro/imit(
domain as their parent unless the( contain an overriding C'AM. 'ro/imit( domains do not impl( an(
e#ection relationships.
An 2! makes no assumptions a0out the pro/imit( or nearness of different pro/imit( domains. The
difference 0etween two integers representing separate pro/imit( domains does not impl( distance 0etween
the pro/imit( domains =in other words, pro/imit( domain 4 is not assumed to 0e closer to pro/imit(
domain than pro/imit( domain +>.
Arguments<
None
3esult Code<
An integer
7.2.13 _SLI (System Locality Information)
The !(stem 1ocalit( %nformation Ta0le =!1%T> ta0le defined in !ection *.2.4+, J!(stem 1ocalit( -istance
%nformation Ta0le =!1%T>L, provides relative distance information 0etween all !(stem 1ocalities for use
during 2! initialiHation.
The value of each .ntr(Vi,:W in the !1%T ta0le, where i represents a row of a matri/ and : represents a
column of a matri/, indicates the relative distances from !(stem 1ocalit( F 'ro/imit( -omain i to ever(
other !(stem 1ocalit( : in the s(stem =including itself>.
The i,: row and column values correlate to the value returned 0( the C'AM o0#ect in the AC'% namespace.
!ee section +.2.42, JC'AM ='ro/imit(>L for more information.
-(namic runtime reconfiguration of the s(stem ma( cause the distance 0etween !(stem 1ocalities to
change.
C!1% is an optional o0#ect that ena0les the platform to provide the 2! with updated relative !(stem
1ocalit( distance information at runtime. C!1% provide 2!'M with an update of the relative distance from
!(stem 1ocalit( i to all other !(stem 1ocalities in the s(stem.
Arguments<
None.
3eturn Code<
%f !(stem 1ocalit( i b N, where N is the num0er of !(stem 1ocalities, the C!1% method returns a 0uffer that
contains the relative distances V=i, >, =i, 4>, N, =i, i&4>, =i, i>, =, i>, =4, i>, N=i&4, i>, =i, i>WK if !(stem 1ocalit(
i T N, the C!1% method returns a 0uffer that contains the relative distances V=i, >, =i, 4>, N, =i, i>, N,=i, N&
4>, =, i>, =4, i>,N=i, i>, N, =N&4, i>W. Note< =i, i> is alwa(s a value of 4.
1xa%ple
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 39
The figure a0ove diagrams a "&node s(stem where the nodes are num0ered through 3 =Node n \ Node 3>
and the granularit( is at the node level for the N,MA distance information. %n this e/ample we assign
!(stem 1ocalities F 'ro/imit( -omain num0ers e:ual to the node num0ers =&3>. The N,MA relative
distances 0etween pro/imit( domains as implemented in this s(stem are descri0ed in the matri/ represented
in Ta0le +&43. 'ro/imit( -omains are represented 0( the num0ers in the top row and left column. -istances
are represented 0( the values in cells internal in the ta0le from the domains.
Ta!le --+# 1xa%ple "elative 5istances <etween Proxi%it) 5o%ains
Proxi%it)
5o%ain
$ + & #
$
4 4* 2 48
+
4* 4 4+ 2"
&
2 4+ 4 42
#
48 2" 42 4
An e/ample of these distances 0etween pro/imit( domains encoded in a !(stem 1ocalit( %nformation
Ta0le for consumption 0( 2!'M at 0oot time is descri0ed in Ta0le +&4".
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
38 Advanced Configuration and 'ower %nterface !pecification
Ta!le --+( 1xa%ple S)ste% Localit) Infor%ation Ta!le
6ield <)te
Length
<)te
3ffset
5escription
@eader
!ignature " O!1%TM.
1ength " " +
3evision 4 8 4
Checksum 4 6 .ntire ta0le must sum to Hero.
2.M%- + 4 2.M %-.
2.M Ta0le %- 8 4+ 5or the !(stem 1ocalit( %nformation Ta0le, the ta0le %-
is the manufacturer model %-.
2.M 3evision " 2" 2.M revision of !(stem 1ocalit( %nformation Ta0le for
supplied 2.M Ta0le %-.
Creator %- " 28 Dendor %- of utilit( that created the ta0le. 5or the -!-T,
3!-T, !!-T, and '!-T ta0les, this is the %- for the
A!1 Compiler.
Creator 3evision " 32 3evision of utilit( that created the ta0le. 5or the -!-T,
3!-T, !!-T, and '!-T ta0les, this is the revision for
the A!1 Compiler.
Num0er of !(stem
1ocalities
8 3+ "
.ntr(VWVW 4 "" 4
.ntr(VWV4W 4 "* 4*
.ntr(VWV2W 4 "+ 2
.ntr(VWV3W 4 "9 48
.ntr(V4WVW 4 "8 4*
.ntr(V4WV4W 4 "6 4
.ntr(V4WV2W 4 * 4+
.ntr(V4WV3W 4 *4 2"
.ntr(V2WVW 4 *2 2
.ntr(V2WV4W 4 *3 4+
.ntr(V2WV2W 4 *" 4
.ntr(V2WV3W 4 ** 42
.ntr(V3WVW 4 *+ 48
.ntr(V3WV4W 4 *9 2"
.ntr(V3WV2W 4 *8 42
.ntr(V3WV3W 4 *6 4
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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%f a new node, JNode "L, is added, then Ta0le +&4* represents the updated s(stemMs N,MA relative
distances of pro/imit( domains.
Ta!le --+A 1xa%ple "elative 5istances <etween Proxi%it) 5o%ains - A 0ode
Proxi%it)
5o%ain
$ + & # (
$
4 4* 2 48 49
+
4* 4 4+ 2" 24
&
2 4+ 4 42 4"
#
48 2" 42 4 23
(
49 24 4" 23 4
The new nodeMs C!1% o0#ect would evaluate to a 0uffer containing V49,24,4",23,4,49,24,4",23,4W.
Note< some s(stems support interleave memor( across the nodes. !1%T representation of these s(stems is
implementation specific.
7.2.14 _SRS (Set Resource Settings)
This optional control method takes one 0(te stream argument that specifies a new resource allocation for a
device. The resource descriptors in the 0(te stream argument must 0e specified in the same order as listed
in the CC3! 0(te stream =for more information, see the CC3! o0#ect definition>. A CC3! o0#ect can 0e
used as a template to ensure that the descriptors are in the correct format.
The settings must take effect 0efore the C!3! control method returns.
This method must not reference an( operation regions that have not 0een declared availa0le 0( a C3.$
method.
%f the device is disa0led, C!3! ena0les the device at the specified resources. C!3! is not used to disa0le a
deviceK use the C-%! control method instead.
Arguments<
;(te stream
3esult Code<
None
7.3 Device Insertion, Removal, and Status Objects
The o0#ects defined in this section provide mechanisms for handling d(namic insertion and removal of
devices and for determining device and notification processing status.
-evice insertion and removal o0#ects are also used for docking and undocking mo0ile platforms to and
from a peripheral e/pansion dock. These o0#ects give information a0out whether or not devices are present,
which devices are ph(sicall( in the same device =independent of which 0us the devices live on>, and
methods for controlling e#ection or interlock mechanisms.
The s(stem is more sta0le when remova0le devices have a software&controlled, DC3&st(le e#ection
mechanism instead of a Jsurprise&st(leL e#ection mechanism. %n this s(stem, the e#ect 0utton for a device
does not immediatel( remove the device, 0ut simpl( signals the operating s(stem. 2!'M then shuts down
the device, closes open files, unloads the driver, and sends a command to the hardware to e#ect the device.
%n AC'%, the se:uence of events for d(namicall( inserting a device follows the process 0elow. Notice that
this process supports hot, warm, and cold insertion of devices.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
34 Advanced Configuration and 'ower %nterface !pecification
4. %f the device is ph(sicall( inserted while the computer is in the working state =in other words, hot
insertion>, the hardware generates a general&purpose event.
2. The control method servicing the event uses the 0otif)=de2ice,> command to inform 2!'M of the 0us
that the new device is on or the device o0#ect for the new device. %f the Notif( command points to the
device o0#ect for the new device, the control method must have changed the deviceMs status returned 0(
C!TA to indicate that the device is now present. The performance of this process can 0e optimiHed 0(
having the o0#ect of the Notif( as close as possi0le, in the namespace hierarch(, to where the new
device resides. The Notif( command can also 0e used from the CWAE control method =for more
information a0out CWAE, see section 9.3.9 JBCWAE =!(stem Wake>L> to indicate device changes that
ma( have occurred while the computer was sleeping. 5or more information a0out the Notif( command,
see section *.+.3 J-evice 20#ect Notification.L.L
3. 2!'M uses the identification and configuration o0#ects to identif(, configure, and load a device driver
for the new device and an( devices found 0elow the device in the hierarch(.
". %f the device has a C1CE control method, 2!'M ma( later run this control method to lock the device.
The new device referred to in step 2 need not 0e a single device, 0ut could 0e a whole tree of devices. 5or
e/ample, it could point to the 'C%&'C% 0ridge docking connector. 2!'M will then load and configure all
devices it found 0elow that 0ridge. The control method can also point to several different devices in the
hierarch( if the new devices do not all live under the same 0us. =in other words, more than one 0us goes
through the connector>.
5or removing devices, AC'% supports 0oth hot removal =s(stem is in the ! state>, and warm removal
=s(stem is in a sleep state< !4&!">. This is done using the C.7x control methods. -evices that can 0e e#ected
include an C.7x control method for each sleeping state the device supports =a ma/imum of 2 C.7x o0#ects
can 0e listed>. 5or e/ample, hot removal devices would suppl( an C.7K warm removal devices would use
one of C.74&.7". These control methods are used to signal the hardware when an e#ect is to occur.
The se:uence of events for d(namicall( removing a device goes as follows<
4. The e#ect 0utton is pressed and generates a general&purpose event. =%f the s(stem was in a sleeping
state, it should wake the computer>.
2. The control method for the event uses the 0otif)=de2ice, 3> command to inform 2!'M which specific
device the user has re:uested to e#ect. Notif( does not need to 0e called for ever( device that ma( 0e
e#ected, 0ut for the top&level device. An( child devices in the hierarch( or an( e#ection&dependent
devices on this device =as descri0ed 0( C.7-, 0elow> are automaticall( removed.
3. The 2! shuts down and unloads devices that will 0e removed.
". %f the device has a C1CE control method, 2!'M runs this control method to unlock the device.
*. The 2! looks to see what C.7x control methods are present for the device. %f the removal event will
cause the s(stem to switch to 0atter( power =in other words, an undock> and the 0atter( is low, dead, or
not present, 2!'M uses the lowest supported sleep state C.7x listedK otherwise it uses the highest state
C.7x. @aving made this decision, 2!'M runs the appropriate C.7x control method to prepare the
hardware for e#ect.
+. Warm removal re:uires that the s(stem 0e put in a sleep state. %f the removal will 0e a warm removal,
2!'M puts the s(stem in the appropriate !x state. %f the removal will 0e a hot removal, 2!'M skips to
step 8, 0elow.
9. 5or warm removal, the s(stem is put in a sleep state. @ardware then uses an( motors, and so on, to
e#ect the device. %mmediatel( after e#ection, the hardware transitions the computer to !. %f the s(stem
was sleeping when the e#ect notification came in, the 2! returns the computer to a sleeping state
consistent with the userMs wake settings.
8. 2!'M calls C!TA to determine if the e#ect successfull( occurred. =%n this case, control methods do not
need to use the 0otif)=de2ice,3> command to tell 2!'M of the change in C!TA> %f there were an(
mechanical failures, C!TA returns 3< device present and not functioning, and 2!'M informs the user
of the pro0lem.
0ote< This mechanism is the same for removing a single device and for removing several devices, as in an
undock.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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AC'% does not disallow surprise&st(le removal of devicesK however, this t(pe of removal is not
recommended 0ecause s(stem and data integrit( cannot 0e guaranteed when a surprise&st(le removal
occurs. ;ecause the 2! is not informed, its device drivers cannot save data 0uffers and it cannot stop
accesses to the device 0efore the device is removed. To handle surprise&st(le removal, a general&purpose
event must 0e raised. %ts associated control method must use the Notif( command to indicate which 0us the
device was removed from.
The device insertion and removal o0#ects are listed in Ta0le +&4+.
Ta!le --+- 5evice Insertion' "e%oval' and Status 3!Cects
3!Cect 5escription
C.-1 20#ect that evaluates to a package of namespace references of device o0#ects that depend on
the device containing C.-1. Whenever the named device is e#ected, 2!'M e#ects all
dependent devices.
C.7- 20#ect that evaluates to the name of a device o0#ect on which a device depends. Whenever the
named device is e#ected, the dependent device must receive an e#ection notification.
C.7x Control method that e#ects a device.
C1CE Control method that locks or unlocks a device.
C2!T Control method invoked 0( 2!'M to conve( processing status to the platform..
C3MD 20#ect that indicates that the given device is remova0le.
C!TA Control method that returns a deviceMs status.
7.3.1 _EDL (Eject Device List)
This o0#ect evaluates to a package of namespace references containing the names of device o0#ects that
depend on the device under which the C.-1 o0#ect is declared. This is primaril( used to support docking
stations. ;efore the device under which the C.-1 o0#ect is declared ma( 0e e#ected, 2!'M prepares the
devices listed in the C.-1 o0#ect for ph(sical removal.
;efore 2!'M e#ects a device via the deviceMs C.7/ methods, all dependent devices listed in the package
returned 0( C.-1 are prepared for removal. Notice that C.7/ methods under the dependent devices are not
e/ecuted.
When descri0ing a platform that includes a docking station, an C.-1 o0#ect is declared under the docking
station device. 5or e/ample, if a mo0ile s(stem can attach to two different t(pes of docking stations, C.-1
is declared under 0oth docking station devices and evaluates to the packaged list of devices that must 0e
e#ected when the s(stem is e#ected from the docking station.
An AC'%&compliant 2! evaluates the C.-1 method #ust prior to e#ecting the device.
7.3.2 _EJD (Ejection Dependent Device)
This o0#ect is used to specif( the name of a device on which the device, under which this o0#ect is declared,
is dependent. This o0#ect is primaril( used to support docking stations. ;efore the device indicated 0( C.7-
is e#ected, 2!'M will prepare the dependent device =in other words, the device under which this o0#ect is
declared> for removal.
C.7- is evaluated once when the AC'% ta0le loads. The .7/ methods of the device indicated 0( C.7- will
0e used to e#ect all the dependent devices. A deviceMs dependents will 0e e#ected when the device itself is
e#ected.
0ote< 2!'M will not e/ecute a dependent deviceMs C.7/ methods when the device indicated 0( C.7- is
e#ected.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
342 Advanced Configuration and 'ower %nterface !pecification
When descri0ing a platform that includes a docking station, usuall( more than one C.7- o0#ect will 0e
needed. 5or e/ample, if a dock attaches 0oth a 'C% device and an AC'%&configured device to a mo0ile
s(stem, then 0oth the 'C% device description package and the AC'%&configured device description package
must include an C.7- o0#ect that evaluates to the name of the docking station =the name specified in an
CA-3 or C@%- o0#ect in the docking stationMs description package>. Thus, when the docking connector
signals an e#ect re:uest, 2!'M first attempts to disa0le and unload the drivers for 0oth the 'C% and AC'%
configured devices.
0ote< An AC'% 4. 2! evaluates the C.7- methods onl( once during the ta0le load process. This greatl(
restricts a ta0le designerMs freedom to descri0e d(namic dependencies such as those created in scenarios
with multiple docking stations. This restriction is illustrated in the e/ample 0elowK the C.7- information
supplied via and AC'% 4.&compati0le namespace omits the %-.2 device from -2CE2Ms list of e#ection
dependencies. !tarting in AC'% 2., 2!'M is presented with a more in&depth view of the e#ection
dependencies in a s(stem 0( use of the C.-1 methods.
1xa%ple
An e/ample use of C.7- and C.-1 is as follows<
Scope(\_SB.P)#()
Device(D0)A4) // Pa22 throu,h doc+ W D0)A4
!ame(_&DR$ Y)
;ethod(_%Z($ () Y/
;ethod(_D)A$ 4) Y/
!ame(_BD!$ Y)
;ethod(_S<&$ () (-5/
!ame(_%D6$ Pac+a,e( ) // D0)A4 ha2 two dependent device2 W #D%3 and )B3
\_SB.P)#(.#D%3$
\_SB.P)#(.)B3/)
/
Device(D0)A3) // Pa22 throu,h doc+ W D0)A3
!ame(_&DR$ Y)
;ethod(_%Z($ () Y/
;ethod(_D)A$ 4) Y/
!ame(_BD!$ Y)
;ethod(_S<&$ () (-(/
!ame(_%D6$ Pac+a,e( ) // D0)A3 ha2 one dependent device W #D%3
\_SB.P)#(.#D%3/)
/
Device(#D%4) // #D% Drive4 not dependent on the doc+
!ame(_&DR$ Y)
/
Device(#D%3) // #D% Drive3
!ame(_&DR$ Y)
!ame(_%ZD$*\\_SB.P)#(.D0)A4*) // Dependent on D0)A4
/
Device()B3) // )ardBu2 )ontroller
!ame(_&DR$ Y)
!ame(_%ZD$*\\_SB.P)#(.D0)A4*) // Dependent on D0)A4
/
/ // end \_SB.P)#0
7.3.3 _EJx (Eject)
These control methods are optional and are supplied for devices that support a software&controlled DC3&
st(le e#ection mechanism or that re:uire an action 0e performed such as isolation of powerFdata lines 0efore
the device can 0e removed from the s(stem. To support warm =s(stem is in a sleep state> and hot =s(stem is
in !> removal, an C.7x control method is listed for each sleep state from which the device supports
removal, where x is the sleeping state supported. 5or e/ample, C.7 indicates the device supports hot
removalK C.74I.7" indicate the device supports warm removal.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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5or hot removal, the device must 0e immediatel( e#ected when 2!'M calls the C.7 control method.
The C.7 control method does not return until e#ection is complete. After calling C.7, 2!'M verifies the
device no longer e/ists to determine if the e#ect succeeded. 5or C@%- devices, 2!'M evaluates the C!TA
method. 5or CA-3 devices, 2!'M checks with the 0us driver for that device.
5or warm removal, the C.74IC.7" control methods do not cause the device to 0e immediatel( e#ected.
%nstead, the( set proprietar( registers to prepare the hardware to e#ect when the s(stem goes into the given
sleep state. The hardware e#ects the device onl( after 2!'M has put the s(stem in a sleep state 0( writing
to the !1'C.N register. After the s(stem resumes, 2!'M calls C!TA to determine if the e#ect succeeded.
The C.7x control methods take one parameter to indicate whether e#ect should 0e ena0led or disa0led<
4I@ot e#ect or mark for e#ection
ICancel mark for e#ection =.7 will never 0e called with this value>
A device o0#ect ma( have multiple C.7x control methods. 5irst, it lists an .7/ control method for the
preferred sleeping state to e#ect the device. 2ptionall(, the device ma( list an .7" control method to 0e used
when the s(stem has no power =for e/ample, no 0atter(> after the e#ect. 5or e/ample, a hot&docking
note0ook might list C.7 and C.7".
7.3.4 _LCK (Lock)
This control method is optional and is re:uired onl( for a device that supports a software&controlled locking
mechanism. When the 2! invokes this control method, the associated device is to 0e locked or unlocked
0ased upon the value of the argument that is passed. 2n a lock re:uest, the control method must not
complete until the device is completel( locked.
The C1CE control method takes one parameter that indicates whether or not the device should 0e locked<
4 I1ock the device.
I,nlock the device.
When descri0ing a platform, devices use either a C1CE control method or an C.7x control method for a
device.
7.3.5 _OST (OSPM Status Indication)
This o0#ect is an optional control method that is invoked 0( 2!'M to indicate processing status to the
platform. -uring device e#ection, device hot add, or other event processing, 2!'M ma( need to perform
specific handshaking with the platform. 2!'M ma( also need to indicate to the platform its ina0ilit( to
complete a re:uested operationK for e/ample, when a user presses an e#ection 0utton for a device that is
currentl( in use or is otherwise currentl( incapa0le of 0eing e#ected. %n this case, the processing of the
AC'% 1Cect "eJuest notification 0( 2!'M fails. 2!'M ma( indicate this failure to the platform through
the invocation of the C2!T control method. As a result of the status notification indicating e#ection failure,
the platform ma( take certain action including reissuing the notification or perhaps turning on an
appropriate indicator light to signal the failure to the user.
Arguments<
Arg I so'rceFe2ent# DWord)on2t
%f the value of so'rceFe2ent is T\ /55, this argument is the AC'% notification value whose processing
generated the status indication. This is the value that was passed into the 0otif) operator.
%f the value of sourceCevent is /4 or greater then the 2!'M status indication is a result of an 2!'M
action as indicated in Ta0le +&49. 5or e/ample, a value of /43 will 0e passed into C2!T for this argument
upon the failure of a user interface invoked device e#ection.
%f 2!'M is una0le to identif( the originating notification value, 2!'M invokes C2!T with a value that
contains all 0its set =ones> for this parameter.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
34" Advanced Configuration and 'ower %nterface !pecification
Arg4 I !tatus Code< DWord)on2t. 2!'M indicates a notification value specific status. !ee Ta0les +&48
and +&46 for status code descriptions.
Arg2 I A 0uffer containing detailed 2!'M&specific information a0out the status indication. This argument
ma( 0e the null string.
3esults<
None
Ta!le --+. D3ST Source 1vent Codes
Source 1vent Code 5escription
&/55 3eserved for Notification Dalues
/4&/42 3eserved
/43 .#ection 'rocessing
/4"&/455 3eserved
/2 %nsertion 'rocessing
/24&/55555555 3eserved
Ta!le --+/ ;eneral Processing Status Codes
Status Code 5escription
!uccess
4 Non&specific failure
2 ,nrecogniHed Notif( Code
3&/95 3eserved
/8&/55555555 Notification value specific status codes
Ta!le --+, 1Cection "eJuest @ 1Cection Processing >Source 1ventsH $x$# and $x+$#? Status Codes
Status Code 5escription
/8 -evice e#ection not supported 0( 2!'M
/84 -evice in use 0( application
/82 -evice ;us(
/83 .#ection dependenc( is 0us( or not supported for e#ection 0( 2!'M
/8" .#ection is in progress =pending>
/8*&/55555555 3eserved
Ta!le --&$ Insertion Processing >Source 1ventH $x&$$? Status Codes
Status Code 5escription
/8 -evice insertion in progress =pending>
/84 -evice driver load failure
/82&/85 3eserved
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Status Code 5escription
/6&/65 %nsertion failure I 3esources ,navaila0le as descri0ed 0( the following 0it
encodings<
;itV3W ;us Num0ers
;itV2W %nterrupts
;itV4W %F2
;itVW Memor(
/A&/55555555 3eserved
%t is possi0le for the platform to issue multiple notifications to 2!'M and for 2!'M to process the
notifications as(nchronousl(. As such, 2!'M ma( invoke C2!T for notifications independent of the order
the notification are conve(ed 0( the platform or 0( software to 2!'M..
The figure 0elow provides and e/ample event flow of device e#ection on a platform emplo(ing the C2!T
o0#ect.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
34+ Advanced Configuration and 'ower %nterface !pecification
6igure --+ 5evice 1Cection 6low 1xa%ple 2sing D3ST
N2T.< To maintain compati0ilit( with 2!'M implementations of previous revisions of the AC'%
specification, the platform must not rel( on 2!'MMs evaluation of the C2!T o0#ect for proper platform
operation.
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./ample A!1 for C2!T usage<
Scope(\_SB.P)#.)
0perationRe,ion(6%D4$ S12tem#0$ (-4()($ (-3()
5ield(6%D4$ &n1&cc$ !o6oc+$ Pre2erve)
// 6%D control2
S(6%$ 4$ // Slot ( %9ection Pro,re22 6%D
S(65$ 4$ // Slot ( %9ection 5ailure 6%D
S46%$ 4$ // Slot 4 %9ection Pro,re22 6%D
S465$ 4$ // Slot 4 %9ection 5ailure 6%D
S36%$ 4$ // Slot 3 %9ection Pro,re22 6%D
S365$ 4$ // Slot 3 %9ection 5ailure 6%D
SF6%$ 4$ // Slot F %9ection Pro,re22 6%D
SF65$ 4 // Slot F %9ection 5ailure 6%D
/
Device(S6<F) // hot plu, device
!ame(_&DR$ (-((()(((F)
;ethod(_0S<$ F$ SerialiCed) // 0S call2 _0S< with notif1 code F or (-4(F
// and 2tatu2 code2 (-=(E(-=F
// to indicate a hot remove re8ue2t failure.
// Statu2 code (-=. indicate2 an e9ection
// re8ue2t pendin,.
#f(6%8ual(&r,($0ne2)) // Xn2pecified event

// Perform ,eneric event proce22in, here


/
Switch(&nd(&r,($(-55)) // ;a2+ to retain low b1te

)a2e((-(F) // %9ection re8ue2t

Switch(&r,4)

)a2e(Pac+a,e()(-=($ (-=4$ (-=3$ (-=F/)


// %9ection 5ailure for 2ome rea2on
Store(7ero$ \\SF6%) // <urn off %9ection Pro,re22 6%D
Store(0ne$ \\SF65) // <urn on %9ection 5ailure 6%D
/
)a2e((-=.) // %9ect re8ue2t pendin,

Store(0ne$ \\SF6%) // <urn on %9ection Re8ue2t 6%D


Store(7ero$ \\SF65) // <urn off %9ection 5ailure 6%D
/
/
/
/
/ // end _0S<
;ethod(_%Z($ 4) // Succe22ful e9ection 2e8uence

Store(7ero$ \\SF6%) // <urn off %9ection Pro,re22 6%D
/
/ // end S6<F
/ // end 2cope \_SB.P)#.
Scope (_:P%)

_%4F

Store(0ne$ \_SB.P)#..SF6%) // <urn on e9ection re8ue2t 6%D
!otif1(S6<F$ F) // %9ection re8ue2t driven from :P%4F
/
/
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348 Advanced Configuration and 'ower %nterface !pecification
7.3.6 _RMV (Remove)
The optional C3MD o0#ect indicates to 2!'M whether the device can 0e removed while the s(stem is in
the working state and does not re:uire an( AC'% s(stem firmware actions to 0e performed for the device to
0e safel( removed from the s(stem =in other words, an( device that onl( supports surprise&st(le removal>.
An( such remova0le device that does not have C1CE or C.7/ control methods must have an C3MD o0#ect.
This allows 2!'M to indicate to the user that the device can 0e removed and to provide a wa( for shutting
down the device 0efore removing it. 2!'M will transition the device into -3 0efore telling the user it is
safe to remove the device.
This method is reevaluated after a device&check notification.
Arguments<
None
3esult Code<
I The device cannot 0e removed.
4 I The device can 0e removed.
0ote< 2perating !(stems implementing AC'% 4. interpret the presence of this o0#ect to mean that the
device is remova0le.
7.3.7 _STA (Status)
This o0#ect returns the status of a device, which can 0e one of the following< ena0led, disa0led, or removed.
Arguments<
None
3esult Code =0itmap><
;it !et if the device is present.
;it 4 !et if the device is ena0led and decoding its resources.
;it 2 !et if the device should 0e shown in the ,%.
;it 3 !et if the device is functioning properl( =cleared if the device failed its diagnostics>.
;it " !et if the 0atter( is present.
;its *I34 3eserved =must 0e cleared>.
%f 0it is cleared, then 0it 4 must also 0e cleared =in other words, a device that is not present cannot 0e
ena0led>.
A device can onl( decode its hardware resources if 0oth 0its and 4 are set. %f the device is not present =0it
cleared> or not ena0led =0it 4 cleared>, then the device must not decode its resources.
%f a device is present in the machine, 0ut should not 0e displa(ed in 2!'M user interface, 0it 2 is cleared.
5or e/ample, a note0ook could have #o(stick hardware =thus it is present and decoding its resources>, 0ut
the connector for plugging in the #o(stick re:uires a port replicator. %f the port replicator is not plugged in,
the #o(stick should not appear in the ,%, so 0it 2 is cleared.
C!TA ma( return 0it clear =not present> with 0it 3 set =device is functional>. This case is used to indicate
a valid device for which no device driver should 0e loaded =for e/ample, a 0ridge device.> Children of this
device ma( 0e present and valid. 2!'M should continue enumeration 0elow a device whose C!TA returns
this 0it com0ination.
%f a device o0#ect =including the processor o0#ect> does not have an C!TA o0#ect, then 2!'M assumes that
all of the a0ove 0its are set =in other words, the device is present, ena0led, shown in the ,%, and
functioning>.
This method must not reference an( operation regions that have not 0een declared availa0le 0( a C3.$
method.
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7.4 Resource Data Types for ACPI
The CC3!, C'3!, and C!3! control methods use packages of resource descriptors to descri0e the resource
re:uirements of devices.
7.4.1 ASL Macros for Resource Descriptors
A!1 includes some macros for creating resource descriptors. The A!1 s(nta/ for these macros is defined in
section 49.*, JA!1 2perator 3eferenceL, along with the other A!1 operators.
7.4.2 Small Resource Data Type
A small resource data t(pe ma( 0e 2 to 8 0(tes in siHe and adheres to the following format<
Ta!le --&+ S%all "esource 5ata T)pe Tag <it 5efinitions
3ffset 6ield
;(te Tag <itN.O Tag <itsN-H#O Tag <its N&H$O
T(peI !mall item name 1engthIn 0(tes
;(tes 4 to n -ata 0(tes
The following small information items are currentl( defined for 'lug and 'la( devices<
Ta!le --&& S%all "esource Ite%s
S%all Ite% 0a%e 7alue
3eserved /4
3eserved /2
3eserved /3
%3G format /"
-MA format /*
!tart dependent 5unction /+
.nd dependent 5unction /9
%F2 port descriptor /8
5i/ed location %F2 port descriptor /6
3eserved /AI/-
Dendor defined /.
.nd tag /5
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7.4.2.1
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IRQ Descriptor
T)pe $' S%all Ite% 0a%e $x(' Length P & or #
The %3G data structure indicates that the device uses an interrupt level and supplies a mask with 0its set
indicating the levels implemented in this device. 5or standard 'C&AT implementation there are 4* possi0le
interrupts so a two&0(te field is used. This structure is repeated for each separate interrupt re:uired.
Ta!le --&# I"K 5escriptor 5efinition
3ffset 6ield 0a%e
;(te Dalue \ 44n; =T(pe \ , small item name \ /", length \ =2 or 3>>
;(te 4 %3G mask 0itsV9<W, C%NT
;itVW represents %3G, 0itV4W is %3G4, and so on.
;(te 2 %3G mask 0itsV4*<8W, C%NT
;itVW represents %3G8, 0itV4W is %3G6, and so on.
;(te 3 %3G %nformation. .ach 0it, when set, indicates this device is capa0le of driving a certain t(pe of
interrupt. =2ptionalPif not included then assume edge sensitive, high true interrupts.> These 0its
can 0e used 0oth for reporting and setting %3G resources.
0oteH This descriptor is meant for descri0ing interrupts that are connected to '%C&compati0le
interrupt controllers, which can onl( 0e programmed for Active&@igh&.dge&Triggered or Active&
1ow&1evel&Triggered interrupts. An( other com0ination is illegal. The ./tended %nterrupt
-escriptor can 0e used to descri0e other com0inations.
;itV9<*W $eser2ed =must 0e >
;itV"W %nterrupt is shara0le, C!@3
;itV3W %nterrupt 'olarit(, C11
Active&@igh I This interrupt is sampled when the signal is high, or true
4 Active&1ow I This interrupt is sampled when the signal is low, or false.
;itV2<4W Ignored
;itVW %nterrupt Mode, C@.
1evel&Triggered I %nterrupt is triggered in response to signal in a low state.
4 .dge&Triggered I %nterrupt is triggered in response to a change in signal state
from low to high.
0ote< 1ow true, level sensitive interrupts ma( 0e electricall( shared, 0ut the process of how this might
work is 0e(ond the scope of this specification.
0ote< %f 0(te 3 is not included, @igh true, edge sensitive, non&sharea0le is assumed.
!ee section 49.*.**, J%nterrupt =%nterrupt 3esource -escriptor Macro,L for a description of the A!1 macro
that creates an %3G descriptor.
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7.4.2.2
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DMA Descriptor
T)pe $' S%all Ite% 0a%e $xA' Length P &
The -MA data structure indicates that the device uses a -MA channel and supplies a mask with 0its set
indicating the channels actuall( implemented in this device. This structure is repeated for each separate
channel re:uired.
Ta!le --&( 5MA 5escriptor 5efinition
3ffset 6ield 0a%e
;(te Dalue \ 444; =T(pe \ , small item name \ /*, length \ 2>
;(te 4 -MA channel mask 0itsV9<W, C-MA
;itVW is channel
;(te 2
;itV9W $eser2ed =must 0e >
;itsV+<*W -MA channel speed supported, CTS'
%ndicates compati0ilit( mode
4 %ndicates T(pe A -MA as descri0ed in the .%!A
4 %ndicates T(pe ; -MA
44 %ndicates T(pe 5
;itsV"<3W Ignored
;itV2W 1ogical device 0us master status, C;M
1ogical device is not a 0us master
4 1ogical device is a 0us master
;itsV4<W -MA transfer t(pe preference, C!%?
8&0it onl(
4 8& and 4+&0it
4 4+&0it onl(
44 $eser2ed
!ee section 49.*.3, J-MA =-MA 3esource -escriptor Macro>,L for a description of the A!1 macro that
creates a -MA descriptor.
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7.4.2.3
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Start Dependent Functions Descriptor
T)pe $' S%all Ite% 0a%e $x-' Length P $ or +
.ach logical device re:uires a set of resources. This set of resources ma( have interdependencies that need
to 0e e/pressed to allow ar0itration software to make resource allocation decisions a0out the logical device.
-ependent functions are used to e/press these interdependencies. The data structure definitions for
dependent functions are shown here. 5or a detailed description of the use of dependent functions refer to
the ne/t section.
Ta!le --&A Start 5ependent 6unctions
3ffset 6ield 0a%e
;(te Dalue \ C44Cn; =T(pe \ , small item name \ /+, length \= or 4>>
!tart -ependent 5unction fields ma( 0e of length or 4 0(tes. The e/tra 0(te is optionall( used to denote
the compati0ilit( or performanceFro0ustness priorit( for the resource group following the !tart -5 tag. The
compati0ilit( priorit( is a ranking of configurations for compati0ilit( with legac( operating s(stems. This is
the same as the priorit( used in the 'N';%2! interface. 5or e/ample, for compati0ilit( reasons, the
preferred configuration for C2M4 is %3G", %F2 358&355. The performanceFro0ustness performance is a
ranking of configurations for performance and ro0ustness reasons. 5or e/ample, a device ma( have a high&
performance, 0us mastering configuration that ma( not 0e supported 0( legac( operating s(stems. The 0us&
mastering configuration would have the highest performanceFro0ustness priorit( while its polled %F2 mode
might have the highest compati0ilit( priorit(.
%f the 'riorit( 0(te is not included, this indicates the dependent function priorit( is Oaccepta0leM. This 0(te is
defined as<
Ta!le --&- Start 5ependent 6unction Priorit) <)te 5efinition
<its 5efinition
4<
Compati0ilit( priorit(. Accepta0le values are<
$ood configuration< @ighest 'riorit( and preferred configuration
4 Accepta0le configuration< 1ower 'riorit( 0ut accepta0le configuration
2 !u0&optimal configuration< 5unctional configuration 0ut not optimal
3 3eserved
3<2
'erformanceFro0ustness. Accepta0le values are<
$ood configuration< @ighest 'riorit( and preferred configuration
4 Accepta0le configuration< 1ower 'riorit( 0ut accepta0le configuration
2 !u0&optimal configuration< 5unctional configuration 0ut not optimal
3 3eserved
9<" $eser2ed =must 0e >
Notice that if multiple -ependent 5unctions have the same priorit(, the( are further prioritiHed 0( the order
in which the( appear in the resource data structure. The -ependent 5unction that appears earliest =nearest
the 0eginning> in the structure has the highest priorit(, and so on.
!ee section 49.*.444, J!tart-ependent5n =!tart -ependent 5unction 3esource -escriptor Macro>,L for a
description of the A!1 macro that creates a !tart -ependent 5unction descriptor.
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7.4.2.4
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End Dependent Functions Descriptor
T)pe $' S%all Ite% 0a%e $x.' Length P $
2nl( one .nd -ependent 5unction item is allowed per logical device. This enforces the fact that -ependent
5unctions cannot 0e nested.
Ta!le --&. 1nd 5ependent 6unctions
3ffset 6ield 0a%e
;(te Dalue \ C444C; =T(pe \ , small item name \ /9 length \>
!ee section 49.*.39, J.nd-ependent5n =.nd -ependent 5unction 3esource -escriptor Macro,L for a
description of the A!1 macro that creates an .nd -ependent 5unctions descriptor.
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7.4.2.5
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I/O Port Descriptor
T)pe $' S%all Ite% 0a%e $x/' Length P .
There are two t(pes of descriptors for %F2 ranges. The first descriptor is a full function descriptor for
programma0le devices. The second descriptor is a minimal descriptor for old %!A cards with fi/ed %F2
re:uirements that use a 4&0it %!A address decode. The first t(pe descriptor can also 0e used to descri0e
fi/ed %F2 re:uirements for %!A cards that re:uire a 4+&0it address decode. This is accomplished 0( setting
the range minimum 0ase address and range ma/imum 0ase address to the same fi/ed %F2 value.
Ta!le --&/ I@3 Port 5escriptor 5efinition
3ffset 6ield 0a%e 5efinition
;(te %F2 port descriptor Dalue \ 4444; =T(pe \ , !mall item name \ /8, 1ength \ 9>
;(te 4 %nformation
;itsV9<4W $eser2ed and must 0e
;itVW =C-.C>
4 The logical device decodes 4+&0it addresses
The logical device onl( decodes address 0itsV6<W
;(te 2 3ange minimum 0ase
address, CM%N 0itsV9<W
Address 0itsV9<W of the minimum 0ase %F2 address that the card ma( 0e
configured for.
;(te 3 3ange minimum 0ase
address, CM%N 0itsV4*<8W
Address 0itsV4*<8W of the minimum 0ase %F2 address that the card ma(
0e configured for.
;(te " 3ange ma/imum 0ase
address, CMAA 0itsV9<W
Address 0itsV9<W of the ma/imum 0ase %F2 address that the card ma(
0e configured for.
;(te * 3ange ma/imum 0ase
address, CMAA 0itsV4*<8W
Address 0itsV4*<8W of the ma/imum 0ase %F2 address that the card ma(
0e configured for.
;(te + ;ase alignment, CA1N Alignment for minimum 0ase address, increment in 4&0(te 0locks.
;(te 9 3ange length, C1.N The num0er of contiguous %F2 ports re:uested.
!ee section 49.*.*+, J%2 =%2 3esource -escriptor Macro,L for a description of the A!1 macro that creates
an %F2 'ort descriptor.
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33 Advanced Configuration and 'ower %nterface !pecification
7.4.2.6
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Fixed Location I/O Port Descriptor
T)pe $' S%all Ite% 0a%e $x,' Length P #
This descriptor is used to descri0e 4&0it %F2 locations.
Ta!le --&, 6ixed-Location I@3 Port 5escriptor 5efinition
3ffset 6ield 0a%e 5efinition
;(te 5i/ed 1ocation %F2 port
descriptor
Dalue \ 4444; =T(pe \ , !mall item name \ /6, 1ength \ 3>
;(te 4 3ange 0ase address,
C;A! 0itsV9<W
Address 0itsV9<W of the 0ase %F2 address that the card ma( 0e configured
for. This descriptor assumes a 4&0it %!A address decode.
;(te 2 3ange 0ase address,
C;A! 0itsV6<8W
Address 0itsV6<8W of the 0ase %F2 address that the card ma( 0e configured
for. This descriptor assumes a 4&0it %!A address decode.
;(te 3 3ange length, C1.N The num0er of contiguous %F2 ports re:uested.
!ee section 49.*."9, J5i/ed%2 =5i/ed %F2 3esource -escriptor Macro,L for a description of the A!1 macro
that creates a 5i/ed %F2 'ort descriptor.
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7.4.2.7
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Vendor-Defned Descriptor
T)pe $' S%all Ite% 0a%e $x1' Length P + to .
The vendor defined resource data t(pe is for vendor use.
Ta!le --#$ 7endor-5efined "esource 5escriptor 5efinition
3ffset 6ield 0a%e
;(te Dalue \ 444nnn; =T(pe \ , small item name \ /., length \ =4&9>>
;(te 4 to 9 Dendor defined
!ee Dendor!hort =page 8"4> for a description of the A!1 macro that creates a short vendor&defined resource
descriptor.
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33" Advanced Configuration and 'ower %nterface !pecification
7.4.2.8
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End Tag
T)pe $' S%all Ite% 0a%e $x6' Length P +
The .nd tag identifies an end of resource data.
0oteH %f the checksum field is Hero, the resource data is treated as if the checksum operation succeeded.
Configuration proceeds normall(.
Ta!le --#+ 1nd Tag 5efinition
3ffset 6ield 0a%e
;(te Dalue \ 44444; =T(pe \ , small item name \ /5, length \ 4>
;(te 4 Checksum covering all resource data after the serial identifier. This checksum is
generated such that adding it to the sum of all the data 0(tes will produce a Hero sum.
The .nd Tag is automaticall( generated 0( the A!1 compiler at the end of the "esourceTe%plate
statement.
7.4.3 Large Resource Data Type
To allow for larger amounts of data to 0e included in the configuration data structure the large format is
shown 0elow. This includes a 4+&0it length field allowing up to +" E; of data.
Ta!le --#& Large "esource 5ata T)pe Tag <it 5efinitions
3ffset 6ield 0a%e
;(te Dalue \ 4///////; =T(pe \ 4, 1arge item name \ ///////>
;(te 4 1ength of data items 0itsV9<W
;(te 2 1ength of data items 0itsV4*<8W
;(tes 3 to
=1ength Z 2>
Actual data items
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The following large information items are currentl( defined for 'lug and 'la( %!A devices<
Ta!le --## Large "esource Ite%s
Large Ite% 0a%e 7alue
2"&0it memor( range descriptor /4
$eneric register descriptor /2
3eserved /3
Dendor defined /"
32&0it memor( range descriptor /*
32&0it fi/ed location memor( range descriptor /+
-W23- address space descriptor /9
W23- address space descriptor /8
./tended %3G descriptor /6
GW23- address space descriptor /A
./tended address space descriptor /;
3eserved /C && /95
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7.4.3.1
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338 Advanced Configuration and 'ower %nterface !pecification
24-Bit Memory Range Descriptor
T)pe +' Large Ite% 0a%e $x+
The 2"&0it memor( range descriptor descri0es a deviceMs memor( range resources within a 2"&0it address
space.
Ta!le --#( Large Me%or) "ange 5escriptor 5efinition
3ffset 6ield 0a%e' ASL 6ield
0a%e
5efinition
;(te Memor( range descriptor Dalue \ 44; =T(pe \ 4, 1arge item name \ /4>
;(te 4 1ength, 0itsV9<W Dalue \ 44; =6>
;(te 2 1ength, 0itsV4*<8W Dalue \ ; =>
;(te 3 %nformation This field provides e/tra information a0out this memor(.
;itV9<4W Ignored
;itVW Write status, C3W
4 writea0le =readFwrite>
non&writea0le =read&onl(>
;(te " 3ange minimum 0ase
address, CM%N, 0itsV9<W
Address 0itsV4*<8W of the minimum 0ase memor( address for
which the card ma( 0e configured.
;(te * 3ange minimum 0ase
address, CM%N, 0itsV4*<8W
Address 0itsV23<4+W of the minimum 0ase memor( address for
which the card ma( 0e configured
;(te + 3ange ma/imum 0ase
address, CMAA, 0itsV9<W
Address 0itsV4*<8W of the ma/imum 0ase memor( address for
which the card ma( 0e configured.
;(te 9 3ange ma/imum 0ase
address, CMAA, 0itsV4*<8W
Address 0itsV23<4+W of the ma/imum 0ase memor( address for
which the card ma( 0e configured
;(te 8 ;ase alignment, CA1N,
0itsV9<W
This field contains the lower eight 0its of the 0ase alignment. The
0ase alignment provides the increment for the minimum 0ase
address. =/ \ +" E;>
;(te 6 ;ase alignment, CA1N,
0itsV4*<8W
This field contains the upper eight 0its of the 0ase alignment. The
0ase alignment provides the increment for the minimum 0ase
address. =/ \ +" E;>
;(te 4 3ange length, C1.N,
0itsV9<W
This field contains the lower eight 0its of the memor( range
length. The range length provides the length of the memor( range
in 2*+ 0(te 0locks.
;(te 44 3ange length, C1.N,
0itsV4*<8W
This field contains the upper eight 0its of the memor( range
length. The range length field provides the length of the memor(
range in 2*+ 0(te 0locks.
0otesH
Address 0its V9<W of memor( 0ase addresses are assumed to 0e .
A Memor( range descriptor can 0e used to descri0e a fi/ed memor( address 0( setting the range
minimum 0ase address and the range ma/imum 0ase address to the same value.
2"&0it Memor( 3ange descriptors are used for legac( devices.
Mi/ing of 2"&0it and 32&0it memor( descriptors on the same device is not allowed.
!ee section 49.*.92, JMemor(2" =Memor( 3esource -escriptor Macro>,L for a description of the A!1
macro that creates a 2"&0it Memor( descriptor.
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7.4.3.2
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Vendor-Defned Descriptor
T)pe +' Large Ite% 0a%e $x(
The vendor defined resource data t(pe is for vendor use.
Ta!le --#A Large 7endor-5efined "esource 5escriptor 5efinition
3ffset 6ield 0a%e 5efinition
;(te Dendor defined Dalue \ 44; =T(pe \ 4, 1arge item name \ /">
;(te 4 1ength, 0itsV9<W 1ower eight 0its of data length =,,%%- c vendor defined
data>
;(te 2 1ength, 0itsV4*<8W ,pper eight 0its of data length =,,%- c vendor defined
data>
;(te 3 ,,%- specific descriptor su0 t(pe ,,%- specific descriptor su0 t(pe value
;(te "&46 ,,%- ,,%- Dalue
;(te 2&
=1engthZ2>
Dendor -efined -ata Dendor defined data 0(tes
AC'% 3. defines the ,,%- specific descriptor su0t(pe field and the ,,%- field to address potential
collision of the use of this descriptor. %t is strongl( recommended that all newl( defined vendor descriptors
use these fields prior to Dendor -efined -ata.
!ee Dendor1ong =page 8"> for a description of the A!1 macro that creates a long vendor&defined resource
descriptor.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 3"4
7.4.3.3
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3"2 Advanced Configuration and 'ower %nterface !pecification
32-Bit Memory Range Descriptor
T)pe +' Large Ite% 0a%e $xA
This memor( range descriptor descri0es a deviceMs memor( resources within a 32&0it address space.
Ta!le --#- Large #&-<it Me%or) "ange 5escriptor 5efinition
3ffset 6ield 0a%e 5efinition
;(te Memor( range descriptor Dalue \ 444; =T(pe \ 4, 1arge item name \ /*>
;(te 4 1ength, 0itsV9<W Dalue \ 44; =49>
;(te 2 1ength, 0itsV4*<8W Dalue \ ; =>
;(te 3 %nformation This field provides e/tra information a0out this memor(.
;itV9<4W Ignored
;itVW Write status, C3W
4 writea0le =readFwrite>
non&writea0le =read&onl(>
;(te " 3ange minimum 0ase address,
CM%N, 0itsV9<W
Address 0itsV9<W of the minimum 0ase memor( address for
which the card ma( 0e configured.
;(te * 3ange minimum 0ase address,
CM%N, 0itsV4*<8W
Address 0itsV4*<8W of the minimum 0ase memor( address for
which the card ma( 0e configured.
;(te + 3ange minimum 0ase address,
CM%N, 0itsV23<4+W
Address 0itsV23<4+W of the minimum 0ase memor( address for
which the card ma( 0e configured.
;(te 9 3ange minimum 0ase address,
CM%N, 0itsV34<2"W
Address 0itsV34<2"W of the minimum 0ase memor( address for
which the card ma( 0e configured.
;(te 8 3ange ma/imum 0ase address,
CMAA, 0itsV9<W
Address 0itsV9<W of the ma/imum 0ase memor( address for
which the card ma( 0e configured.
;(te 6 3ange ma/imum 0ase address,
CMAA, 0itsV4*<8W
Address 0itsV4*<8W of the ma/imum 0ase memor( address for
which the card ma( 0e configured.
;(te 4 3ange ma/imum 0ase address,
CMAA, 0itsV23<4+W
Address 0itsV23<4+W of the ma/imum 0ase memor( address for
which the card ma( 0e configured.
;(te 44 3ange ma/imum 0ase address,
CMAA, 0itsV34<2"W
Address 0itsV34<2"W of the ma/imum 0ase memor( address for
which the card ma( 0e configured.
;(te 42 ;ase alignment, CA1N 0itsV9<W
This field contains ;itsV9<W of the 0ase alignment. The 0ase
alignment provides the increment for the minimum 0ase
address.
;(te 43 ;ase alignment, CA1N 0itsV4*<8W
This field contains ;itsV4*<8W of the 0ase alignment. The 0ase
alignment provides the increment for the minimum 0ase
address.
;(te 4" ;ase alignment, CA1N 0itsV23<4+W
This field contains ;itsV23<4+W of the 0ase alignment. The 0ase
alignment provides the increment for the minimum 0ase
address.
;(te 4* ;ase alignment, CA1N 0itsV34<2"W
This field contains ;itsV34<2"W of the 0ase alignment. The 0ase
alignment provides the increment for the minimum 0ase
address.
;(te 4+ 3ange length, C1.N 0itsV9<W
This field contains ;itsV9<W of the memor( range length. The
range length provides the length of the memor( range in 4&
0(te 0locks.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 3"3
3ffset 6ield 0a%e 5efinition
;(te 49 3ange length, C1.N 0itsV4*<8W
This field contains ;itsV4*<8W of the memor( range length. The
range length provides the length of the memor( range in 4&
0(te 0locks.
;(te 48 3ange length, C1.N 0itsV23<4+W
This field contains ;itsV23<4+W of the memor( range length.
The range length provides the length of the memor( range in
4&0(te 0locks.
;(te 46 3ange length, C1.N 0itsV34<2"W
This field contains ;itsV34<2"W of the memor( range length.
The range length provides the length of the memor( range in
4&0(te 0locks.
0oteH Mi/ing of 2"&0it and 32&0it memor( descriptors on the same device is not allowed.
!ee section 49.*.93, JMemor(32 =Memor( 3esource -escriptor Macro>,L for a description of the A!1
macro that creates a 32&0it Memor( descriptor.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3"" Advanced Configuration and 'ower %nterface !pecification
7.4.3.4
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 3"*
32-Bit Fixed Memory Range Descriptor
T)pe +' Large Ite% 0a%e $x-
This memor( range descriptor descri0es a deviceMs memor( resources within a 32&0it address space.
Ta!le --#. Large 6ixed-Location Me%or) "ange 5escriptor 5efinition
3ffset 6ield 0a%e 5efinition
;(te Memor( range descriptor Dalue \ 444; =T(pe \ 4, 1arge item name \ +>
;(te 4 1ength, 0itsV9<W Dalue \ 44; =6>
;(te 2 1ength, 0itsV4*<8W Dalue \ ; =>
;(te 3 %nformation This field provides e/tra information a0out this memor(.
;itV9<4W Ignored
;itVW Write status, C3W
4 writea0le =readFwrite>
non&writea0le =read&onl(>>
;(te " 3ange 0ase address,
C;A! 0itsV9<W
Address 0itsV9<W of the 0ase memor( address for which the card ma(
0e configured.
;(te * 3ange 0ase address,
C;A! 0itsV4*<8W
Address 0itsV4*<8W of the 0ase memor( address for which the card ma(
0e configured.
;(te + 3ange 0ase address,
C;A! 0itsV23<4+W
Address 0itsV23<4+W of the 0ase memor( address for which the card ma(
0e configured.
;(te 9 3ange 0ase address,
C;A! 0itsV34<2"W
Address 0itsV34<2"W of the 0ase memor( address for which the card ma(
0e configured.
;(te 8 3ange length, C1.N
0itsV9<W
This field contains ;itsV9<W of the memor( range length. The range
length provides the length of the memor( range in 4&0(te 0locks.
;(te 6 3ange length, C1.N
0itsV4*<8W
This field contains ;itsV4*<8W of the memor( range length. The range
length provides the length of the memor( range in 4&0(te 0locks.
;(te 4 3ange length, C1.N
0itsV23<4+W
This field contains ;itsV23<4+W of the memor( range length. The range
length provides the length of the memor( range in 4&0(te 0locks.
;(te 44 3ange length, C1.N
0itsV34<2"W
This field contains ;itsV34<2"W of the memor( range length. The range
length provides the length of the memor( range in 4&0(te 0locks.
0oteH Mi/ing of 2"&0it and 32&0it memor( descriptors on the same device is not allowed.
!ee section 49.*.9", JMemor(325i/ed =Memor( 3esource -escriptor>,L for a description of the A!1 macro
that creates a 32&0it 5i/ed Memor( descriptor.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3"+ Advanced Configuration and 'ower %nterface !pecification
7.4.3.5
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 3"9
Address Space Resource Descriptors
The GW23-, -W23-, W23-, and ./tended Address !pace -escriptors are general&purpose structures
for descri0ing a variet( of t(pes of resources. These resources also include support for advanced server
architectures =such as multiple root 0uses>, and resource t(pes found on some 3%!C processors. These
descriptors can descri0e various kinds of resources. The following ta0le defines the valid com0ination of
each field and how the( should 0e interpreted.
Ta!le --#/ 7alid co%!ination of Address Space 5escriptors fields
DL10 DMI6 DMA6 5efinition
Daria0le siHe, varia0le location resource descriptor for C'3!.
%f CM%5 is set, CM%N must 0e a multiple of =C$3AZ4>. %f CMA5 is set, CMAA
must 0e =a multiple of =C$3AZ4>>&4.
2! can pick the resource range that satisfies following conditions<
%f CM%5 is not set, start address is a multiple of =C$3AZ4> and greater
or e:ual to CM%N. 2therwise, start address is CM%N.
%f CMA5 is not set, end address is =a multiple of =C$3AZ4>>&4 and less
or e:ual to CMAA. 2therwise, end address is CMAA.
4
4
4 4 =%llegal com0ination>
) 5i/ed siHe, varia0le location resource descriptor for C'3!.
C1.N must 0e a multiple of =C$3AZ4>.
2! can pick the resource range that satisfies following conditions<
!tart address is a multiple of =C$3AZ4> and greater or e:ual to CM%N.
.nd address is =start addressZC1.N&4> and less or e:ual to CMAA.
) 4 =%llegal com0ination>
) 4 =%llegal com0ination>
) 4 4 5i/ed siHe, fi/ed location resource descriptor.
C$3A must 0e and C1.N must 0e =CMAA & CM%N Z4>.
7.4.3.5.1 QWord Address Space Descriptor
T)pe +' Large Ite% 0a%e $xA
The GW23- address space descriptor is used to report resource usage in a +"&0it address space =like
memor( and %F2>.
Ta!le --#, K:3"5 Address Space 5escriptor 5efinition
3ffset 6ield 0a%e 5efinition
;(te GW23- Address !pace
-escriptor
Dalue\444; =T(pe \ 4, 1arge item name \ /A>
;(te 4 1ength, 0itsV9<W Daria0le< Dalue \ "3 =minimum>
;(te 2 1ength, 0itsV4*<8W Daria0le< Dalue \ =minimum>
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3"8 Advanced Configuration and 'ower %nterface !pecification
3ffset 6ield 0a%e 5efinition
;(te 3 3esource T(pe %ndicates which t(pe of resource this descriptor descri0es. -efined
values are<
Memor( range
4 %F2 range
2 ;us num0er range
3I464 $eser2ed
462&2**@ardware Dendor -efined
;(te " $eneral 5lags 5lags that are common to all resource t(pes<
;itsV9<"W $eser2ed =must 0e >
;itV3W Min Address 5i/ed, CMA5<
4 The specified ma/imum address is fi/ed
The specified ma/imum address is not fi/ed
and can 0e changed
;itV2W Ma/ Address 5i/ed,CM%5<
4 The specified minimum address is fi/ed
The specified minimum address is not fi/ed
and can 0e changed
;itV4W -ecode T(pe, C-.C<
4 This 0ridge su0tractivel( decodes this address
=top level 0ridges onl(>
This 0ridge positivel( decodes this address
;itVW ConsumerF'roducer<
4IThis device consumes this resource
IThis device produces and consumes this resource
;(te * T(pe !pecific 5lags 5lags that are specific to each resource t(pe. The meaning of the
flags in this field depends on the value of the 3esource T(pe field
=see a0ove>.
;(te + Address space granularit(,
C$3A 0itsV9<W
A set 0it in this mask means that this 0it is decoded. All 0its less
significant than the most significant set 0it must 0e set. That is, the
value of the full Address !pace $ranularit( field =all 32 0its> must
0e a num0er =2
n
&4>.
;(te 9 Address space granularit(,
C$3A 0itsV4*<8W
;(te 8 Address space granularit(,
C$3A 0itsV23<4+W
;(te 6 Address space granularit(,
C$3A 0itsV34<2"W
;(te 4 Address space granularit(,
C$3A 0itsV36<32W
;(te 44 Address space granularit(,
C$3A 0itsV"9<"W
;(te 42 Address space granularit(,
C$3A 0itsV**<"8W
;(te 43 Address space granularit(,
C$3A 0itsV+3<*+W
;(te 4" Address range minimum,
CM%N 0itsV9<W
5or 0ridges that translate addresses, this is the address space on the
secondar( side of the 0ridge.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 3"6
3ffset 6ield 0a%e 5efinition
;(te 4* Address range minimum,
CM%N 0itsV4*<8W
;(te 4+ Address range minimum,
CM%N 0itsV23<4+W
;(te 49 Address range minimum,
CM%N 0itsV34<2"W
;(te 48 Address range minimum,
CM%N 0itsV36<32W
;(te 46 Address range minimum,
CM%N 0itsV"9<"W
;(te 2 Address range minimum,
CM%N 0itsV**<"8W
;(te 24 Address range minimum,
CM%N 0itsV+3<*+W
;(te 22 Address range ma/imum,
CMAA 0itsV9<W
5or 0ridges that translate addresses, this is the address space on the
secondar( side of the 0ridge.
;(te 23 Address range ma/imum,
CMAA 0itsV4*<8W
;(te 2" Address range ma/imum,
CMAA 0itsV23<4+W
;(te 2* Address range ma/imum,
CMAA 0itsV34<2"W
;(te 2+ Address range ma/imum,
CMAA 0itsV36<32W
5or 0ridges that translate addresses, this is the address space on the
secondar( side of the 0ridge.
;(te 29 Address range ma/imum,
CMAA 0itsV"9<"W
;(te 28 Address range ma/imum,
CMAA 0itsV**<"8W
;(te 26 Address range ma/imum,
CMAA 0itsV+3<*+W
;(te 3 Address Translation offset,
CT3A 0itsV9<W
5or 0ridges that translate addresses across the 0ridge, this is the
offset that must 0e added to the address on the secondar( side to
o0tain the address on the primar( side. Non&0ridge devices must list
for all Address Translation offset 0its.
;(te 34 Address Translation offset,
CT3A 0itsV4*<8W
;(te 32 Address Translation offset,
CT3A 0itsV23<4+W
;(te 33 Address Translation offset,
CT3A 0itsV34<2"W
;(te 3" Address Translation offset,
CT3A 0itsV36<32W
;(te 3* Address Translation offset,
CT3A 0itsV"9<"W
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3* Advanced Configuration and 'ower %nterface !pecification
3ffset 6ield 0a%e 5efinition
;(te 3+ Address Translation offset,
CT3A 0itsV**<"8W
;(te 39 Address Translation offset,
CT3A 0itsV+3<*+W
;(te 38 Address length, C1.N
0itsV9<W
;(te 36 Address length, C1.N,
0itsV4*<8W
;(te " Address length, C1.N
0itsV23<4+W
;(te "4 Address length, C1.N
0itsV34<2"W
;(te "2 Address length, C1.N
0itsV36<32W
;(te "3 Address length, C1.N
0itsV"9<"W
;(te "" Address length, C1.N
0itsV**<"8W
;(te "* Address length, C1.N
0itsV+3<*+W
;(te "+ 3esource !ource %nde/ =2ptional> 2nl( present if 3esource !ource =0elow> is present. This
field gives an inde/ to the specific resource descriptor that this
device consumes from in the current resource template for the
device o0#ect pointed to in 3esource !ource.
!tring 3esource !ource =2ptional> %f present, the device that uses this descriptor consumes
its resources from the resources produced 0( the named device
o0#ect. %f not present, the device consumes its resources out of a
glo0al pool. %f not present, the device consumes this resource from
its hierarchical parent.
!ee GWord%2 =page 823>, GWordMemor( =page 82*> and A!1CGWordAddress!pace for a description of
the A!1 macros that creates a GW23- Address !pace descriptor.
7.4.3.5.2 DWord Address Space Descriptor
T)pe +' Large Ite% 0a%e $x.
The -W23- address space descriptor is used to report resource usage in a 32&0it address space =like
memor( and %F2>.
Ta!le --($ 5:3"5 Address Space 5escriptor 5efinition
3ffset 6ield 0a%e 5efinition
;(te -W23- Address !pace
-escriptor
Dalue\4444; =T(pe \ 4, 1arge item name \ /9>
;(te 4 1ength, 0itsV9<W Daria0le< Dalue \ 23 =minimum>
;(te 2 1ength, 0itsV4*<8W Daria0le< Dalue \ =minimum>
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 3*4
3ffset 6ield 0a%e 5efinition
;(te 3 3esource T(pe %ndicates which t(pe of resource this descriptor descri0es. -efined
values are<
Memor( range
4 %F2 range
2 ;us num0er range
3I464 $eser2ed
462&2**@ardware Dendor -efined
;(te " $eneral 5lags 5lags that are common to all resource t(pes<
;itsV9<"W $eser2ed =must 0e >
;itV3W Min Address 5i/ed, CMA5<
4 The specified ma/imum address is fi/ed
The specified ma/imum address is not fi/ed
and can 0e changed
;itV2W Ma/ Address 5i/ed,CM%5<
4 The specified minimum address is fi/ed
The specified minimum address is not fi/ed
and can 0e changed
;itV4W -ecode T(pe, C-.C<
4 This 0ridge su0tractivel( decodes this address
=top level 0ridges onl(>
This 0ridge positivel( decodes this address
;itVW ConsumerF'roducer<
4IThis device consumes this resource
IThis device produces and consumes this resource
;(te * T(pe !pecific 5lags 5lags that are specific to each resource t(pe. The meaning of the
flags in this field depends on the value of the 3esource T(pe field
=see a0ove>.
;(te + Address space granularit(,
C$3A 0itsV9<W
A set 0it in this mask means that this 0it is decoded. All 0its less
significant than the most significant set 0it must 0e set. =in other
words, the value of the full Address !pace $ranularit( field =all 32
0its> must 0e a num0er =2
n
&4>.
;(te 9 Address space granularit(,
C$3A 0itsV4*<8W
;(te 8 Address space granularit(,
C$3A 0its V23<4+W
;(te 6 Address space granularit(,
C$3A 0its V34<2"W
;(te 4 Address range minimum,
CM%N 0its V9<W
5or 0ridges that translate addresses, this is the address space on the
secondar( side of the 0ridge.
;(te 44 Address range minimum,
CM%N 0its V4*<8W
;(te 42 Address range minimum,
CM%N 0its V23<4+W
;(te 43 Address range minimum,
CM%N 0its V34<2"W
;(te 4" Address range ma/imum,
CMAA 0its V9<W
5or 0ridges that translate addresses, this is the address space on the
secondar( side of the 0ridge.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3*2 Advanced Configuration and 'ower %nterface !pecification
3ffset 6ield 0a%e 5efinition
;(te 4* Address range ma/imum,
CMAA 0its V4*<8W
;(te 4+ Address range ma/imum,
CMAA 0its V23<4+W
;(te 49 Address range ma/imum,
CMAA 0its V34<2"W
;(te 48 Address Translation offset,
CT3A0its V9<W
5or 0ridges that translate addresses across the 0ridge, this is the
offset that must 0e added to the address on the secondar( side to
o0tain the address on the primar( side. Non&0ridge devices must
list for all Address Translation offset 0its.
;(te 46 Address Translation offset,
CT3A 0its V4*<8W
;(te 2 Address Translation offset,
CT3A 0its V23<4+W
;(te 24 Address Translation offset,
CT3A 0its V34<2"W
;(te 22 Address 1ength, C1.N, 0its
V9<W
;(te 23 Address 1ength, C1.N, 0its
V4*<8W
;(te 2" Address 1ength, C1.N, 0its
V23<4+W
;(te 2* Address 1ength, C1.N, 0its
V34<2"W
;(te 2+ 3esource !ource %nde/ =2ptional> 2nl( present if 3esource !ource =0elow> is present. This
field gives an inde/ to the specific resource descriptor that this
device consumes from in the current resource template for the
device o0#ect pointed to in 3esource !ource.
!tring 3esource !ource =2ptional> %f present, the device that uses this descriptor consumes
its resources from the resources produced 0( the named device
o0#ect. %f not present, the device consumes its resources out of a
glo0al pool.
%f not present, the device consumes this resource from its
hierarchical parent.
!ee -Word%2 =page 99+>, -WordMemor( =page 998> and A!1C-WordAddress!pace for a description of
the A!1 macro that creates a -W23- Address !pace descriptor
7.4.3.5.3 Word Address Space Descriptor
T)pe +' Large Ite% 0a%e $x/
The W23- address space descriptor is used to report resource usage in a 4+&0it address space =like
memor( and %F2>.
0oteH This descriptor is e/actl( the same as the -W23- descriptor specified in Ta0le +&29K the onl(
difference is that the address fields are 4+ 0its wide rather than 32 0its wide.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ 3*3
Ta!le --(+ :3"5 Address Space 5escriptor 5efinition
3ffset 6ield 0a%e 5efinition
;(te W23- Address !pace
-escriptor
Dalue\44; =T(pe \ 4, 1arge item name \ /8>
;(te 4 1ength, 0itsV9<W Daria0le< Dalue \ 43 =minimum>
;(te 2 1ength, 0itsV4*<8W Daria0le< Dalue \ =minimum>
;(te 3 3esource T(pe %ndicates which t(pe of resource this descriptor descri0es. -efined
values are<
Memor( range
4 %F2 range
2 ;us num0er range
3I464 $eser2ed
462&2**@ardware Dendor -efined
;(te " $eneral 5lags 5lags that are common to all resource t(pes<
;itsV9<"W $eser2ed =must 0e >
;itV3W Min Address 5i/ed, CMA5<
4 The specified ma/imum address is fi/ed
The specified ma/imum address is not fi/ed
and can 0e changed
;itV2W Ma/ Address 5i/ed,CM%5<
4 The specified minimum address is fi/ed
The specified minimum address is not fi/ed
and can 0e changed
;itV4W -ecode T(pe, C-.C<
4 This 0ridge su0tractivel( decodes this address
=top level 0ridges onl(>
This 0ridge positivel( decodes this address
;itVW ConsumerF'roducer<
4IThis device consumes this resource
IThis device produces and consumes this resource
;(te * T(pe !pecific 5lags 5lags that are specific to each resource t(pe. The meaning of the
flags in this field depends on the value of the 3esource T(pe field
=see a0ove>.
;(te + Address space granularit(,
C$3A 0itsV9<W
A set 0it in this mask means that this 0it is decoded. All 0its less
significant than the most significant set 0it must 0e set. =%n other
words, the value of the full Address !pace $ranularit( field =all 4+
0its> must 0e a num0er =2
n
&4>.
;(te 9 Address space granularit(,
C$3A 0itsV4*<8W
;(te 8 Address range minimum,
CM%N, 0its V9<W
5or 0ridges that translate addresses, this is the address space on the
secondar( side of the 0ridge.
;(te 6 Address range minimum,
CM%N, 0its V4*<8W
;(te 4 Address range ma/imum,
CMAA, 0its V9<W
5or 0ridges that translate addresses, this is the address space on the
secondar( side of the 0ridge.
;(te 44 Address range ma/imum,
CMAA, 0its V4*<8W
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3*" Advanced Configuration and 'ower %nterface !pecification
3ffset 6ield 0a%e 5efinition
;(te 42 Address Translation offset,
CT3A, 0its V9<W
5or 0ridges that translate addresses across the 0ridge, this is the
offset that must 0e added to the address on the secondar( side to
o0tain the address on the primar( side. Non&0ridge devices must list
for all Address Translation offset 0its.
;(te 43 Address Translation offset,
CT3A, 0its V4*<8W
;(te 4" Address 1ength, C1.N, 0its
V9<W
;(te 4* Address 1ength, C1.N, 0its
V4*<8W
;(te 4+ 3esource !ource %nde/ =2ptional> 2nl( present if 3esource !ource =0elow> is present. This
field gives an inde/ to the specific resource descriptor that this
device consumes from in the current resource template for the
device o0#ect pointed to in 3esource !ource.
!tring 3esource !ource =2ptional> %f present, the device that uses this descriptor consumes
its resources from the resources produced 0( the named device
o0#ect. %f not present, the device consumes its resources out of a
glo0al pool. %f not present, the device consumes this resource from
its hierarchical parent.
!ee Word%2 =page 8"3>, Word;usNum0er =page 8"2> and A!1CWordAddress!pace for a description of the
A!1 macros that create a Word address descriptor.
7.4.3.5.4 Extended Address Space Descriptor
T)pe +' Large Ite% 0a%e $x<
The ./tended Address !pace descriptor is used to report resource usage in the address space =like memor(
and %F2>.
Ta!le --(& 1xtended Address Space 5escriptor 5efinition
3ffset 6ield 0a%e 5efinition
;(te ./tended Address !pace
-escriptor
Dalue\4444; =T(pe \ 4, 1arge item name \ /;>
;(te 4 1ength, 0itsV9<W Daria0le< Dalue \ *3
;(te 2 1ength, 0itsV4*<8W Daria0le< Dalue \
;(te 3 3esource T(pe %ndicates which t(pe of resource this descriptor descri0es. -efined
values are<
Memor( range
4 %F2 range
2 ;us num0er range
3I464 $eser2ed
462&2**@ardware Dendor -efined
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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3ffset 6ield 0a%e 5efinition
;(te " $eneral 5lags 5lags that are common to all resource t(pes<
;itsV9<"W $eser2ed =must 0e >
;itV3W Min Address 5i/ed, CMA5<
4 The specified ma/imum address is fi/ed
The specified ma/imum address is not fi/ed
and can 0e changed
;itV2W Ma/ Address 5i/ed,CM%5<
4 The specified minimum address is fi/ed
The specified minimum address is not fi/ed
and can 0e changed
;itV4W -ecode T(pe, C-.C<
4 This 0ridge su0tractivel( decodes this address
=top level 0ridges onl(>
This 0ridge positivel( decodes this address
;itVW ConsumerF'roducer<
4IThis device consumes this resource
IThis device produces and consumes this resource
;(te * T(pe !pecific 5lags 5lags that are specific to each resource t(pe. The meaning of the
flags in this field depends on the value of the 3esource T(pe field
=see a0ove>. 5or the Memor( 3esource T(pe, the definition is
defined in sectionTref). 5or other 3esource T(pes, refer to the
e/isting definitions for the Address !pace -escriptors.
;(te + 3evision %- %ndicates the revision of the ./tended Address !pace descriptor. 5or
AC'% 3., this value is 4.
;(te 9 3eserved
Ta!le --(& 1xtended Address Space 5escriptor 5efinition (continued)
3ffset 6ield 0a%e 5efinition
;(te 8 Address space granularit(,
C$3A 0itsV9<W
A set 0it in this mask means that this 0it is decoded. All 0its less
significant than the most significant set 0it must 0e set. That is, the
value of the full Address !pace $ranularit( field =all 32 0its> must
0e a num0er =2
n
&4>.
;(te 6 Address space granularit(,
C$3A 0itsV4*<8W
;(te 4 Address space granularit(,
C$3A 0itsV23<4+W
;(te 44 Address space granularit(,
C$3A 0itsV34<2"W
;(te 42 Address space granularit(,
C$3A 0itsV36<32W
;(te 43 Address space granularit(,
C$3A 0itsV"9<"W
;(te 4" Address space granularit(,
C$3A 0itsV**<"8W
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3*+ Advanced Configuration and 'ower %nterface !pecification
3ffset 6ield 0a%e 5efinition
;(te 4* Address space granularit(,
C$3A 0itsV+3<*+W
;(te 4+ Address range minimum,
CM%N 0itsV9<W
5or 0ridges that translate addresses, this is the address space on the
secondar( side of the 0ridge.
;(te 49 Address range minimum,
CM%N 0itsV4*<8W
;(te 48 Address range minimum,
CM%N 0itsV23<4+W
;(te 46 Address range minimum,
CM%N 0itsV34<2"W
;(te 2 Address range minimum,
CM%N 0itsV36<32W
;(te 24 Address range minimum,
CM%N 0itsV"9<"W
Ta!le --(& 1xtended Address Space 5escriptor 5efinition (continued)
3ffset 6ield 0a%e 5efinition
;(te 22 Address range minimum,
CM%N 0itsV**<"8W
;(te 23 Address range minimum,
CM%N 0itsV+3<*+W
;(te 2" Address range ma/imum,
CMAA 0itsV9<W
5or 0ridges that translate addresses, this is the address space on the
secondar( side of the 0ridge.
;(te 2* Address range ma/imum,
CMAA 0itsV4*<8W
;(te 2+ Address range ma/imum,
CMAA 0itsV23<4+W
;(te 29 Address range ma/imum,
CMAA 0itsV34<2"W
;(te 28 Address range ma/imum,
CMAA 0itsV36<32W
5or 0ridges that translate addresses, this is the address space on the
secondar( side of the 0ridge.
;(te 26 Address range ma/imum,
CMAA 0itsV"9<"W
;(te 3 Address range ma/imum,
CMAA 0itsV**<"8W
;(te 34 Address range ma/imum,
CMAA 0itsV+3<*+W
;(te 32 Address Translation offset,
CT3A 0itsV9<W
5or 0ridges that translate addresses across the 0ridge, this is the
offset that must 0e added to the address on the secondar( side to
o0tain the address on the primar( side. Non&0ridge devices must list
for all Address Translation offset 0its.
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3ffset 6ield 0a%e 5efinition
;(te 33 Address Translation offset,
CT3A 0itsV4*<8W
;(te 3" Address Translation offset,
CT3A 0itsV23<4+W
;(te 3* Address Translation offset,
CT3A 0itsV34<2"W
Ta!le --(& 1xtended Address Space 5escriptor 5efinition (continued)
3ffset 6ield 0a%e 5efinition
;(te 3+ Address Translation offset, CT3A
0itsV36<32W
;(te 39 Address Translation offset, CT3A
0itsV"9<"W
;(te 38 Address Translation offset, CT3A
0itsV**<"8W
;(te 36 Address Translation offset, CT3A
0itsV+3<*+W
;(te " Address length, C1.N 0itsV9<W
;(te "4 Address length, C1.N, 0itsV4*<8W
;(te "2 Address length, C1.N 0itsV23<4+W
;(te "3 Address length, C1.N 0itsV34<2"W
;(te "" Address length, C1.N 0itsV36<32W
;(te "* Address length, C1.N 0itsV"9<"W
;(te "+ Address length, C1.N 0itsV**<"8W
;(te "9 Address length, C1.N 0itsV+3<*+W
;(te "8 T(pe !pecific Attri0ute, CATT
0itsV9<W
Attri0utes that are specific to each resource t(pe. The
meaning of the attri0utes in this field depends on the value of
the 3esource T(pe field =see a0ove>. 5or the Memor(
3esource T(pe, the definition is defined section Tref). 5or
other 3esource T(pes, this field is reserved to .
;(te "6 T(pe !pecific Attri0ute, CATT
0itsV4*<8W
;(te * T(pe !pecific Attri0ute, CATT
0itsV23<4+W
;(te *4 T(pe !pecific Attri0ute, CATT
0itsV34<2"W
;(te *2 T(pe !pecific Attri0ute, CATT
0itsV36<32W
;(te *3 T(pe !pecific Attri0ute, CATT
0itsV"9<"W
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3*8 Advanced Configuration and 'ower %nterface !pecification
3ffset 6ield 0a%e 5efinition
;(te *" T(pe !pecific Attri0ute, CATT
0itsV**<"8W
;(te ** T(pe !pecific Attri0ute, CATT
0itsV+3<*+W
!ee section 49.*."4, J./tended!pace =./tended Address !pace 3esource -escriptor Macro>,L for a
description of the A!1 macro that creates an ./tended Address !pace descriptor.
7.4.3.5.4.1 Type Specifc Attributes
The meaning of the T(pe !pecific Attri0utes field of the ./tended Address !pace -escriptor depends on
the value of the 3esource T(pe field in the descriptor. When 3esource T(pe \ =memor( resource>, the
T(pe !pecific Attri0utes field values are defined as follows<
FF These attri0utes can 0e d23edd together as needed.
Ydefine AC'%CM.M23SC,C /4
Ydefine AC'%CM.M23SCWC /2
Ydefine AC'%CM.M23SCWT /"
Ydefine AC'%CM.M23SCW; /8
Ydefine AC'%CM.M23SC,C. /4
Ydefine AC'%CM.M23SCND /8
AC'%CM.M23SC,C Memor( cachea0ilit( attri0ute< The memor( region supports 0eing configured as
not cachea0le.
AC'%CM.M23SCWC Memor( cachea0ilit( attri0ute< The memor( region supports 0eing configured as
write com0ining.
AC'%CM.M23SCWT Memor( cachea0ilit( attri0ute< The memor( region supports 0eing configured as
cachea0le with a dwrite through dpolic(. Writes that hit in the cache will also 0e written to main memor(.
AC'%CM.M23SCW; Memor( cachea0ilit( attri0ute< The memor( region supports 0eing configured as
cachea0le with a dwrite 0ack dpolic(. 3eads and writes that hit in the cache do not propagate to main
memor(. -irt( data is written 0ack to main memor( when a new cache line is allocated.
AC'%CM.M23SC,C. Memor( cachea0ilit( attri0ute< The memor( region supports 0eing configured as
not cachea0le, e/ported, and supports the dfetch and add dsemaphore mechanism.
AC'%CM.M23SCND Memor( non&volatile attri0ute< The memor( region is non&volatile. ,se of memor(
with this attri0ute is su0#ect to characteriHation.
Notice< These 0its are defined so as to match the .5% definition when applica0le.
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7.4.3.5.5 Resource Type Specifc Flags
The meaning of the flags in the T(pe !pecific 5lags field of the Address !pace -escriptors depends on the
value of the 3esource T(pe field in the descriptor. The flags for each resource t(pe are defined in the
following ta0les<
Ta!le --(# Me%or) "esource 6lag >"esource T)pe P $? 5efinitions
<its Meaning
;itsV9<+W 3eserved =must 0e >
;itV*W Memor( to %F2 Translation, CTT'
4 T(peTranslation< This resource, which is memor( on the secondar( side of the
0ridge, is %F2 on the primar( side of the 0ridge.
T(pe!tatic< This resource, which is memor( on the secondar( side of the 0ridge, is
also memor( on the primar( side of the 0ridge.
;itsV"<3W Memor( attri0utes, CMT'. These 0its are onl( defined if this memor( resource descri0es
s(stem 3AM. 5or a definition of the la0els descri0ed here, see section 4*, J!(stem Address
Map %nterfaces.L
Address3angeMemor(
4 Address3ange3eserved
2 Address3angeAC'%
3 Address3angeND!
;itsV2<4W Memor( attri0utes, CM.M
The memor( is non&cachea0le.
4 The memor( is cachea0le.
2 The memor( is cachea0le and supports write com0ining.
3 The memor( is cachea0le and prefetcha0le.
=Notice< 2!'M ignores this field in the ./tended address space descriptor. %nstead it uses the
T(pe !pecific Attri0utes field to determine memor( attri0utes>
;itVW Write status, C3W
4 This memor( range is read&write.
This memor( range is read&onl(.
Ta!le --(( I@3 "esource 6lag >"esource T)pe P +? 5efinitions
<its Meaning
;itsV9<+W 3eserved =must 0e >
;itV*W !parse Translation, CT3!. This 0it is onl( meaningful if ;itV"W is set.
4 !parseTranslation< The primar(&side memor( address of an( specific %F2 port within
the secondar(&side range can 0e found using the following function.
addre22 L (((port V (-555c) ?? 4() UU (port V (-555)) D _<R&
%n the address used to access the %F2 port, 0itsV44<2W must 0e identical to
0itsV24<42W, this gives four 0(tes of %F2 ports on each " E; page.
-enseTranslation< The primar(&side memor( address of an( specific %F2 port within
the secondar(&side range can 0e found using the following function.
addre22 L port D _<R&
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3+ Advanced Configuration and 'ower %nterface !pecification
<its Meaning
;itV"W %F2 to Memor( Translation, CTT'
4 T(peTranslation< This resource, which is %F2 on the secondar( side of the 0ridge, is
memor( on the primar( side of the 0ridge.
T(pe!tatic< This resource, which is %F2 on the secondar( side of the 0ridge, is also %F2
on the primar( side of the 0ridge.
;itV3<2W $eser2ed =must 0e >
;itV4<W C3N$
3 Memor( window covers the entire range
2 %!A3anges2nl(. This flag is for 0ridges on s(stems with multiple 0ridges. !etting this
0it means the memor( window specified in this descriptor is limited to the %!A %F2
addresses that fall within the specified window. The %!A %F2 ranges are< n&n55,
n"&n"55, n8&n855, nC&nC55. This 0it can onl( 0e set for 0ridges entirel(
configured through AC'% namespace.
4 Non%!A3anges2nl(. This flag is for 0ridges on s(stems with multiple 0ridges. !etting
this 0it means the memor( window specified in this descriptor is limited to the non&
%!A %F2 addresses that fall within the specified window. The non&%!A %F2 ranges are<
n4&n355, n*&n955, n6&n;55, n-&n555. This 0it can onl( 0e set for 0ridges
entirel( configured through AC'% namespace.
3eserved
Ta!le --(A <us 0u%!er "ange "esource 6lag >"esource T)pe P &? 5efinitions
<its Meaning
;itV9<W $eser2ed =must 0e >
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7.4.3.6
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3+2 Advanced Configuration and 'ower %nterface !pecification
Extended Interrupt Descriptor
T)pe +' Large Ite% 0a%e $x,
The ./tended %nterrupt -escriptor is necessar( to descri0e interrupt settings and possi0ilities for s(stems
that support interrupts a0ove 4*.
To specif( multiple interrupt num0ers, this descriptor allows vendors to list an arra( of possi0le interrupt
num0ers, an( one of which can 0e used.
Ta!le --(- 1xtended Interrupt 5escriptor 5efinition
3ffset 6ield 0a%e 5efinition
;(te ./tended %nterrupt
-escriptor
Dalue\444; =T(pe \ 4, 1arge item name \ /6>
;(te 4 1ength, 0itsV9<W Daria0le< Dalue \ + =minimum>
;(te 2 1ength, 0itsV4*<8W Daria0le< Dalue \ =minimum>
;(te 3 %nterrupt Dector
5lags
%nterrupt Dector %nformation.
;itV9<"W $eser2ed =must 0e >
;itV3W %nterrupt is sharea0le, DSH"
;itV2W %nterrupt 'olarit(, DLL
Active&@igh< This interrupt is sampled
when the signal is high, or true.
4 Active&1ow< This interrupt is sampled
when the signal is low, or false.
;itV4W %nterrupt Mode, DH1
1evel&Triggered< %nterrupt is triggered in response
to the signal 0eing in either a high or low state.
4 .dge&Triggered< This interrupt is
triggered in response to a change in signal
state, either high to low or low to high.
;itVW ConsumerF'roducer<
4IThis device consumes this resource
IThis device produces and consumes this resource
;(te " %nterrupt ta0le
length
%ndicates the num0er of interrupt num0ers that follow. When this
descriptor is returned from CC3!, or when 2!'M passes this descriptor
to C!3!, this field must 0e set to 4.
;(te
"nZ*
%nterrupt Num0er,
C%NT 0its V9<W
%nterrupt num0er
;(te
"nZ+
%nterrupt Num0er,
C%NT 0its V4*<8W
;(te
"nZ9
%nterrupt Num0er,
C%NT 0its V23<4+W
;(te
"nZ8
%nterrupt Num0er,
C%NT 0its V34<2"W
N N Additional interrupt num0ers
;(te x 3esource !ource
%nde/
=2ptional> 2nl( present if 3esource !ource =0elow> is present. This field
gives an inde/ to the specific resource descriptor that this device
consumes from in the current resource template for the device o0#ect
pointed to in 3esource !ource.
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3ffset 6ield 0a%e 5efinition
!tring 3esource !ource =2ptional> %f present, the device that uses this descriptor consumes its
resources from the resources produces 0( the named device o0#ect. %f not
present, the device consumes its resources out of a glo0al pool.
%f not present, the device consumes this resource from its hierarchical
parent.
0oteH 1ow true, level sensitive interrupts ma( 0e electricall( shared, the process of how this might work is
0e(ond the scope of this specification.
%f the 2! is running using the 82*6 interrupt model, onl( interrupt num0er values of &4* will 0e used, and
interrupt num0ers greater than 4* will 0e ignored.
!ee %nterrupt =page 8"> for a description of the A!1 macro that creates an ./tended %nterrupt descriptor.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
3+" Advanced Configuration and 'ower %nterface !pecification
7.4.3.7
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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Generic Register Descriptor
T)pe +' Large Ite% 0a%e $x&
The generic register descriptor descri0es the location of a fi/ed width register within an( of the AC'%&
defined address spaces.
Ta!le --(. ;eneric "egister 5escriptor 5efinition
3ffset 6ield 0a%e' ASL 6ield 0a%e 5efinition
;(te $eneric register descriptor Dalue \ 44; =T(pe \ 4, 1arge item name \ /2>
;(te 4 1ength, 0itsV9<W Dalue \ 44; =42>
;(te 2 1ength, 0itsV4*<8W Dalue \ ; =>
;(te 3 Address !pace %-, CA!% The address space where the data structure or register
e/ists. -efined values are<
/ !(stem Memor(
/4 !(stem %F2
/2 'C% Configuration !pace
/3 .m0edded Controller
/" !M;us
/95 5unctional 5i/ed @ardware
;(te " 3egister ;it Width, C3;W %ndicates the register width in 0its.
;(te * 3egister ;it 2ffset, C3;2 %ndicates the offset to the start of the register in 0its from
the 3egister Address.
;(te + Address !iHe, CA!?
!pecifies access siHe.
&,ndefined =legac( reasons>
4&;(te access
2&Word access
3&-word access
"&Gword access
;(te 9 3egister Address, CA-3 0itsV9<W 3egister Address
;(te 8 3egister Address, CA-3 0itsV4*<8W
;(te 6 3egister Address, CA-3 0itsV23<4+W
;(te 4 3egister Address, CA-3 0itsV34<2"W
;(te 44 3egister Address, CA-3 0itsV36<32W
;(te 42 3egister Address, CA-3 0itsV"9<"W
;(te 43 3egister Address, CA-3 0itsV**<"8W
;(te 4" 3egister Address, CA-3 0itsV+3<*+W
!ee 3egister =page 828> for a description of the A!1 macro that creates a $eneric 3egister resource
descriptor.
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3++ Advanced Configuration and 'ower %nterface !pecification
7.5 Other Objects and Control Methods
Ta!le --(/ 3ther 3!Cects and Methods
3!Cect 5escription
C%N% -evice initialiHation method that is run shortl( after AC'% has 0een ena0led.
C-CE %ndicates that the device is a docking station.
C;-N Correlates a docking station 0etween AC'% and legac( interfaces.
C3.$ Notifies AM1 code of a change in the availa0ilit( of an operation region.
C;;N 'C% 0us num0er set up 0( the ;%2!.
C!.$ %ndicates a 0us segment location.
C$1E %ndicates the $lo0al 1ock must 0e ac:uired when accessing a device.
7.5.1 _INI (Init)
C%N% is a device initialiHation o0#ect that performs device specific initialiHation. This control method is
located under a device o0#ect and is run onl( when 2!'M loads a description ta0le. There are restrictions
related to when this method is called and governing writing code for this method. The C%N% method must
onl( access 2peration 3egions that have 0een indicated to availa0le as defined 0( the C3.$ method. The
C3.$ method is descri0ed in section +.*.", JC3.$ =3egion>.L This control method is run 0efore CA-3,
CC%-, C@%-, C!,N, and C,%- are run.
%f the C!TA method indicates that the device is present, 2!'M will evaluate the CC%N% for the device =if the
C%N% method e/ists> and will e/amine each of the children of the device for C%N% methods. %f the C!TA
method indicates that the device is not present, 2!'M will not run the C%N% and will not e/amine the
children of the device for C%N% methods. %f the device 0ecomes present after the ta0le has alread( 0een
loaded, 2!'M will not evaluate the C%N% method, nor e/amine the children for C%N% methods.
The C%N% control method is generall( used to switch devices out of a legac( operating mode. 5or e/ample,
;%2!es often configure Card;us controllers in a legac( mode to support legac( operating s(stems. ;efore
enumerating the device with an AC'% operating s(stem, the Card;us controllers must 0e initialiHed to
Card;us mode. 5or such s(stems, the vendor can include an C%N% control method under the Card;us
controller to switch the device into Card;us mode.
%n addition to device initialiHation, 2!'M unconditionall( evaluates an C%N% o0#ect under the BC!;
namespace, if present, at the 0eginning of namespace initialiHation.
7.5.2 _DCK (Dock)
This control method is located in the device o0#ect that represents the docking station =that is, the device
o0#ect with all the C.7/ control methods for the docking station>. The presence of C-CE indicates to the
2! that the device is reall( a docking station.
C-CE also controls the isolation logic on the docking connector. This allows an 2! to prepare for docking
0efore the 0us is activated and devices appear on the 0us.
Arguments<
Arg
4I-ock =that is, remove isolation from connector>
I,ndock =isolate from connector>
3eturn Code<
4 if successful, if failed.
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0oteH When C-CE is called with , 2!'M will ignore the return value. The C!TA o0#ect that follows the
C.7/ control method will notif( whether or not the porta0le has 0een e#ected.
7.5.3 _BDN (BIOS Dock Name)
C;-N is used to correlate a docking station reported via AC'% and the same docking station reported via
legac( interfaces. %t is primaril( used for upgrading over non&AC'% environments.
C;-N must appear under a device o0#ect that represents the dock, that is, the device o0#ect with C.#/
methods. This o0#ect must return a -W23- that is the .%!A&packed -ock%- returned 0( the 'lug and
'la( ;%2! 5unction * =$et -ocking !tation %dentifier> for a dock.
0oteH %f the machine does not support 'N';%2!, this o0#ect is not re:uired.
7.5.4 _REG (Region)
The 2! runs C3.$ control methods to inform AM1 code of a change in the availa0ilit( of an operation
region. When an operation region handler is unavaila0le, AM1 cannot access data fields in that region.
=2peration region writes will 0e ignored and reads will return indeterminate data.>.
./cept for the cases shown 0elow, control methods must assume all operation regions inaccessi0le until the
C3.$=3egion!pace, 4> method is e/ecuted. 2nce C3.$ has 0een e/ecuted for a particular operation
region, indicating that the operation region handler is read(, a control method can access fields in the
operation region. Conversel(, control methods must not access fields in operation regions when C3.$
method e/ecution has not indicated that the operation region handler is read(.
5or e/ample, until the .m0edded Controller driver is read(, the control methods cannot access the
.m0edded Controller. 2nce 2!'M has run C3.$=.m0eddedControl, 4>, the control methods can then
access operation regions in .m0edded Controller address space. 5urthermore, if 2!'M e/ecutes
C3.$=.m0eddedControl, >, control methods must stop accessing operation regions in the .m0edded
Controller address space.
The e/ceptions for this rule are<
4. 2!'M must guarantee that the following operation regions must alwa(s 0e accessi0le<
'C%CConfig operation regions on a 'C% root 0us containing a C;;N o0#ect.
%F2 operation regions.
Memor( operation regions when accessing memor( returned 0( the !(stem Address Map
reporting interfaces.
2. 2!'M must make .m0edded Controller operation regions, accessed via the .m0edded
Controllers descri0ed in .C-T, availa0le 0efore e/ecuting an( control method. These operation
regions ma( 0ecome inaccessi0le after 2!'M runs C3.$=.m0eddedControl, >.
'lace C3.$ in the same scope as operation region declarations. The 2! will run the C3.$ in a given scope
when the operation regions declared in that scope are availa0le for use.
5or e/ample<
Scope(\_SB.P)#()
0perationRe,ion(0PR4$ P)#_)onfi,$ ...)
;ethod(_R%:$ 3) .../ // 0SP; e-ecute2 thi2 when P)#0 operation re,ion handler
// 2tatu2 chan,e2
Device(P)#4)
;ethod(_R%:$ 3) .../
Device(%<"()
0perationRe,ion(0PR3$ P)#_)onfi,$ ...)
;ethod(_R%:$3) .../
/
/
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3+8 Advanced Configuration and 'ower %nterface !pecification
Device(#S&()
0perationRe,ion(0PRF$ #/0$ ...)
;ethod(_R%:$ 3) .../ // 0SP; e-ecute2 thi2 when #S&0 operation re,ion handler
// 2tatu2 chan,e2
Device(%)()
!ame(_"#D$ %#S&#D(PP!P()(HP))
0perationRe,ion(0PR.$ %)$ ...)
;ethod(_R%:$ 3) .../ // 0SP; e-ecute2 thi2 when %) operation re,ion
// handler 2tatu2 chan,e2
/
/
/
When the 'C% operation region handler is read(, 2!'M will run the C3.$ method declared in 'C% scope
to indicate that 'C% Config space operation region access is availa0le within the 'C% scope =in other
words, 2'34 access is allowed>. When the %!A operation handler is read(, 2!'M will run the C3.$
method in the %!A scope to indicate that the %F2 space operation region access is availa0le within that
scope =in other words, 2'33 access is allowed>. 5inall(, when the .m0edded Controller operation region
handler is read(, 2!'M will run the C3.$ method in the .C scope to indicate that .C space operation
region access is availa0le within the .C scope =in other words, 2'3" access is allowed>. %t should 0e
noted that 'C% Config !pace 2peration 3egions are read( as soon the host controller or 0ridge controller
has 0een programmed with a 0us num0er. 'C%4Ms C3.$ method would not 0e run until the 'C%&'C% 0ridge
has 0een properl( configured. At the same time, the 2! will also run .T@Ms C3.$ method since its 'C%
Config !pace would 0e also availa0le. The 2! will again run .T@Ms C3.$ method when the .T@
device is started. Also, when the host controller or 0ridge controller is turned off or disa0led, 'C% Config
!pace 2peration 3egions for child devices are no longer availa0le. As such, .T@Ms C3.$ method will 0e
run when it is turned off and will again 0e run when 'C%4 is turned off.
0ote< The 2! onl( runs C3.$ methods that appear in the same scope as operation region declarations that
use the operation region t(pe that has #ust 0een made availa0le. 5or e/ample, C3.$ in the .C device
would not 0e run when the 'C% 0us driver is loaded since the operation regions declared under .C do not
use an( of the operation region t(pes made availa0le 0( the 'C% driver =namel(, config space, %F2, and
memor(>.
Arguments<
Arg< %nteger< 2peration region space<
!(stemMemor(
4 !(stem%2
2 'C%CConfig
3 .m0edded Controller
" !M;us
* CM2!
+ 'C%;A3Target
/8&/55 2.M region space handler
Arg4< %nteger< 4 for connecting the handler, for disconnecting the handler
7.5.5 _BBN (Base Bus Number)
5or multi&root 'C% machines, C;;N is the 'C% 0us num0er that the ;%2! assigns. This is needed to access
a 'C%CConfig operation region for the specific 0us. The C;;N o0#ect must 0e uni:ue for ever( host 0ridge
within a segment since it is the 'C% 0us num0er.
7.5.6 _SEG (Segment)
The optional C!.$ o0#ect evaluates to an integer that descri0es the 'C% !egment $roup =see 'C% 5irmware
!pecification v3.>. %f C!.$ does not e/ist, 2!'M assumes that all 'C% 0us segments are in 'C% !egment
$roup .
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'C% !egment $roup is purel( a software concept managed 0( s(stem firmware and used 0( 2!'M. %t is a
logical collection of 'C% 0uses =or 0us segments>. There is no tie to an( ph(sical entities. %t is a wa( to
logicall( group the 'C% 0us segments and 'C% ./press @ierarchies. C!.$ is a level higher than C;;N.
'C% !egment $roup supports more than 2*+ 0uses in a s(stem 0( allowing the reuse of the 'C% 0us
num0ers. Within each 'C% !egment $roup, the 0us num0ers for the 'C% 0uses must 0e uni:ue. 'C% 0uses
in different 'C% !egment $roup are permitted to have the same 0us num0er.
A 'C% !egment $roup contains one or more 'C% host 0ridges.
The lower 4+ 0its of C!.$ returned integer is the 'C% !egment $roup num0er. 2ther 0its are reserved.
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7.5.6.1
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Example
Device(!D() // thi2 i2 a node (
!ame(_"#D$ '&)P#(((.*)
// Return2 the P)urrent Re2ource2P
!ame(_)RS$
Re2ource<emplate()
Y
/
)
Device(P)#()
!ame(_"#D$ %#S&#D('P!P(&(F*))
!ame(_&DR$ (-(((((((()
!ame(_S%:$ () // <he bu2e2 below the ho2t brid,e belon, to P)# 2e,ment (
Y
!ame(_BB!$ ()
Y
/
Device(P)#4)
Y
!ame(_S%:$ () // <he bu2e2 below the ho2t brid,e belon, to P)# 2e,ment (
Y
!ame(_BB!$ 4I)
Y
/
Y
/
Device(!D4) // thi2 i2 a node 4
!ame(_"#D$ '&)P#(((.*)
// Return2 the P)urrent Re2ource2P
!ame(_)RS$
Re2ource<emplate()
Y
/
)
Device(P)#()
!ame(_"#D$ %#S&#D('P!P(&(F*))
!ame(_&DR$ (-(((((((()
!ame(_S%:$ 4) // <he bu2e2 below the ho2t brid,e belon, to P)# 2e,ment 4
Y
!ame(_BB!$ ()
Y
/
Device(P)#4)
Y
!ame(_S%:$ 4) // <he bu2e2 below the ho2t brid,e belon, to P)# 2e,ment 4
Y
!ame(_BB!$ 4I)
Y
/
/
7.5.7 _GLK (Global Lock)
This optional named o0#ect is located in a device o0#ect. This o0#ect returns a value that indicates to an(
entit( that accesses this device =in other words, 2!'M or an( device driver> whether the $lo0al 1ock must
0e ac:uired when accessing the device. 2!&0ased device accesses must 0e performed while in ac:uisition
of the $lo0al 1ock when potentiall( contentious accesses to device resources are performed 0( non&2!
code, such as !(stem Management Mode =!MM>&0ased code in %ntel architecture&0ased s(stems.
An e/ample of this device resource contention is a device driver for an !M;us&0ased device contending
with !MM&0ased code for access to the .m0edded Controller, !M;&@C, and !M;us target device. %n this
case, the device driver must ac:uire and release the $lo0al 1ock when accessing the device to avoid
resource contention with !MM&0ased code that accesses an( of the listed resources.
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3eturn Codes<
4 $lo0al 1ock re:uired, $lo0al 1ock not re:uired
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39" Advanced Configuration and 'ower %nterface !pecification
8 Power and Performance Management
This section specifies the device power management o0#ects and s(stem power management o0#ects.
2!'M uses these o0#ects to manage the platform 0( achieving a desira0le 0alance 0etween performance
and energ( conservation goals.
-evice performance states ='/ states> are power consumption and capa0ilit( states within the active =->
device power state. 'erformance states allow 2!'M to make tradeoffs 0etween performance and energ(
conservation. -evice performance states have the greatest impact when the implementation is such that the
states invoke different device efficienc( levels as opposed to a linear scaling of performance and energ(
consumption. !ince performance state transitions occur in the active device states, care must 0e taken to
ensure that performance state transitions do not adversel( impact the s(stem.
-evice performance state o0#ects, when necessar(, are defined on a per device class 0asis as descri0ed in
the device class specifications =!ee Appendi/ A>.
The s(stem state indicator o0#ects are also specified in this section.
8.1 Declaring a Power Resource Object
An A!1 Power"esource statement is used to declare a Power"esource o0#ect. A 'ower 3esource o0#ect
refers to a software&controlla0le power plane, clock plane, or other resource upon which an integrated AC'%
power&managed device might rel(. 'ower resource o0#ects can appear wherever is convenient in
namespace.
The s(nta/ of a Power"esource statement is<
Power"esource >reso'rcename. systemle2el. reso'rceorder? Q0a%edListR
where the systemle2el parameter is a num0er and the reso'rceorder parameter is a numeric constant =a
W23->. 5or a formal definition of the Power"esource statement s(nta/, see section 49, JAC'% !ource
1anguage 3eference.L
Systemle2el is the lowest power s(stem sleep level 2!'M must maintain to keep this power resource on =
e:uates to !, 4 e:uates to !4, and so on>.
.ach power&managed AC'% device lists the resources it re:uires for its supported power levels. 2!'M
multiple/es this information from all devices and then ena0les and disa0les the re:uired 'ower 3esources
accordingl(. The reso'rceorder field in the 'ower 3esource o0#ect is a uni:ue value per 'ower 3esource,
and it provides the s(stem with the order in which 'ower 3esources must 0e ena0led or disa0led. 'ower
3esources are ena0led from low values to high values and are disa0led from high values to low values. The
operating software ena0les or disa0les all affected 'ower 3esources in an( one reso'rceorder level at a
time 0efore moving on to the ne/t ordered level. 'utting 'ower 3esources in different order levels provides
power se:uencing and serialiHation where re:uired.
A 'ower 3esource can have named o0#ects under its Namespace location. 5or a description of the AC'%&
defined named o0#ects for a 'ower 3esource, see section 8.2, J-evice 'ower Management 20#ects.L
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The following 0lock of A!1 sample code shows a use of Power"esource.
PowerRe2ource(P#D%$ ($ ()
;ethod(_S<&)
Return (Ror (:#0.#D%#$ 0ne$ 7ero)) // inver2e of i2olation
/
;ethod(_0!)
Store (0ne$ :#0.#D%P) // a22ert power
Sleep (4() // wait 4(m2
Store (0ne$ :#0.#D%R) // deEa22ert re2etQ
Stall (4() // wait 4(u2
Store (7ero$ :#0.#D%#) // deEa22ert i2olation
/
;ethod(_055)
Store (0ne$ :#0.#D%#) // a22ert i2olation
Store (7ero$ :#0.#D%R) // a22ert re2etQ
Store (7ero$ :#0.#D%P) // deEa22ert power
/
/
8.1.1 Defned Child Objects for a Power Resource
.ach power resource o0#ect is re:uired to have the following control methods to allow 0asic control of each
power resource. As 2!'M changes the state of device o0#ects in the s(stem, the power resources that are
needed will also change causing 2!'M to turn power resources on and off. To determine the initial power
resource settings the C!TA method can 0e used.
Ta!le .-+ Power "esource Child 3!Cects
3!Cect 5escription
C255 !et the resource off.
C2N !et the resource on.
C!TA 20#ect that evaluates to the current on or off state of the 'ower 3esource. I255, 4I2N
8.1.2 _OFF
This power resource control method puts the power resource into the 255 state. The control method does
not complete until the power resource is off. 2!'M onl( turns on or off one resource at a time, so the AM1
code can o0tain the proper timing se:uencing 0( using !tall or !leep within the 2N =or 255> method to
cause the proper se:uencing dela(s 0etween operations on power resources.
Arguments<
None
3esult Code<
None
8.1.3 _ON
This power resource control method puts the power resource into the 2N state. The control method does
not complete until the power resource is on. 2!'M onl( turns on or off one resource at a time, so the AM1
code can o0tain the proper timing se:uencing 0( using !tall or !leep within the 2N =or 255> method to
cause the proper se:uencing dela(s 0etween operations on power resources.
Arguments<
None
3esult Code<
None
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8.1.4 _STA (Status)
3eturns the current 2N or 255 status for the power resource.
Arguments<
None
3esult Code<
indicates the power resource is currentl( off.
4 indicates the power resource is currentl( on.
8.2 Device Power Management Objects
5or a device that is power&managed using AC'%, a -efinition ;lock contains one or more of the o0#ects
found in the ta0le 0elow. 'ower management of a device is done using two different paradigms<
'ower 3esource control
-evice&specific control
'ower 3esources are resources that could 0e shared amongst multiple devices. The operating software will
automaticall( handle control of these devices 0( determining which particular 'ower 3esources need to 0e
in the 2N state at an( given time. This determination is made 0( considering the state of all devices
connected to a 'ower 3esource.
;( definition, a device that is 255 does not have an( power resource or s(stem power state re:uirements.
Therefore, device o0#ects do not list power resources for the 255 power state.
5or 2!'M to put the device in the -3 state, the following must occur<
All 'ower 3esources no longer referenced 0( an( device in the s(stem must 0e in the 255 state.
%f present, the C'!3 control method is e/ecuted to set the device into the -3 device state.
The onl( transition allowed from the -3 device state is to the - device state.
5or man( devices the 'ower 3esource control is all that is re:uiredK however, device o0#ects ma( include
their own device&specific control method.
These two t(pes of power management controls =through 'ower 3esources and through specific devices>
can 0e applied in com0ination or individuall( as re:uired.
5or s(stems that do not control device power states through power plane management, 0ut whose devices
support multiple -&states, more information is re:uired 0( the 2! to determine the !&state to -&state
mapping for the device. The AC'% ;%2! can give this information to 2!'M 0( wa( of the C!x- methods.
These methods tell 2!'M for !&state JxL, the highest -&state supported 0( the device is Jy.L 2!'M is
allowed to pick a lower -&state for a given !&state, 0ut 2!'M is not allowed to e/ceed the given -&state.
5urther rules that appl( to device power management o0#ects are<
5or a given !&state, a device cannot 0e in a higher -&state than its parent device.
%f there e/ists an AC'% 20#ect to turn on a device =either through C'!x or C'3x o0#ects>, then a
corresponding o0#ect to turn the device off must also 0e declared and vice versa.
%f there e/ists an AC'% 20#ect that controls power =C'!x or C'3x, where x \, 4, 2, or 3>, then
methods to set the device into - and -3 device states must 0e present.
%f a mi/ture of C'!x and C'3x methods is declared for the device, then the device states supported
through C'!x methods must 0e identical to the device states supported through C'3x methods. AC'%
s(stem firmware ma( ena0le device power state control e/clusivel( through C'!x =or C'3x> method
declarations.
When controlling power to devices which must wake the s(stem during a s(stem sleeping state<
The device must declare its a0ilit( to wake the s(stem 0( declaring either the C'3W or C'!W
o0#ect.
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%f C'3 is present, then 2!'M must choose a sleeping state which is less than or e:ual to the
sleeping state specified.
After 2!'M has called C'T!, it must call the deviceMs C'!W to ena0le wake.
2!'M must transition the device into a -&state which is greater than or e:ual that specified 0( the
deviceMs C!/- o0#ect, 0ut less than or e:ual to that specified 0( the deviceMs C!/W o0#ect.
2!'M ma( transition the s(stem to the specified sleep state.
Ta!le .-& 5evice Power Manage%ent Child 3!Cects
3!Cect 5escription
C-!W Control method that ena0les or disa0les the deviceMs wake function for device&onl( wake.
C'! Control method that puts the device in the - device state =device full( on>.
C'!4 Control method that puts the device in the -4 device state.
C'!2 Control method that puts the device in the -2 device state.
C'!3 Control method that puts the device in the -3 device state =device off>.
C'!C 20#ect that evaluates to the deviceMs current power state.
C'3 20#ect that evaluates to the deviceMs power re:uirements in the - device state =device full(
on>.
C'34 20#ect that evaluates to the deviceMs power re:uirements in the -4 device state. The onl(
devices that suppl( this level are those that can achieve the defined -4 device state according
to the related device class.
C'32 20#ect that evaluates to the deviceMs power re:uirements in the -2 device state. The onl(
devices that suppl( this level are those that can achieve the defined -2 device state according
to the related device class.
C'3W 20#ect that evaluates to the deviceMs power re:uirements in order to wake the s(stem from a
s(stem sleeping state.
C'!W Control method that ena0les or disa0les the deviceMs wake function.
C%3C 20#ect that signifies the device has a significant inrush current draw.
C!4- @ighest -&state supported 0( the device in the !4 state
C!2- @ighest -&state supported 0( the device in the !2 state
C!3- @ighest -&state supported 0( the device in the !3 state
C!"- @ighest -&state supported 0( the device in the !" state
C!W 1owest -&state supported 0( the device in the ! state which can wake the device
C!4W 1owest -&state supported 0( the device in the !4 state which can wake the s(stem.
C!2W 1owest -&state supported 0( the device in the !2 state which can wake the s(stem.
C!3W 1owest -&state supported 0( the device in the !3 state which can wake the s(stem.
C!"W 1owest -&state supported 0( the device in the !" state which can wake the s(stem.
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8.2.1 _DSW (Device Sleep Wake)
%n addition to C'3W, this control method can 0e used to ena0le or disa0le the deviceMs a0ilit( to wake a
sleeping s(stem. This control method can onl( access 2peration 3egions that are either alwa(s availa0le
while in a s(stem working state or that are availa0le when the 'ower 3esources referenced 0( the C'3W
o0#ect are all 2N. 5or e/ample, do not put a power plane control for a 0us controller within configuration
space located 0ehind the 0us. The method should ena0le the device onl( for the last s(stem stateFdevice
state com0ination passed in 0( 2!'M. 2!'M will onl( pass in com0inations allowed 0( the C!x- and
C!xW o0#ects.
The arguments provided to C-!W indicate the eventual -evice !tate the device will 0e transitioned to and
the eventual s(stem state that the s(stem will 0e transitioned to. The target s(stem state is allowed to 0e the
s(stem working state =!>. The C-!W method will 0e run 0efore the device is placed in the designated
state and also 0efore the s(stem is placed in the designated s(stem state.
Compati0ilit( Note< The C'!W method is deprecated in AC'% 3.. The C-!W method should 0e used
instead. 2!'M will onl( use the C'!W method if 2!'M does not support C-!W or if the C-!W method is
not present.
Arguments<
I .na0le F -isa0le< to disa0le the deviceMs wake capa0ilities.
4 to ena0le the deviceMs wake capa0ilities.
4& Target !(stem !tate to indicate s(stem will 0e in !
4 to indicate s(stem will 0e in !4
N
2& Target -evice !tate to indicate that the device will remain in -
4 to indicate that the device will 0e placed in either - or -4
2 to indicate that the device will 0e placed in either -, -4, or -2
3 to indicate that the device will 0e placed in either -, -4, -2, or -3
3esult Code<
None
8.2.2 _PS0 (Power State 0)
This Control Method is used to put the specific device into its - state. This Control Method can onl(
access 2peration 3egions that are either alwa(s availa0le while in a s(stem working state or that are
availa0le when the 'ower 3esources references 0( the C'3 o0#ect are all 2N.
Arguments<
None
3esult Code<
None
8.2.3 _PS1 (Power State 1)
This control method is used to put the specific device into its -4 state. This control method can onl( access
2peration 3egions that are either alwa(s availa0le while in a s(stem working state or that are availa0le
when the 'ower 3esources references 0( the C'34 o0#ect are all 2N.
Arguments<
None
3esult Code<
None
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8.2.4 _PS2 (Power State 2)
This control method is used to put the specific device into its -2 state. This control method can onl( access
2peration 3egions that are either alwa(s availa0le while in a s(stem working state or that are availa0le
when the 'ower 3esources references 0( the C'32 o0#ect are all 2N.
Arguments<
None
3esult Code<
None
8.2.5 _PS3 (Power State 3)
This control method is used to put the specific device into its -3 state. This control method can onl( access
2peration 3egions that are alwa(s availa0le while in a s(stem working state.
A device in the -3 state must no longer 0e using its resources =for e/ample, its memor( space and %F2 ports
are availa0le to other devices>.
Arguments<
None
3esult Code<
None
8.2.6 _PSC (Power State Current)
This control method evaluates to the current device state. This control method is not re:uired if the device
state can 0e inferred 0( the 'ower 3esource settings. This would 0e the case when the device does not
re:uire a C'!, C'!4, C'!2, or C'!3 control method.
Arguments<
None
3esult Code<
The result codes are shown in Ta0le 9&3.
Ta!le .-# DPSC Control Method "esult Codes
"esult 5evice State
-
4 -4
2 -2
3 -3
8.2.7 _PR0 (Power Resources for D0)
This o0#ect evaluates to a package of the following definition<
Ta!le .-( Power "esource "eJuire%ents Package
1le%ent 3!Cect 5escription
4 o0#ect reference 3eference to re:uired 'ower 3esource Y
N o0#ect reference 3eference to re:uired 'ower 3esource YN
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38 Advanced Configuration and 'ower %nterface !pecification
5or 2!'M to put the device in the - device state, the following must occur<
4. All 'ower 3esources referenced 0( elements 4 through N must 0e in the 2N state.
2. All 'ower 3esources no longer referenced 0( an( device in the s(stem must 0e in the 255 state.
3. %f present, the C'! control method is e/ecuted to set the device into the - device state.
C'3 must return the same data each time it is evaluated. All power resources referenced must e/ist in the
namespace.
8.2.8 _PR1 (Power Resources for D1)
This o0#ect evaluates to a package as defined in Ta0le 9&". 5or 2!'M to put the device in the -4 device
state, the following must occur<
4. All 'ower 3esources referenced 0( elements 4 through N must 0e in the 2N state.
2. All 'ower 3esources no longer referenced 0( an( device in the s(stem must 0e in the 255 state.
3. %f present, the C'!4 control method is e/ecuted to set the device into the -4 device state.
C'34 must return the same data each time it is evaluated. All power resources referenced must e/ist in the
namespace.
8.2.9 _PR2 (Power Resources for D2)
This o0#ect evaluates to a package as defined in Ta0le 9&". 5or 2!'M to put the device in the -2 device
state, the following must occur<
4. All 'ower 3esources referenced 0( elements 4 through N must 0e in the 2N state.
2. All 'ower 3esources no longer referenced 0( an( device in the s(stem must 0e in the 255 state.
3. %f present, the C'!2 control method is e/ecuted to set the device into the -2 device state.
C'32 must return the same data each time it is evaluated. All power resources referenced must e/ist in the
namespace.
8.2.10 _PRW (Power Resources for Wake)
This o0#ect is onl( re:uired for devices that have the a0ilit( to wake the s(stem from a s(stem sleeping
state. This o0#ect evaluates to a package of the following definition<
Ta!le .-A :ake Power "eJuire%ents Package
1le%ent 3!Cect
T)pe
5escription
Numeric or
package
%f the data t(pe of this package element is numeric, then this C'3W package
element is the 0it inde/ in the $'./C.N, in the $'. 0locks descri0ed in the
5A-T, of the ena0le 0it that is ena0led for the wake event.
%f the data t(pe of this package element is a package, then this C'3W package
element is itself a package containing two elements. The first is an o0#ect
reference to the $'. ;lock device that contains the $'. that will 0e triggered 0(
the wake event. The second element is numeric and it contains the 0it inde/ in the
$'./C.N, in the $'. ;lock referenced 0( the first element in the package, of the
ena0le 0it that is ena0led for the wake event.
5or e/ample, if this field is a package then it is of the form<
Pac%a&e'()\_#B.PCI*.I#A.+PE, ./
4 Numeric The lowest power s(stem sleeping state that can 0e entered while still providing
wake functionalit(.
2 20#ect
3eference
3eference to re:uired 'ower 3esource Y
N 20#ect
3eference
3eference to re:uired 'ower 3esource YN
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5or 2!'M to have the defined wake capa0ilit( properl( ena0led for the device, the following must occur<
4. All 'ower 3esources referenced 0( elements 2 through N are put into the 2N state.
2. %f present, the C'!W control method is e/ecuted to set the device&specific registers to ena0le the wake
functionalit( of the device.
3. The -&state 0eing entered must 0e at least that specified in the C!/- state 0ut no greater than that
specified in the C!/W state.
Then, if the s(stem enters a sleeping state 2!'M must ensure<
4. %nterrupts are disa0led.
2. The sleeping state 0eing entered must 0e less than or e:ual to the power state declared in element
4 of the C'3W o0#ect.
3. The proper general&purpose register 0its are ena0led.
The s(stem sleeping state specified must 0e a state that the s(stem supports =in other words, a
corresponding BC!x o0#ect must e/ist in the namespace>.
C'3W must return the same data each time it is evaluated. All power resources referenced must e/ist in the
namespace.
8.2.11 _PSW (Power State Wake)
%n addition to the C'3Wcontrol method, this control method can 0e used to ena0le or disa0le the deviceMs
a0ilit( to wake a sleeping s(stem. This control method can onl( access 2peration 3egions that are either
alwa(s availa0le while in a s(stem working state or that are availa0le when the 'ower 3esources references
0( the C'3W o0#ect are all 2N. 5or e/ample, do not put a power plane control for a 0us controller within
configuration space located 0ehind the 0us.
Compati0ilit( Note< The C'!W method is deprecated in AC'% 3.. 2!'M must use C-!W if it is present.
2therwise, it ma( use C'!W.
Arguments<
I .na0le F -isa0le< to disa0le the deviceMs wake capa0ilities.
4 to ena0le the deviceMs wake capa0ilities.
3esult Code<
None
8.2.12 _IRC (In Rush Current)
The presence of this o0#ect signifies that transitioning the device to its - state causes a s(stem&significant
in&rush current load. %n general, such operations need to 0e serialiHed such that multiple operations are not
attempted concurrentl(. Within AC'%, this t(pe of serialiHation can 0e accomplished with the reso'rceorder
parameter of the deviceMs 'ower 3esourcesK however, this does not serialiHe AC'%&controlled devices with
non&AC'% controlled devices. %3C is used to signif( this fact outside of 2!'M to 2!'M such that 2!'M
can serialiHe all devices in the s(stem that have in&rush current serialiHation re:uirements. 2!'M can onl(
transition one device containing an C%3C o0#ect within its device scope to the - state at a time. %t is
important to note that 2!'M does not evaluate the C%3C o0#ect. %t has no defined input arguments nor does
it return an( value. 2!'M derives meaning simpl( from the e/istence of the C%3C o0#ect.
8.2.13 _S1D (S1 Device State)
This o0#ect evaluates to an integer that conve(s to 2!'M the highest power =lowest num0er> -&state
supported 0( this device in the !4 s(stem sleeping state. C!4- must return the same integer each time it is
evaluated. This value overrides an !&state to -&state mapping 2!'M ma( ascertain from the deviceMs
power resource declarations. !ee Ta0le 9&3 for valid result codes.
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%f the device can wake the s(stem from the !4 s(stem sleeping state =see C'3W> then the device must
support wake in the -&state returned 0( this o0#ect. @owever, 2!'M cannot assume wake from the !4
s(stem sleeping state is supported in an( lower -&state unless specified 0( a corresponding C!4W o0#ect.
The ta0le 0elow provides a mapping from -esired Actions to 3esultant -&state entered 0ased on the values
returned from the C!4-, C'3W, and C!4W o0#ects if the( e/ist . =-FC means -onMt Care I evaluation is
irrelevant, and NFA means Non Applica0le I o0#ect does not e/ist>.
Ta!le .-- S+ Action @ "esult Ta!le
-esired Action C!4- C'3W C!4W 3esultant -&state
.nter !4 -FC -FC -FC 2!'M decides
.nter !4, No Wake 2 -FC -FC .nter -2 or -3
.nter !4, Wake 2 4 NFA .nter -2
.nter !4, Wake 2 4 3 .nter -2 or -3
.nter !4, Wake NFA 4 2 .nter -,-4 or -2
8.2.14 _S2D (S2 Device State)
This o0#ect evaluates to an integer that conve(s to 2!'M the highest power =lowest num0er> -&state
supported 0( this device in the !2 s(stem sleeping state. C!2- must return the same integer each time it is
evaluated. This value overrides an !&state to -&state mapping 2!'M ma( ascertain from the deviceMs
power resource declarations. !ee Ta0le 9&3 for valid result codes.
%f the device can wake the s(stem from the !2 s(stem sleeping state =see C'3W> then the device must
support wake in the -&state returned 0( this o0#ect. @owever, 2!'M cannot assume wake from the !2
s(stem sleeping state is supported in an( lower -&state unless specified 0( a corresponding C!2W o0#ect.
The ta0le 0elow provides a mapping from -esired Actions to 3esultant -&state entered 0ased on the values
returned from the C!2-, C'3W, and C!2W o0#ects if the( e/ist . =-FC means -onMt Care I evaluation is
irrelevant, and NFA means Non Applica0le I o0#ect does not e/ist>.
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Ta!le .-. S& Action @ "esult Ta!le
-esired Action C!2- C'3W C!2W 3esultant -&state
.nter !2 -FC -FC -FC 2!'M decides
.nter !2, No Wake 2 -FC -FC .nter -2 or -3
.nter !2, Wake 2 2 NFA .nter -2
.nter !2, Wake 2 2 3 .nter -2 or -3
.nter !2, Wake NFA 2 2 .nter -,-4 or -2
8.2.15 _S3D (S3 Device State)
This o0#ect evaluates to an integer that conve(s to 2!'M the highest power =lowest num0er> -&state
supported 0( this device in the !3 s(stem sleeping state. C!3- must return the same integer each time it is
evaluated. This value overrides an !&state to -&state mapping 2!'M ma( ascertain from the deviceMs
power resource declarations. !ee Ta0le 9&3 for valid result codes.
%f the device can wake the s(stem from the !3 s(stem sleeping state =see C'3W> then the device must
support wake in the -&state returned 0( this o0#ect. @owever, 2!'M cannot assume wake from the !3
s(stem sleeping state is supported in an( lower -&state unless specified 0( a corresponding C!3W o0#ect.
The ta0le 0elow provides a mapping from -esired Actions to 3esultant -&state entered 0ased on the values
returned from the C!3-, C'3W, and C!3W o0#ects if the( e/ist . =-FC means -onMt Care I evaluation is
irrelevant, and NFA means Non Applica0le I o0#ect does not e/ist>.
Ta!le .-/ S# Action @ "esult Ta!le
-esired Action C!3- C'3W C!3W 3esultant -&state
.nter !3 NFA -FC NFA 2!'M decides
.nter !3, No Wake 2 -FC -FC .nter -2 or -3
.nter !3, Wake 2 3 NFA .nter -2
.nter !3, Wake 2 3 3 .nter -2 or -3
.nter !3, Wake NFA 3 2 .nter -, -4 or -2
8.2.16 _S4D (S4 Device State)
This o0#ect evaluates to an integer that conve(s to 2!'M the highest power =lowest num0er> -&state
supported 0( this device in the !" s(stem sleeping state. C!"- must return the same integer each time it is
evaluated. This value overrides an !&state to -&state mapping 2!'M ma( ascertain from the deviceMs
power resource declarations. !ee Ta0le 9&3 for valid result codes.
%f the device can wake the s(stem from the !" s(stem sleeping state =see C'3W> then the device must
support wake in the -&state returned 0( this o0#ect. @owever, 2!'M cannot assume wake from the !"
s(stem sleeping state is supported in an( lower -&state unless specified 0( a corresponding C!"W o0#ect.
The ta0le 0elow provides a mapping from -esired Actions to 3esultant -&state entered 0ased on the values
returned from the C!"-, C'3W, and C!"W o0#ects if the( e/ist . =-FC means -onMt Care I evaluation is
irrelevant, and NFA means Non Applica0le I o0#ect does not e/ist>.
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Ta!le .-, S( Action @ "esult Ta!le
-esired Action C!"- C'3W C!3W 3esultant -&state
.nter !" NFA -FC NFA 2!'M decides
.nter !", No Wake 2 -FC -FC .nter -2 or -3
.nter !", Wake 2 " No .nter -2
.nter !", Wake 2 " 3 .nter -2 or -3
.nter !", Wake NFA " 2 .nter -, -4 or -2
8.2.17 _S0W (S0 Device Wake State)
This o0#ect evaluates to an integer that conve(s to 2!'M the lowest power =highest num0er> -&state
supported 0( this device in the ! s(stem sleeping state w1ere t1e de2ice can wa3e itself! C!W must return
the same integer each time it is evaluated. This value allows 2!'M to choose the lowest power -&state and
still achieve wake functionalit(. %f o0#ect evaluates to Hero, then the device cannot wake itself from an(
lower sleeping state.
8.2.18 _S1W (S1 Device Wake State)
This o0#ect evaluates to an integer that conve(s to 2!'M the lowest power =highest num0er> -&state
supported 0( this device in the !4 s(stem sleeping state w1ic1 can wa3e t1e system. C!4W must return the
same integer each time it is evaluated. This value allows 2!'M to choose a lower !&state to -&state
mapping than specified 0( C!4-. This value must alwa(s 0e greater than or e:ual to C!4-, if C!4- is
present.
8.2.19 _S2W (S2 Device Wake State)
This o0#ect evaluates to an integer that conve(s to 2!'M the lowest power =highest num0er> -&state
supported 0( this device in the !2 s(stem sleeping state w1ic1 can wa3e t1e system. C!2W must return the
same integer each time it is evaluated. This value allows 2!'M to choose a lower !&state to -&state
mapping than specified 0( C!2-. This value must alwa(s 0e greater than or e:ual to C!2-, if C!2- is
present.
8.2.20 _S3W (S3 Device Wake State)
This o0#ect evaluates to an integer that conve(s to 2!'M the lowest power =highest num0er> -&state
supported 0( this device in the !3 s(stem sleeping state w1ic1 can wa3e t1e system. C!3W must return the
same integer each time it is evaluated. This value allows 2!'M to choose a lower !&state to -&state
mapping than specified 0( C!3-. This value must alwa(s 0e greater than or e:ual to C!3-, if C!3- is
present.
8.2.21 _S4W (S4 Device Wake State)
This o0#ect evaluates to an integer that conve(s to 2!'M the lowest power =highest num0er> -&state
supported 0( this device in the !" s(stem sleeping state w1ic1 can wa3e t1e system. C!"W must return the
same integer each time it is evaluated. This value allows 2!'M to choose a lower !&state to -&state
mapping than specified 0( C!"-. This value must alwa(s 0e greater than or e:ual to C!"-, if C!"- is
present.
8.3 OEM-Supplied System-Level Control Methods
An 2.M&supplied -efinition ;lock provides some num0er of controls appropriate for s(stem&level
management. These are used 0( 2!'M to integrate to the 2.M&provided features. The following ta0le lists
the defined 2.M s(stem controls that can 0e provided.
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Ta!le .-+$ <I3S-Supplied Control Methods for S)ste%-Level 6unctions
3!Cect 5escription
BC;5! Control method e/ecuted immediatel( following a wake event.
BC'T! Control method used to notif( the platform of impending sleep transition.
BC$T! Control method e/ecuted #ust prior to setting the sleep ena0le =!1'C.N> 0it.
BC! 'ackage that defines s(stem BC! state mode.
BC!4 'ackage that defines s(stem BC!4 state mode.
BC!2 'ackage that defines s(stem BC!2 state mode.
BC!3 'ackage that defines s(stem BC!3 state mode.
BC!" 'ackage that defines s(stem BC!" state mode.
BC!* 'ackage that defines s(stem BC!* state mode.
BCTT! Control method used to prepare to sleep and run once awakened
BCWAE Control method run once awakened.
8.3.1 \_BFS (Back From Sleep)
C;5! is an optional control method. %f it e/ists, 2!'M must e/ecute the C;5! method immediatel(
following wake from an( sleeping state !4, !2, !3, or !". C;5! allows AC'% s(stem firmware to perform
an( re:uired s(stem specific functions when returning a s(stem sleep state. 2!'M will e/ecute the C;5!
control method 0efore performing an( other ph(sical %F2 or ena0ling an( interrupt servicing upon returning
from a sleeping state. A value that indicates the sleeping state from which the s(stem was awoken =in other
words, 4\!4, 2\!2, 3\!3, "\!"> is passed as an argument to the C;5! control method.
The C;5! method must 0e self&contained =not call other methods>. Additionall(, C;5! ma( onl( access
2p3egions that are currentl( availa0le =see the C3.$ method for details>.
Arguments<
< The value of the previous sleeping state =4 for !4, 2 for !2, and so on>.
8.3.2 \_PTS (Prepare To Sleep)
The C'T! control method is e/ecuted 0( the 2! during the sleep transition process for !4, !2, !3, !", and
for orderl( !* shutdown. The sleeping state value =5or e/ample, 4, 2, 3, " or * for the !* soft&off state> is
passed to the C'T! control method. This method is called after 2!'M has notified native device drivers of
the sleep state transition and 0efore the 2!'M has had a chance to full( prepare the s(stem for a sleep state
transition. Thus, this control method can 0e e/ecuted a relativel( long time 0efore actuall( entering the
desired sleeping state. %f 2!'M a0orts the sleep state transition, 2!'M should run the CWAE method to
indicate this condition to the platform.
The C'T! control method cannot modif( the current configuration or power state of an( device in the
s(stem. 5or e/ample, C'T! would simpl( store the sleep t(pe in the em0edded controller in se:uencing the
s(stem into a sleep state when the !1'C.N 0it is set.
The platform must not make an( assumptions a0out the state of the machine when C'T! is called. 5or
e/ample, operation region accesses that re:uire devices to 0e configured and ena0led ma( not succeed, as
these devices ma( 0e in a non&decoding state due to plug and pla( or power management operations.
Arguments<
< The value of the sleeping state =4 for !4, 2 for !2, and so on>.
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8.3.3 \_GTS (Going To Sleep)
C$T! is an optional control method. %f it e/ists, 2!'M must e/ecute the C$T! control method #ust prior to
setting the sleep ena0le =!1'C.N> 0it in the 'M4 control register when entering the !4, !2, !3, and !"
sleeping states and when entering !* for orderl( shutdown. C$T! allows AC'% s(stem firmware to perform
an( re:uired s(stem specific functions prior to entering a s(stem sleep state. 2!'M will set the sleep
ena0le =!1'C.N> 0it in the 'M4 control register immediatel( following the e/ecution of the C$T! control
method without performing an( other ph(sical %F2 or allowing an( interrupt servicing. The sleeping state
value =4, 2, 3, ", or *> is passed as an argument to the C$T! control method. The C$T! method must not
attempt to directl( place the s(stem into a sleeping state. 2!'M performs this function 0( setting the sleep
ena0le 0it upon return from C$T!. %n the case of entr( into the !* soft off state however, C$T! ma( indeed
perform operations that place the s(stem into the !* state as 2!'M will not regain control.
The C$T! method must 0e self&contained =not call other methods>. Additionall(, C$T! ma( onl( access
2p3egions that are currentl( availa0le =see the C3.$ method for details>.
Arguments<
< The value of the sleeping state =4 for !4, 2 for !2, and so on>.
8.3.4 System \_Sx states
All s(stem states supported 0( the s(stem must provide a package containing the -W23- value of the
following format in the static -efinition ;lock. The s(stem states, known as !I!*, are referenced in the
namespace as BC!IBC!* and for clarit( the short !x names are used unless specificall( referring to the
named BC!x o0#ect. 5or each !x state, there is a defined s(stem 0ehavior.
Ta!le .-++ S)ste% State Package
<)te
Length
<)te
3ffset 5escription
4 Dalue for 'M4aCCNT.!1'CTS' register to enter this s(stem state.
4 4 Dalue for 'M40CCNT.!1'CTS' register to enter this s(stem state. To enter an(
given state, 2!'M must write the 'M4aCCNT.!1'CTS' register 0efore the
'M40CCNT.!1'CTS' register.
2 2 3eserved
!tates !4I!" represent some s(stem sleeping state. The ! state is the s(stem working state. Transition into
the ! state from some other s(stem state =such as sleeping> is automatic, and, 0( virtue that instructions
are 0eing e/ecuted, 2!'M assumes the s(stem to 0e in the ! state. Transition into an( s(stem sleeping
state is onl( accomplished 0( the operating software directing the hardware to enter the appropriate state,
and the operating software can onl( do this within the re:uirements defined in the 'ower 3esource and
;usF-evice 'ackage o0#ects.
All run&time s(stem state transitions =for e/ample, to and from the ! state>, e/cept !" and !*, are done
similarl( such that the code se:uence to do this is the following<
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/[
[ #ntel &rchitecture SetSleepin,State e-ample
[/
X60!:
SetS12temSleepin, (
#! X60!: !ewState
)

PR0)%SS0R_)0!<%R< )onte-tK
X60!: PowerSe8eunceK
B006%&! 5lu2h)ache2K
XS"0R< Slp<1pK
// Re0u1re" en1ron2ent3 %-ecutin, on the 212tem boot
// proce22or. &ll other proce22or2 2topped. #nterrupt2
// di2abled. &ll Power Re2ource2 (and device2) are in
// corre2pondin, device 2tate to 2upport !ewState.
// :et h/w attribute2 for thi2 212tem 2tate
5lu2h)ache2L Sleep<1peM!ewStateN.5lu2h)acheK
Slp<1p L Sleep<1peM!ewStateN.Slp<1p V S6P_<SP_;&SAK
_a2m
lea ea-$ 02Re2ume)onte-t
pu2h ea- K Build real mode handler the re2ume
pu2h off2et 2pG( K conte-t$ with eip L 2pG(
call SaveProce22orState
mov ea-$ Re2ume@ector K 2et firmware]2 re2ume vector
mov Mea-N$ off2et 02Real;odeRe2ume)ode
mov ed-$ P;4a_S<S K;a+e 2ure wa+e 2tatu2 i2 clear
mov a-$ W&A_S<S K (cleared b1 a22ertin, the bit
out d-$ a- K in the 2tatu2 re,i2ter)
mov ed-$ P;4b_S<S K
out d-$ a- K
and ea-$ not S6P_<SP_;&SA
or ea-$ Slp<1p K 2et S6P_<SP
or a-$ S6P_%! K 2et S6P_%!
cmp 5lu2h)ache2$ (
9C 2hort 2p4( K #f needed$ en2ure no dirt1 data in
call 5lu2hProce22or)ache2 K the cache2 while 2leepin,
2p4(> mov ed-$ P;4a_S6P_<SP K ,et addre22 for P;4a_S6P_<SP
out d-$ a- K 2tart h/w 2e8uencin,
mov ed-$ P;4b_S6P_<SP K ,et addre22 for P;4b_S6P_<SP
out d-$ a- K 2tart h/w 2e8uencin,
mov ed-$ P;4a_S<S K ,et addre22 for P;4-_S<S
mov ec-$ P;4b_S<S
2p3(> in a-$ d- K wait for W&A 2tatu2
-ch, ed-$ ec-
te2t a-$ W&A_S<S
9C 2hort 2p3(
2pG(>
/
// Done..
[Re2ume@ector L !X66K
return (K
/
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8.3.4.1
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8.3.4.1
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36 Advanced Configuration and 'ower %nterface !pecification
System \_S0 State (Working)
While the s(stem is in the ! state, it is in the s(stem working state. The 0ehavior of this state is defined as<
The processors are in the C, C4, C2, or C3 states. The processor&comple/ conte/t is maintained
and instructions are e/ecuted as defined 0( an( of these processor states.
-(namic 3AM conte/t is maintained and is readFwrite 0( the processors.
-evices states are individuall( managed 0( the operating software and can 0e in an( device state
=-, -4, -2, or -3>.
'ower 3esources are in a state compati0le with the current device states.
Transition into the ! state from some s(stem sleeping state is automatic, and 0( virtue that instructions are
0eing e/ecuted 2!'M, assumes the s(stem to 0e in the ! state.
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8.3.4.2
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System \_S1 State (Sleeping with Processor Context Maintained)
While the s(stem is in the !4 sleeping state, its 0ehavior is the following<
The processors are not e/ecuting instructions. The processor&comple/ conte/t is maintained.
-(namic 3AM conte/t is maintained.
'ower 3esources are in a state compati0le with the s(stem !4 state. All 'ower 3esources that
suppl( a !(stem&1evel reference of ! are in the 255 state.
-evices states are compati0le with the current 'ower 3esource states. 2nl( devices that solel(
reference 'ower 3esources that are in the 2N state for a given device state can 0e in that device state.
%n all other cases, the device is in the -3 =off> state
4
.
-evices that are ena0led to wake the s(stem and that can do so from their current device state can
initiate a hardware event that transitions the s(stem state to !. This transition causes the processor to
continue e/ecution where it left off.
To transition into the !4 state, the 2!'M must flush all processor caches.
4
2r it is at least assumed to 0e in the -3 state 0( its device driver. 5or e/ample, if the device doesnMt
e/plicitl( descri0e how it can sta( in some state non&off state while the s(stem is in a sleeping state, the
operating software must assume that the device can lose its power and state.
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8.3.4.3
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System \_S2 State
The !2 sleeping state is logicall( lower than the !4 state and is assumed to conserve more power. The
0ehavior of this state is defined as<
The processors are not e/ecuting instructions. The processor&comple/ conte/t is not maintained.
-(namic 3AM conte/t is maintained.
'ower 3esources are in a state compati0le with the s(stem !2 state. All 'ower 3esources that
suppl( a !(stem&1evel reference of ! or !4 are in the 255 state.
-evices states are compati0le with the current 'ower 3esource states. 2nl( devices that solel(
reference 'ower 3esources that are in the 2N state for a given device state can 0e in that device state.
%n all other cases, the device is in the -3 =off> state.
-evices that are ena0led to wake the s(stem and that can do so from their current device state can
initiate a hardware event that transitions the s(stem state to !. This transition causes the processor to
0egin e/ecution at its 0oot location. The ;%2! performs initialiHation of core functions as needed to
e/it an !2 state and passes control to the firmware resume vector. !ee section 49.3.2, J;%2!
%nitialiHation of Memor(,L for more details on ;%2! initialiHation.
;ecause the processor conte/t can 0e lost while in the !2 state, the transition to the !2 state re:uires that
the operating software flush all dirt( cache to d(namic 3AM =-3AM>.
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8.3.4.4
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8.3.4.4
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System \_S3 State
The !3 state is logicall( lower than the !2 state and is assumed to conserve more power. The 0ehavior of
this state is defined as follows<
The processors are not e/ecuting instructions. The processor&comple/ conte/t is not maintained.
-(namic 3AM conte/t is maintained.
'ower 3esources are in a state compati0le with the s(stem !3 state. All 'ower 3esources that
suppl( a !(stem&1evel reference of !, !4, or !2 are in the 255 state.
-evices states are compati0le with the current 'ower 3esource states. 2nl( devices that solel(
reference 'ower 3esources that are in the 2N state for a given device state can 0e in that device state.
%n all other cases, the device is in the -3 =off> state.
-evices that are ena0led to wake the s(stem and that can do so from their current device state can
initiate a hardware event that transitions the s(stem state to !. This transition causes the processor to
0egin e/ecution at its 0oot location. The ;%2! performs initialiHation of core functions as necessar( to
e/it an !3 state and passes control to the firmware resume vector. !ee section 49.3.2, J;%2!
%nitialiHation of Memor(,L for more details on ;%2! initialiHation.
5rom the software viewpoint, this state is functionall( the same as the !2 state. The operational difference
can 0e that some 'ower 3esources that could 0e left 2N to 0e in the !2 state might not 0e availa0le to the
!3 state. As such, additional devices ma( need to 0e in a logicall( lower -, -4, -2, or -3 state for !3
than !2. !imilarl(, some device wake events can function in !2 0ut not !3.
;ecause the processor conte/t can 0e lost while in the !3 state, the transition to the !3 state re:uires that
the operating software flush all dirt( cache to -3AM.
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8.3.4.5
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System \_S4 State
While the s(stem is in this state, it is in the s(stem !" sleeping state. The state is logicall( lower than the !3
state and is assumed to conserve more power. The 0ehavior of this state is defined as follows<
The processors are not e/ecuting instructions. The processor&comple/ conte/t is not maintained.
-3AM conte/t is not maintained.
'ower 3esources are in a state compati0le with the s(stem !" state. All 'ower 3esources that
suppl( a !(stem&1evel reference of !, !4, !2, or !3 are in the 255 state.
-evices states are compati0le with the current 'ower 3esource states. %n other words, all devices
are in the -3 state when the s(stem state is !".
-evices that are ena0led to wake the s(stem and that can do so from their !" device state can
initiate a hardware event that transitions the s(stem state to !. This transition causes the processor to
0egin e/ecution at its 0oot location.
After 2!'M has e/ecuted the C'T! control method and has put the entire s(stem state into main memor(,
there are two wa(s that 2!'M ma( handle the ne/t phase of the !" state transitionK saving and restoring
main memor(. The first wa( is to use the operating s(stemMs drivers to access the disks and file s(stem
structures to save a cop( of memor( to disk and then initiate the hardware !" se:uence 0( setting the
!1'C.N register 0it. When the s(stem wakes, the firmware performs a normal 0oot process and transfers
control to the 2! via the firmwareCwakingCvector loader. The 2! then restores the s(stemMs memor( and
resumes e/ecution.
The alternate method for entering the !" state is to utiliHe the ;%2! via the !";%2! transition. The ;%2!
uses firmware to save a cop( of memor( to disk and then initiates the hardware !" se:uence. When the
s(stem wakes, the firmware restores memor( from disk and wakes 2!'M 0( transferring control to the
5AC! waking vector.
The !";%2! transition is optional, 0ut an( s(stem that supports this mechanism must support entering the
!" state via the direct 2! mechanism. Thus the preferred mechanism for !" support is the direct 2!
mechanism as it provides 0roader platform support. The alternate !";%2! transition provides a wa( to
achieve !" support on operating s(stems that do not have support for the direct method.
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8.3.4.6
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8.3.4.6
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System \_S5 State (Soft Of)
The !* state is similar to the !" state e/cept that 2!'M does not save an( conte/t. The s(stem is in the
soft off state and re:uires a complete 0oot when awakened =;%2! and 2!>. !oftware uses a different state
value to distinguish 0etween this state and the !" state to allow for initial 0oot operations within the ;%2!
to distinguish whether or not the 0oot is going to wake from a saved memor( image. 2!'M does not
disa0le wake events 0efore setting the !1'C.N 0it when entering the !* s(stem state. This provides
support for remote management initiatives 0( ena0ling 3emote !tart capa0ilit(. An AC'%&compliant 2!
must provide an end user accessi0le mechanism for disa0ling all wake devices, with the e/ception of the
s(stem power 0utton, from a single point in the user interface.
8.3.5 _SWS (System Wake Source)
This o0#ect provides a means for 2!'M to definitivel( determine the source of an event that caused the
s(stem to enter the ! state. $eneral&purpose event and fi/ed&feature hardware registers containing wake
event sources information are insufficient for this purpose as the source event information ma( not 0e
availa0le after transitions to the ! state from all other s(stem states =!4&!*>. To determine the source event
that caused the s(stem to transition to the ! state, 2!'M will evaluate the C!W! o0#ect, when it e/ists,
under the BC$'. scope =for all fi/ed&feature general&purpose events from the $'. ;locks>, under the BC!;
scope =for fi/ed&feature hardware events>, and within the scope of a $'. ;lock device =for $'. events
from this device>. C!W! o0#ects ma( e/ist in an( or all of these locations as necessar( for the platform to
determine the source event that caused the s(stem to transition to the ! state.
To ena0le 2!'M to determine the source of the ! state transition via the C!W! o0#ect, hardware or
firmware should detect and save the event that caused the transition so that it can 0e returned during C!W!
o0#ect evaluation. The single wake source for the s(stem ma( 0e latched in hardware during the transition
so that no false wake events can 0e returned 0( C!W!. An implementation that does not use hardware to
latch a single wake source for the s(stem and instead uses firmware to save the wake source must do so as
:uickl( as possi0le after the wakeup event occurs, so that C!W! does not return values that correspond to
events that occurred after the sleep&to&wake transition. !uch an implementation must also take care to
ensure that events that occur su0se:uent to the wakeup source 0eing saved do not overwrite the original
wakeup source. The source event data returned 0( C!W! must 0e determined for each transition into the !
state. The value returned 0( C!W! must also 0e persistent during the s(stemMs residenc( in the ! state as
2!'M ma( evaluate C!W! multiple times. %n this case, the platform must return the same source event
information for each invocation.
Arguments<
None
3esult Code
#ourceEent< DWord)on2t
Where<
#ourceEent is the inde/ of the $'. input that caused the s(stem to transition to the ! state if
2!'M evaluates C!W! under the BC$'. scope.
#ourceEent is the inde/ of the $'. input that caused the s(stem to transition to the ! state if
2!'M evaluates C!W! within the scope of a $'. ;lock device. %n this case the inde/ is relative
to the $'. 0lock device, and is not uni:ue s(stem&wide.
#ourceEent is the inde/ in the 'M4 !tatus register that caused the s(stem to transition to the !
state if 2!'M evaluates C!W! under the BC!; scope .
#ourceEent has all 0its set =3nes> if the event that caused the s(stem to transition to the ! state
cannot 0e determined when 2!'M evaluates C!W! under an( of the three scopes listed a0ove.
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After evaluating an C!W! o0#ect within the BC$'. scope or within the scope of a $'. 0lock device,
2!'M will invoke the CW// control method corresponding to the $'. inde/ returned 0( C!W! if it e/ists.
This allows the platform to further determine source event if the $'. is shared among multiple devices.
!ee !ection *.+.2.2." for details.
8.3.6 \_TTS (Transition To State)
The CTT! control method is e/ecuted 0( the 2!'M at the 0eginning of the sleep transition process for !4,
!2, !3, !", and orderl( !* shutdown. 2!'M will invoke CTT! 0efore it has notified an( native mode
device drivers of the sleep state transition. The sleeping state value =5or e/ample, 4, 2, 3, " or * for the !*
soft&off state> is passed to the CTT! control method.
The CTT! control method is also e/ecuted 0( the 2!'M at the end of an( sleep transition process when the
s(stem transitions to ! from !4, !2, !3, or !". 2!'M will invoke CTT! after it has notified an( native
mode device drivers of the end of the sleep state transition. The working state value => is passed to the
CTT! control method.
%f 2!'M a0orts the sleep transition process, 2!'M will still run CTT! for an ! transition to indicate the
2!'M has returned to the ! state. The platform must assume that if 2!'M invokes the CTT! control
method for an !4, !2, !3, or !" transition, that 2!'M will invoke CTT! control method for an !
transition 0efore returning to the ! state.
The platform must not make an( assumptions a0out the state of the machine when CTT! is called. 5or
e/ample, operation region accesses that re:uire devices to 0e configured and ena0led ma( not succeed, as
these devices ma( 0e in a non&decoding state due to plug and pla( or power management operations.
Arguments<
< The value of the sleeping state =4 for !4, 2 for !2, and so on>
8.3.7 \_WAK (System Wake)
After the s(stem wakes from a sleeping state, it will invoke the BCWAE method and pass the sleeping state
value that has ended. This operation occurs as(nchronousl( with other driver notifications in the s(stem
and is not the first action to 0e taken when the s(stem wakes. The AM1 code for this control method issues
device, thermal, and other notifications to ensure that 2!'M checks the state of devices, thermal Hones, and
so on, that could not 0e maintained during the s(stem sleeping state. 5or e/ample, if the s(stem cannot
determine whether a device was inserted or removed from a 0us while in the !2 state, the CWAE method
would issue a de2icec1ec3 t(pe of notification for that 0us when issued with the sleeping state value of 2
=for more information a0out t(pes of notifications, see section +.+.3, J-evice 20#ect NotificationsL>. Notice
that a device check notification from the BC!; node will cause 2!'M to re&enumerate the entire tree
44
.
@ardware is not o0ligated to track the state needed to suppl( the resulting statusK however, this method
must return status concerning the last sleep operation initiated 0( 2!'M. The result codes can 0e used to
provide additional information to 2!'M or user.
Arguments<
The value of the sleeping state =4 for !4, 2 for !2, and so on>.
3esult Code =2 -W23- package><
!tatus ;it field of defined conditions that occurred during sleep.
/ Wake was signaled and was successful
/4 Wake was signaled 0ut failed due to lack of power.
/2 Wake was signaled 0ut failed due to thermal condition.
2ther 3eserved
44
2nl( 0uses that support hardware&defined enumeration methods are done automaticall( at run&time. This
would include AC'%&enumerated devices.
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"" Advanced Configuration and 'ower %nterface !pecification
'!! %f non&Hero, the effective !&state the power suppl( reall( entered.
This value is used to detect when the targeted !&state was not entered 0ecause of too much current
0eing drawn from the power suppl(. 5or e/ample, this might occur when some active deviceMs current
consumption pushes the s(stemMs power re:uirements over the low power suppl( mark, thus
preventing the lower power mode from 0eing entered as desired.
8.4 OSPM usage of _GTS, _PTS, _TTS, _WAK, and _BFS
2!'M will invoke C$T!, C'T!, CTT!, CWAE, and C;5! in the following order<
4.2!'M decides =through a polic( scheme> to place the s(stem into a sleeping state.
2.CTT!=!/> is run, where !/ is the desired sleep state to enter.
3. 2!'M notifies all native device drivers of the sleep state transition
".C'T! is run
*.2!'M readies s(stem for the sleep state transition
+.C$T! is run
9.2!'M writes the sleep vector and the s(stem enters the specified !/ sleep state.
8.!(stem Wakes up
6.C;5! is run
4.2!'M readies s(stem for the return from the sleep state transition
44.CWAE is run
42. 2!'M notifies all native device drivers of the return from the sleep state transition
43.CTT!=> is run to indicate the return to the ! state.
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6igure .-+ :orking @ Sleeping State o!Cect evaluation flow
9 Processor Power and Performance State Confguration and Control
This section descri0es the configuration and control of the processorMs power and performance states. The
ma#or controls over the processors are<
'rocessor power states< C, C4, C2, C3, N Cn
'rocessor clock throttling
'rocessor performance states< ', '4, N 'n
These controls are used in com0ination 0( 2!'M to achieve the desired 0alance of the following
sometimes conflicting goals<
'erformance
'ower consumption and 0atter( life
Thermal re:uirements
Noise&level re:uirements
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"+ Advanced Configuration and 'ower %nterface !pecification
;ecause the goals interact with each other, the operating software needs to implement a polic( as to when
and where tradeoffs 0etween the goals are to 0e made
42
. 5or e/ample, the operating software would
determine when the audi0le noise of the fan is undesira0le and would trade off that re:uirement for lower
thermal re:uirements, which can lead to lower processing performance. .ach processor configuration and
control interface is discussed in the following sections along with how controls interacts with the various
goals.
9.1 Processor Power States
AC'% defines the power state of s(stem processors while in the $ working state
43
as 0eing either active
=e/ecuting> or sleeping =not e/ecuting>. 'rocessor power states include are designated C, C4, C2, C3, N
Cn. The C power state is an active power state where the C', e/ecutes instructions. The C4 through Cn
power states are processor sleeping states where the processor consumes less power and dissipates less heat
than leaving the processor in the C state. While in a sleeping state, the processor does not e/ecute an(
instructions. .ach processor sleeping state has a latenc( associated with entering and e/iting that
corresponds to the power savings. %n general, the longer the entr(Fe/it latenc(, the greater the power
savings when in the state. To conserve power, 2!'M places the processor into one of its supported sleeping
states when idle. While in the C state, AC'% allows the performance of the processor to 0e altered through
a defined JthrottlingL process and through transitions into multiple performance states ='&states>. A diagram
of processor power states is provided 0elow.
Interr(pt
Interr(pt
!+T
P>+D+5
T!T>&@<3
an"
DTA<val(e
T!T>&@<0
Perfor%ance
State P' Throttling
C3 C5 C-
P>+D+-
ARB>DIS<3
Interr(pt or
B*Access
,0
.or/ing
C0
42
A thermal warning leaves room for operating s(stem tradeoffs to occur =to start the fan or to reduce
performance>, 0ut a critical thermal alert does not occur.
43
Notice that these C', states map into the $ working state. The state of the C', is undefined in the $3
sleeping state, the Cx states onl( appl( to the $ state.
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6igure /-+ Processor Power States
AC'% defines logic on a per&C', 0asis that 2!'M uses to transition 0etween the different processor power
states. This logic is optional, and is descri0ed through the 5A-T ta0le and processor o0#ects =contained in
the hierarchical namespace>. The fields and flags within the 5A-T ta0le descri0e the s(mmetrical features
of the hardware, and the processor o0#ect contains the location for the particular C',Ms clock logic
=descri0ed 0( the 'C;1E register 0lock and CC!T o0#ects>.
The 'C1D12 and 'C1D13 registers provide optional support for placing the s(stem processors into the C2
or C3 states. The 'C1D12 register is used to se:uence the selected processor into the C2 state, and the
'C1D13 register is used to se:uence the selected processor into the C3 state. Additional support for the C3
state is provided through the 0us master status and ar0iter disa0le 0its =;MC!T! in the 'M4C!T! register
and A3;C-%! in the 'M2CCNT register>. !(stem software reads the 'C1D12 or 'C1D13 registers to enter
the C2 or C3 power state. The @ardware must put the processor into the proper clock state precisel( on the
read operation to the appropriate 'C1D1/ register. The platform ma( alternativel( define interfaces
allowing 2!'M to enter C&states using the CC!T o0#ect, which is defined in !ection 8.".2.4, JCC!T =C
!tates>L.
'rocessor power state support is s(mmetric when presented via the 5A-T and 'C;1E interfacesK 2!'M
assumes all processors in a s(stem support the same power states. %f processors have non&s(mmetric power
state support, then the ;%2! will choose and use the lowest common power states supported 0( all the
processors in the s(stem through the 5A-T ta0le. 5or e/ample, if the C', processor supports all power
states up to and including the C3 state, 0ut the C',4 processor onl( supports the C4 power state, then
2!'M will onl( place idle processors into the C4 power state =C', will never 0e put into the C2 or C3
power states>. Notice that the C4 power state must 0e supported. The C2 and C3 power states are optional
=see the '32CCC4 flag in the 5A-T ta0le description in section *.2.+, J!(stem -escription Ta0le
@eaderL>.
The following sections descri0e processor power states in detail.
9.1.1 Processor Power State C0
While the processor is in the C power state, it e/ecutes instructions. While in the C power state, 2!'M
can generate a polic( to run the processor at less than ma/imum performance. The clock throttling
mechanism provides 2!'M with the functionalit( to perform this task in addition to thermal control. The
mechanism allows 2!'M to program a value into a register that reduces the processorMs performance to a
percentage of ma/imum performance.
dut, width
dut, 9alue
cloc: on time
cloc: off time
P%C&T
dut, offset dut, width
dut, 9alue
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"8 Advanced Configuration and 'ower %nterface !pecification
6igure /-& Throttling 1xa%ple
The 5A-T contains the dut( offset and dut( width values. The dut( offset value determines the offset
within the 'CCNT register of the dut( value. The dut( width value determines the num0er of 0its used 0(
the dut( value =which determines the granularit( of the throttling logic>. The performance of the processor
0( the clock logic can 0e e/pressed with the following e:uation<
X [ Performance
d'tysetting
d'tywidt1
=
2
4X
1Juation + 5ut) C)cle 1Juation
Nominal performance is defined as Jclose as possi0le, 0ut not 0elow the indicated performance level.L
2!'M will use the dut( offset and dut( width to determine how to access the dut( setting field. 2!'M will
then program the dut( setting 0ased on the thermal condition and desired power of the processor o0#ect.
2!'M calculates the nominal performance of the processor using the e:uation e/pressed in .:uation 4.
Notice that a d'tysetting of Hero is reserved.
5or e/ample, the clock logic could use the stop grant c(cle to emulate a divided processor clock fre:uenc(
on an %A processor =through the use of the !T'C1EY signal>. This signal internall( stops the processorMs
clock when asserted 12W. To implement logic that provides eight levels of clock control, the !T'C1EY
pin could 0e asserted as follows =to emulate the different fre:uenc( settings><
1 / Reser9ed 6alue
!
"
(
>
;
K
<
1 ! " ( > ; K <
"(tysetting
D(ty .i"th 1--bits2
S
T
P
C
+
K
B
S
i
g
n
a
l
CP* Cloc: Running
CP* Cloc: Stopped
6igure /-# 1xa%ple Control for the STPCLES
To start the throttling logic 2!'M sets the desired dut( setting and then sets the T@TC.N 0it @%$@. To
change the dut( setting, 2!'M will first reset the T@TC.N 0it 12W, then write another value to the dut(
setting field while preserving the other unused fields of this register, and then set the T@TC.N 0it @%$@
again.
The e/ample logic model is shown 0elow<
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// dut, width
T7T-%'TA
P%C&T4x
P%-6-(
Read
P%-6-"
Read
T7T%$&
P%C&T4>
Cloc: -ogic
S,stem
Ar0iter
ARB%'IS
PM"%C&T
BM%STS
PM!x%STS4>
BM%R-'
PM!x%C&T4!
6igure /-( ACPI Clock Logic >3ne per Processor?
%mplementation of the AC'% processor power state controls minimall( re:uires the support a single C',
sleeping state =C4>. All of the C', power states occur in the $F! s(stem stateK the( have no meaning
when the s(stem transitions into the sleeping state=!4&!">. AC'% defines the attri0utes =semantics> of the
different C', states =defines four of them>. %t is up to the platform implementation to map an appropriate
low&power C', state to the defined AC'% C', state.
AC'% clock control is supported through the optional processor register 0lock ='C;1E>. AC'% re:uires that
there 0e a uni:ue processor register 0lock for each C', in the s(stem. Additionall(, AC'% re:uires that the
clock logic for multiprocessor s(stems 0e s(mmetrical when using the 'C;1E and 5A-T interfacesK if the
' processor supports the C4, C2, and C3 states, 0ut '4 onl( supports the C4 state, then 2!'M will limit
all processors to enter the C4 state when idle.
The following sections define the different AC'% C', sleeping states.
9.1.2 Processor Power State C1
All processors must support this power state. This state is supported through a native instruction of the
processor =@1T for %A 32&0it processors>, and assumes no hardware support is needed from the chipset. The
hardware latenc( of this state must 0e low enough that 2!'M does not consider the latenc( aspect of the
state when deciding whether to use it. Aside from putting the processor in a power state, this state has no
other software&visi0le effects. %n the C4 power state, the processor is a0le to maintain the conte/t of the
s(stem caches.
The hardware can e/it this state for an( reason, 0ut must alwa(s e/it this state when an interrupt is to 0e
presented to the processor.
9.1.3 Processor Power State C2
This processor power state is optionall( supported 0( the s(stem. %f present, the state offers improved
power savings over the C4 state and is entered 0( using the 'C1D12 command register for the local
processor or an alternative mechanism as indicated 0( the CC!T o0#ect. The worst&case hardware latenc(
for this state is declared in the 5A-T and 2!'M can use this information to determine when the C4 state
should 0e used instead of the C2 state. Aside from putting the processor in a power state, this state has no
other software&visi0le effects. 2!'M assumes the C2 power state has lower power and higher e/it latenc(
than the C4 power state.
The C2 power state is an optional AC'% clock state that needs chipset hardware support. This clock logic
consists of an interface that can 0e manipulated to cause the processor comple/ to precisel( transition into a
C2 power state. %n a C2 power state, the processor is assumed capa0le of keeping its caches coherentK for
e/ample, 0us master and multiprocessor activit( can take place without corrupting cache conte/t.
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The C2 state puts the processor into a low&power state optimiHed around multiprocessor and 0us master
s(stems. 2!'M will cause an idle processor comple/ to enter a C2 state if there are 0us masters or Multiple
processor activit( =which will prevent 2!'M from placing the processor comple/ into the C3 state>. The
processor comple/ is a0le to snoop 0us master or multiprocessor C', accesses to memor( while in the C2
state.
The hardware can e/it this state for an( reason, 0ut must alwa(s e/it this state whenever an interrupt is to
0e presented to the processor.
9.1.4 Processor Power State C3
This processor power state is optionall( supported 0( the s(stem. %f present, the state offers improved
power savings over the C4 and C2 state and is entered 0( using the 'C1D13 command register for the local
processor or an alternative mechanism as indicated 0( the CC!T o0#ect. The worst&case hardware latenc(
for this state is declared in the 5A-T, and 2!'M can use this information to determine when the C4 or C2
state should 0e used instead of the C3 state. While in the C3 state, the processorMs caches maintain state 0ut
the processor is not re:uired to snoop 0us master or multiprocessor C', accesses to memor(.
The hardware can e/it this state for an( reason, 0ut must alwa(s e/it this state when an interrupt is to 0e
presented to the processor or when ;MC31- is set and a 0us master is attempting to gain access to
memor(.
2!'M is responsi0le for ensuring that the caches maintain coherenc(. %n a uniprocessor environment, this
can 0e done 0( using the 'M2CCNT.A3;C-%! 0us master ar0itration disa0le register to ensure 0us master
c(cles do not occur while in the C3 state. %n a multiprocessor environment, the processorsM caches can 0e
flushed and invalidated such that no d(namic information remains in the caches 0efore entering the C3
state.
There are two mechanisms for supporting the C3 power state<
@aving 2!'M flush and invalidate the caches prior to entering the C3 state.
'roviding hardware mechanisms to prevent masters from writing to memor( =uniprocessor&onl(
support>.
%n the first case, 2!'M will flush the s(stem caches prior to entering the C3 state. As there is normall(
much latenc( associated with flushing processor caches, 2!'M is likel( to onl( support this in
multiprocessor platforms for idle processors. 5lushing of the cache is accomplished through one of the
defined AC'% mechanisms =descri0ed 0elow in section 8.2, J5lushing CachesL>.
%n uniprocessor&onl( platforms that provide the needed hardware functionalit( =defined in this section>,
2!'M will attempt to place the platform into a mode that will prevent s(stem 0us masters from writing
into memor( while the processor is in the C3 state. This is accomplished 0( disa0ling 0us masters prior to
entering a C3 power state. ,pon a 0us master re:uesting an access, the C', will awaken from the C3 state
and re&ena0le 0us master accesses.
2!'M uses the ;MC!T! 0it to determine the power state to enter when considering a transition to or from
the C2FC3 power state. The ;MC!T! is an optional 0it that indicates when 0us masters are active. 2!'M
uses this 0it to determine the polic( 0etween the C2 and C3 power states< a lot of 0us master activit(
demotes the C', power state to the C2 =or C4 if C2 is not supported>, no 0us master activit( promotes the
C', power state to the C3 power state. 2!'M keeps a running histor( of the ;MC!T! 0it to determine
C', power state polic(.
The last hardware feature used in the C3 power state is the ;MC31- 0it. This 0it determines if the Cx
power state was e/ited as a result of 0us master re:uests. %f set, then the Cx power state was e/ited upon a
re:uest from a 0us master. %f reset, the power state was not e/ited upon 0us master re:uests. %n the C3 state,
0us master re:uests need to transition the C', 0ack to the C state =as the s(stem is capa0le of maintaining
cache coherenc(>, 0ut such a transition is not needed for the C2 state. 2!'M can optionall( set this 0it
when using a C3 power state, and clear it when using a C4 or C2 power state.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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9.1.5 Additional Processor Power States
AC'% introduced optional processor power states 0e(ond C3 starting in AC'% 2.. These power states,
C"N Cn, are conve(ed to 2!'M through the CC!T o0#ect defined in section 8.".2.4, JCC!T =C&!tates>.L
These additional power states are characteriHed 0( e:uivalent operational semantics to the C4 through C3
power states, as defined in the previous sections, 0ut with different entr(Fe/it latencies and power savings.
!ee section 8.".2.4, JCC!T =C&!tates>,L for more information.
9.2 Flushing Caches
To support the C3 power state without using the A3;C-%! feature, the hardware must provide functionalit(
to flush and invalidate the processorsM caches =for an %A processor, this would 0e the W;%ND- instruction>.
To support the !4, !2 or !3 sleeping states, the hardware must provide functionalit( to flush the platform
caches. 5lushing of caches is supported 0( one of the following mechanisms<
'rocessor instruction to write 0ack and invalidate s(stem caches =W;%ND- instruction for %A
processors>.
'rocessor instruction to write 0ack 0ut not invalidate s(stem caches =W;%ND- instruction for %A
processors and some chipsets with partial supportK that is, the( donMt invalidate the caches>.
The AC'% specification e/pects all platforms to support the local C', instruction for flushing s(stem
caches =with support in 0oth the C', and chipset>, and provides some limited J0est effortL support for
s(stems that donMt currentl( meet this capa0ilit(. The method used 0( the platform is indicated through the
appropriate 5A-T fields and flags indicated in this section.
AC'% specifies parameters in the 5A-T that descri0e the s(stemMs cache capa0ilities. %f the platform
properl( supports the processorMs write 0ack and invalidate instruction =W;%ND- for %A processors>, then
this support is indicated to 2!'M 0( setting the W;%ND- flag in the 5A-T.
%f the platform supports neither of the first two flushing options, then 2!'M can attempt to manuall( flush
the cache if it meets the following criteria<
A cache&ena0led se:uential read of contiguous ph(sical memor( of not more than 2 M; will flush
the platform caches.
There are two additional 5A-T fields needed to support manual flushing of the caches<
51,!@C!%?., t(picall( twice the siHe of the largest cache in the s(stem.
51,!@C!T3%-., t(picall( the smallest cache line siHe in the s(stem.
9.3 Power, Performance, and Throttling State Dependencies
Cost and comple/it( trade&off considerations have driven into the platform control dependencies 0etween
logical processors when entering power, performance, and throttling states. These dependencies e/ist in
various forms in multi&processor, multi&threaded processor, and multi&core processor&0ased platforms.
These dependencies ma( also 0e hierarchical. 5or e/ample, a multi&processor s(stem consisting of
processors containing multiple cores containing multiple threads ma( have various dependencies as a result
of the hardware implementation.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"42 Advanced Configuration and 'ower %nterface !pecification
,nless 2!'M is aware of the dependenc( 0etween the logical processors, it might lead to scenarios where
one logical processor is implicitl( transitioned to a power, performance, or throttling state when it is
unwarranted, leading to incorrect F non&optimal s(stem 0ehavior. $iven knowledge of the dependencies,
2!'M can coordinate the transitions 0etween logical processors, choosing to initiate the transition when
doing so does not lead to incorrect or non&optimal s(stem 0ehavior. This 2!'M coordination is referred to
as !oftware =!W> Coordination. Alternatel(, it might 0e possi0le for the underl(ing hardware to coordinate
the state transition re:uests on multiple logical processors, causing the processors to transition to the target
state when the transition is guaranteed to not lead to incorrect or non&optimal s(stem 0ehavior. This
scenario is referred to as @ardware =@W> coordination. When hardware coordinates transitions, 2!'M
continues to initiate state transitions as it would if there were no dependencies. @owever, in this case it is
re:uired that hardware provide 2!'M with a means to determine actual state residenc( so that correct F
optimal control polic( can 0e realiHed.
'latforms containing logical processors with cross&processor dependencies in the power, performance, or
throttling state control areas use AC'% defined interfaces to group logical processors into what is referred to
as a dependenc( domain. The Coordination T(pe characteristic for a domain specifies whether 2!'M or
underl(ing hardware is responsi0le for the coordination. When 2!'M coordinates, the platform ma(
re:uire that 2!'M transition A11 =/5C> or ANS 2N. =/5-> of the processors 0elonging to the domain
into a particular target state. 2!'M ma( choose at its discretion to perform coordination even though the
underl(ing hardware supports hardware coordination. %n this case, 2!'M must transition all logical
processors in the dependenc( domain to the particular target state.
There are no dependencies implied 0etween a processorMs C&states, '&states or T&states. @ence, for e/ample
it is possi0le to use the same dependenc( domain num0er for specif(ing dependencies 0etween '&states
among one set of processors and C&states among another set of processors without an( dependencies 0eing
implied 0etween the '&!tate transitions on a processor in the first set and C&state transitions on a processor
in the second set.
9.4 Declaring Processors
.ach processor in the s(stem must 0e declared in the AC'% namespace in either the BC!; or BC'3 scope 0ut
not 0oth. -eclaration of processor in the BC'3 scope is re:uired for platforms desiring compati0ilit( with
AC'% 4.&0ased 2!'M implementations. 'rocessors are declared either via the A!1 Processor statement
or the A!1 5evice statement. A Processor definition declares a processor o0#ect that provides processor
configuration information and points to the processor register 0lock ='C;1E>. A 5evice definition for a
processor is declared using the AC'%9 hardware identifier =@%->. %n this case, processor configuration
information is provided e/clusivel( 0( o0#ects in the processor deviceMs o0#ect list.
When the platform uses the A'%C interrupt model, 2!'M associates processors declared in the namespace
with entries in the MA-T. 'rior to AC'% 3., this was accomplished using the processor o0#ectMs
'rocessor%- and the AC'% 'rocessor %- fields in MA-T entries. ,%- fields have 0een added to MA-T
entries in AC'% 3.. ;( e/panding processor declaration using 5evice definitions, ,%- o0#ect values under
a processor device can now 0e used to associate processor devices with entries in the MA-T. This removes
the previous 2*+ processor declaration limit.
'rocessor&specific o0#ects ma( 0e included in the processor o0#ectMs optional o0#ect list or declared within
the processor deviceMs scope. These o0#ects serve multiple purposes including providing alternative
definitions for the registers descri0ed 0( the processor register 0lock ='C;1E> and processor performance
state control. 2ther AC'%&defined device&related o0#ects are also allowed in the processor o0#ectMs o0#ect
list or under the processor deviceMs scope =for e/ample, the uni:ue identifier o0#ect C,%->.
With device&like characteristics attri0uted to processors, it is implied that a processor device driver will 0e
loaded 0( 2!'M to, at a minimum, process device notifications. 2!'M will enumerate processors in the
s(stem using the AC'% Namespace, processor&specific native identification instructions, and optionall( the
C@%- method.
2!'M will ignore definitions of AC'%&defined o0#ects in an o0#ect list of a processor o0#ect declared under
the BC'3 namespace.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "43
5or more information on the declaration of the processor o0#ect, see section 49.*.63, J'rocessor =-eclare
'rocessor>.L 'rocessor&specific o0#ects are descri0ed in the following sections.
9.4.1 _PDC (Processor Driver Capabilities)
This optional o0#ect is a method that is used 0( 2!'M to communicate to the platform the level of
processor power management support provided 0( 2!'M. This o0#ect is a child o0#ect of the processor.
2!'M evaluates C'-C prior to evaluating an( other processor power management o0#ects returning
configuration information.
The C'-C o0#ect provides 2!'M a mechanism to conve( to the platform the capa0ilities supported 0(
2!'M for processor power management. This allows the platform to modif( the AC'% namespace o0#ects
returning configuration information for processor power management 0ased on the level of support
provided 0( 2!'M. ,sing this method provides a mechanism for 2.Ms to provide support for new
technologies on legac( 2!es, while also allowing 2!'M to leverage new technologies on platforms
capa0le of supporting them. This method is evaluated once during processor device initialiHation, and will
not 0e re&evaluated during resume from a sleep state transition. The platform must preserve state
information across !4&!3 sleep state transitions.
S)ntax
_PD) (PDCBuffer)LB !ull
Argu%ents
PDCBuffer
-WordConst ;uffer =3evision%-, Count. Capa0ilities-W23-4.G.Capa0ilities-W23-n>
Re1s1onID
The revision %- of the Capa41l1t1esD56RD format.
Count
The num0er of Capa41l1t1esD56RD values in the 0uffer.
Capa41lt1esD56RD78n
Capa0ilities -Words, where each 0it defines capa0ilities and features supported 0( 2!'M for
processor configuration and power management as specified 0( the C', manufacturer.
The use of C'-C is deprecated in AC'% 3. in favor of C2!C. 5or 0ackwards compati0ilit(, C'-C ma( 0e
implemented using C2!C as follows<
;ethod(_PD)$4)

)reateDword5ield (&r,($ ($ R%@S)


)reateDword5ield (&r,($ .$ S#7%)
)reate5ield (&r,($ I.$ Subtract (;ultipl1 (SiCe0f (&r,()$ =)$ I.)$ BX55)
_0S) (<oXX#D ('cHH4H3e3EITIcE.a.=E=T4HEF=3.cGIIbfab*)$ R%@S$ 7ero$ S#7%$ BX55)
/
9.4.2 Processor Power State Control
AC'% defines two processor power state =C state> control interfaces. These are<
4> The 'rocessor 3egister ;lockMs ='C;1EMs> 'C1D12 and 'C1D13 registers coupled with 5A-T
'C1D1/C1AT values and
2> The CC!T o0#ect in the processorMs o0#ect list.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"4" Advanced Configuration and 'ower %nterface !pecification
'C;1E 0ased C state controls are descri0ed in !ection ", JAC'% @ardware !pecificationL and !ection 8.4,
J'rocessor 'ower !tatesL. CC!T 0ased C state controls e/pand the functionalit( of the 'C;1E 0ased
controls allowing the num0er and t(pe of C states to 0e d(namic and accommodate C', architecture
specific C state entr( and e/it mechanisms as indicated 0( registers defined using the 5unctional 5i/ed
@ardware address space.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
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9.4.2.1
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"4+ Advanced Configuration and 'ower %nterface !pecification
_CST (C States)
CC!T is an optional o0#ect that provides an alternative method to declare the supported processor power
states =C !tates>. Dalues provided 0( the CC!T o0#ect override 'C1D1/ values in 'C;1E and
'C1D1/C1AT values in the 5A-T. The CC!T o0#ect allows the num0er of processor power states to 0e
e/panded 0e(ond C4, C2, and C3 to an ar0itrar( num0er of power states. The entr( semantics for these
e/panded states, =in other words>, the considerations for entering these states, are conve(ed to 2!'M 0(
the C&stateCT(pe field and correspond to the entr( semantics for C4, C2, and C3 as descri0ed in sections
8.4.2 through 8.4.". CC!T defines ascending C&states characteriHed 0( lower power and higher entr(Fe/it
latenc(.
S)ntax
_)S< LB C#9Pac%a&e
"eturn 7alue
C#9Pac%a&e< Pac+a,e =Count, C#tate,N, C#tate> where<
Count< B1te)on2t
The num0er of C#tate packages included in C#9Pac%a&e
CState< Pac+a,e =Re&1ster. 9:pe. ;atenc:. Po<er>
Where<
Re&1ster< Re,i2ter<erm
A register that 2!'M reads to place the processor in the corresponding C state.
9:pe< B1te)on2t
The C !tate t(pe =for e/ample, 4\C4, 2\C2, and so on>. This field conve(s the semantics
to 0e used 0( 2!'M when enteringFe/iting the C state. ?ero is not a valid value
;atenc:< Word)on2t
The worst&case latenc( in microseconds to enter and e/it the C !tate. There are no
latenc( restrictions.
Po<er< DWord)on2t
The average power consumption in milliwatts of the processor when in the corresponding
C !tate.
The platform must e/pose a CC!T o0#ect for either all or none of its processors. %f the CC!T o0#ect e/ists,
2!'M uses the C state information specified in the CC!T o0#ect in lieu of 'C1D12 and 'C1D13 registers
defined in 'C;1E and the 'C1D1/C1AT values defined in the 5A-T. Also notice that if the CC!T o0#ect
e/ists and the C'TC o0#ect does not e/ist, 2!'M will use the 'rocessor Control 3egister defined in
'C;1E and the CC!tateC3egister registers in the CC!T o0#ect.
The platform ma( change the num0er or t(pe of C !tates availa0le for 2!'M use d(namicall( 0( issuing a
0otif) events on the processor o0#ect with a notification value of /84. This will cause 2!'M to re&
evaluate an( CC!T o0#ect residing under the processor o0#ect notified. 5or e/ample, the platform might
notif( 2!'M that the num0er of supported C !tates has changed as a result of an as(nchronous AC
insertion F removal event.
The platform must specif( uni:ue CC!tateC3egister addresses for all entries within a given CC!T o0#ect.
CC!T eliminates the AC'% 4. restriction that all processors must have C !tate parit(. With CC!T, each
processor can have its own characteristics independent of other processors. 5or e/ample, processor can
support C4, C2 and C3, while processor 4 supports onl( C4.
The fields in the processor structure remain for 0ackward compati0ilit(.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "49
1=AMPL1
Proce22or (
\_SB.)PX($ // Proce22or !ame
4$ // &)P# Proce22or number
(-43($ // PBl+ 212tem #0 addre22
I ) // PBl+6en

!ame(_)S<$ Pac+a,e()

.$ // <here are four )E2tate2 defined here with three 2emantic2


// <he third and fourth )E2tate2 defined have the 2ame )F entr1 2emantic2
Pac+a,e()Re2ource<emplate()Re,i2ter(55i-ed"W$ ($ ($ ()/$ 4$ 3($ 4(((/$
Pac+a,e()Re2ource<emplate()Re,i2ter(S12tem#0$ =$ ($ (-4I4)/$ 3$ .($ TG(/$
Pac+a,e()Re2ource<emplate()Re,i2ter(S12tem#0$ =$ ($ (-4I3)/$ F$ I($ G((/$
Pac+a,e()Re2ource<emplate()Re,i2ter(S12tem#0$ =$ ($ (-4IF)/$ F$ 4(($ 3G(/
/)
/
Notice in the e/ample a0ove that 2!'M should anticipate the possi0ilit( of a CC!T o0#ect providing more
than one entr( with the same CC!tateCT(pe value. %n this case 2!'M must decide which CC!tateC3egister
it will use to enter that C state.
1=AMPL1
This is an e/ample usage of the CC!T o0#ect using the t(pical values as defined in AC'% 4..
Proce22or (
\_SB.)PX($ // Proce22or !ame
4$ // &)P# Proce22or number
(-43($ // PB6A 212tem #0 addre22
I ) // PB6A 6en

!ame(_)S<$ Pac+a,e()

3$ // <here are two )E2tate2 defined here W )3 and )F


Pac+a,e()Re2ource<emplate()Re,i2ter(S12tem#0$ =$ ($ (-43.)/$ 3$ 2$ TG(/$
Pac+a,e()Re2ource<emplate()Re,i2ter(S12tem#0$ =$ ($ (-43G)/$ F$ IG$ G((/
/)
/
The platform will issue a 0otif)=BC!;.C',, /84) to inform 2!'M to re&evaluate this o0#ect when the
num0er of availa0le processor power states changes.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"48 Advanced Configuration and 'ower %nterface !pecification
9.4.2.2
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "46
_CSD (C-State Dependency)
This optional o0#ect provides C&state control cross logical processor dependenc( information to 2!'M.
The CC!- o0#ect evaluates to a packaged list of information that correlates with the C&state information
returned 0( the CC!T o0#ect. .ach packaged list entr( identifies the C&state for which the dependenc( is
0eing specified =as an inde/ into the CC!T o0#ect list>, a dependenc( domain num0er for that C&state, the
coordination t(pe for that C&state and the num0er of logical processors 0elonging to the domain for the
particular C&state. %t is possi0le that a particular C&state ma( 0elong to multiple domains. That is, it is
possi0le to have multiple entries in the CC!- list with the same C!tate%nde/ value.
S)ntax
_)SD LB C#DPac%a&e
"eturn 7alue
C#DPac%a&e< Pac+a,e =C#tateDep,N, C#tateDep>
Where<
CState5ep< Pac+a,e =Nu24er6fEntr1es, Re1s1on. Do2a1n. Coor"9:pe. Nu2Processors,
In"e=>
Where<
Nu24er6fEntr1es< B1te)on2t
The num0er of entries in the C#tateDep package including this field. Current value is +.
Re1s1on< B1te)on2t
The revision num0er of the C#tateDep package format. Current value is .
Do2a1n< DWord)on2t
The dependenc( domain num0er to which this C state entr( 0elongs.
Coor"9:pe< DWord)on2t
The t(pe of coordination that e/ists =hardware> or is re:uired =software> as a result of the
underl(ing hardware dependenc(. Could 0e either /5C =!WCA11>, /5- =!WCANS>
or /5. =@WCA11> indicating whether 2!'M is responsi0le for coordinating the C&state
transitions among processors with dependencies =and needs to initiate the transition on all
or an( processor in the domain> or whether the hardware will perform this coordination.
Nu2Processors< DWord)on2t
The num0er of processors 0elonging to the domain for the particular C&state. 2!'M will not
start performing power state transitions to a particular C&state until this num0er of processors
0elonging to the same domain for the particular C&state have 0een detected and started.
In"e=< DWord)on2t
%ndicates the inde/ of the C&!tate entr( in the CC!T o0#ect for which the dependenc(
applies.
$iven that the num0er or t(pe of availa0le C !tates ma( change d(namicall(, AC'% supports Notif( events
on the processor o0#ect, with Notif( events of t(pe /84 causing 2!'M to re&evaluate an( CC!T o0#ects
residing under the particular processor o0#ect notified. 2n receipt of Notif( events of t(pe /84, 2!'M
should re&evaluate an( present CC!- o0#ects also.
1=AMPL1
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"2 Advanced Configuration and 'ower %nterface !pecification
This is an e/ample usage of the CC!- structure in a 'rocessor structure in the name space. The e/ample
represents a two processor configuration. The C4&t(pe state can 0e independentl( entered on each
processor. 5or the C2&t(pe state, there e/ists dependence 0etween the two processors, such that one
processor transitioning to the C2&t(pe state, causes the other processor to transition to the C2&t(pe state. A
similar dependence e/ists for the C3&t(pe state. 2!'M will 0e re:uired to coordinate the C2 and C3
transitions 0etween the two processors. Also 2!'M can initiate a transition on either processor to cause
0oth to transition to the common target C&state.
Proce22or (
\_SB.)PX($ // Proce22or !ame
4$ // &)P# Proce22or number
(-43($ // PBl+ 212tem #0 addre22
I ) // PBl+6en

!ame (_)S<$ Pac+a,e()

F$ // <here are three )E2tate2 defined here with three 2emantic2


Pac+a,e()Re2ource<emplate()Re,i2ter(55i-ed"W$ ($ ($ ()/$ 4$ 3($ 4(((/$
Pac+a,e()Re2ource<emplate()Re,i2ter(S12tem#0$ =$ ($ (-4I4)/$ 3$ .($ TG(/$
Pac+a,e()Re2ource<emplate()Re,i2ter(S12tem#0$ =$ ($ (-4I3)/$ F$ I($ G((/
/)
!ame(_)SD$ Pac+a,e()

Pac+a,e()I$ ($ ($ (-5D$ 3$ 4/$ // I entrie2$ Revi2ion ($ Domain ($ 0SP;


)oordinate
// #nitiate on &n1 Proc$ 3 Proc2$ #nde- 4 ()3Et1pe)
Pac+a,e()I$ ($ ($ (-5D$ 3$ 3/ // I entrie2$ Revi2ion ($ Domain ($ 0SP;
)oordinate
// #nitiate on &n1 Proc$ 3 Proc2$ #nde- 3 ()FEt1pe)
/)
/
Proce22or (
\_SB.)PX4$ // Proce22or !ame
3$ // &)P# Proce22or number
$ // PBl+ 212tem #0 addre22
) // PBl+6en

!ame(_)S<$ Pac+a,e()

F$ // <here are three )E2tate2 defined here with three 2emantic2


Pac+a,e()Re2ource<emplate()Re,i2ter(55i-ed"W$ ($ ($ ()/$ 4$ 3($ 4(((/$
Pac+a,e()Re2ource<emplate()Re,i2ter(S12tem#0$ =$ ($ (-4I4)/$ 3$ .($ TG(/$
Pac+a,e()Re2ource<emplate()Re,i2ter(S12tem#0$ =$ ($ (-4I3)/$ F$ I($ G((/
/)
!ame(_)SD$ Pac+a,e()

Pac+a,e()I$ ($ ($ (-5D$ 3$ 4/$ // I entrie2$ Revi2ion ($ Domain ($ 0SP;


)oordinate
// #nitiate on an1 Proc$ 3 Proc2$ #nde- 4 ()3Et1pe)
Pac+a,e()I$ ($ ($ (-5D$ 3$ 3/ // I entrie2$ Revi2ion ($ Domain ($ 0SP;
)oordinate
// #nitiate on an1 Proc$ 3 Proc2$ #nde- 3 ()FEt1pe)
/)
/
When the platform issues a 0otif)=BC!;.C',, /84) to inform 2!'M to re&evaluate CC!T when the
num0er of availa0le processor power states changes, 2!'M should also evaluate CC!-.
9.4.3 Processor Throttling Controls
AC'% defines two processor throttling =T state> control interfaces. These are<
4> The 'rocessor 3egister ;lockMs ='C;1EMs> 'CCNT register and
2> The com0ined C'TC, CT!!, and CT'C o0#ects in the processorMs o0#ect list.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "24
'C;1E 0ased throttling state controls are descri0ed in !ection ", JAC'% @ardware !pecificationL and
!ection 8.4.4, J'rocessor 'ower !tate CL. Com0ined C'TC, CT!!, and CT'C 0ased throttling state
controls e/pand the functionalit( of the 'C;1E 0ased control allowing the num0er of T states to 0e
d(namic and accommodate C', architecture specific T state control mechanisms as indicated 0( registers
defined using the 5unctional 5i/ed @ardware address space. While platform definition of the C'TC, CT!!,
and CT'C o0#ects is optional, all three o0#ects must e/ist under a processor for 2!'M to successfull(
perform processor throttling via these controls.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"22 Advanced Configuration and 'ower %nterface !pecification
9.4.3.1
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "23
_PTC (Processor Throttling Control)
C'TC is an optional o0#ect that defines a processor throttling control interface alternative to the %F2 address
spaced&0ased 'C;1E throttling control register ='CCNT> descri0ed in section ", JAC'% @ardware
!pecificationL. The processor throttling control register mechanism remains as defined in section 8.4.4, J
'rocessor 'ower !tate C.L
The C'TC o0#ect contains data in the following format<
!ame (_P<)$ Pac+a,e()

Processor_Control_Register //Re2ource<emplate<ermE:eneric Re,i2ter De2criptor)


Processor_Status_Register //Re2ource<emplate<ermE:eneric Re,i2ter De2criptor)
/) // %nd of _P<)
The platform must e/pose a C'TC o0#ect for either all or none of its processors. Notice that if the C'TC
o0#ect e/ists, the specified register is used instead of the 'CCNT register specified in the 'rocessor term.
Also notice that if the C'TC o0#ect e/ists and the CC!T o0#ect does not e/ist, 2!'M will use the processor
control register from the C'TC o0#ect and the 'C1D1/ registers from the 'C;1E.
1=AMPL1
This is an e/ample usage of the C'TC o0#ect in a 'rocessor o0#ect list<
Proce22or (
\_SB.)PX($ // Proce22or !ame
4$ // &)P# Proce22or number
(-43($ // PBl+ 212tem #0 addre22
I ) // PBl+6en
//0b9ect 6i2t
!ame(_P<)$ Re2ource<emplate()

Re,i2ter(55i-ed"W$ ($ ($ ()
Re,i2ter(55i-ed"W$ ($ ($ ()
/) //%nd of _P<) 0b9ect
/ // %nd of 0b9ect 6i2t
1=AMPL1
This is an e/ample usage of the C'TC o0#ect using the values defined in AC'% 4.. This is an illustrative
e/ample to demonstrate the mechanism with well&known values.
Proce22or (
\_SB.)PX($ // Proce22or !ame
4$ // &)P# Proce22or number
(-43($ // PB6A 212tem #0 addre22
I ) // PB6A 6en
//0b9ect 6i2t
!ame(_P<)$ // F3 bit wide #0 2paceEba2ed re,i2ter at the ?P_B6AB addre22
Re2ource<emplate()

Re,i2ter(S12tem#0$ F3$ ($ (-43()


Re,i2ter(S12tem#0$ F3$ ($ (-43()
/) //%nd of _P<) 0b9ect
/ // %nd of 0b9ect 6i2t
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"2" Advanced Configuration and 'ower %nterface !pecification
9.4.3.2
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "2*
_TSS (Throttling Supported States)
This optional o0#ect indicates to 2!'M the num0er of supported processor throttling states that an( given
s(stem can support. This o0#ect evaluates to a packaged list of information a0out availa0le throttling states
including internal C', core fre:uenc(, t(pical power dissipation, control register values needed to
transition 0etween throttling states, and status register values that allow 2!'M to verif( throttling state
transition status after an( 2!&initiated transition change re:uest. The list is sorted in descending order 0(
t(pical power dissipation. As a result, the Heroth entr( descri0es the highest throttling state and the OnthM
entr( descri0es the lowest throttling state.
!ame (_<SS$ Pac+a,e()
// 5ield !ame 5ield <1pe
Pac+a,e () // <hrottle State ( Definition W <(

FreqPercentage$ // DWord)on2t
Power$ // DWord)on2t
TransitionLatency$ // DWord)on2t
Control$ // DWord)on2t
Status // DWord)on2t
/$
.
.
.
Pac+a,e () // <hrottle State n Definition W <n

FreqPercentage$ // DWord)on2t
Power$ // DWord)on2t
TransitionLatency$ // DWord)on2t
Control$ // DWord)on2t
Status // DWord)on2t
/
/) // %nd of _<SS ob9ect
.ach throttling state entr( contains five data fields as follows<
)re:Percentage %ndicates the percent of the core C', operating fre:uenc( that this throttling
state will invoke. The range for this field is 4&4. This percentage applies independent of the
processorMs performance state ='&state>. That is, this throttling state will invoke the percentage
indicated of the Core)re: field of theC'!! entr( corresponding to the '&state for which the processor
is resident.
Power %ndicates the t(pical power dissipation =in milliWatts>.
'ransitionLatenc&; %ndicates the worst&case latenc( in microseconds that the C', is unavaila0le
during a transition from an( performance state to this performance state.
Control; %ndicates the value to 0e written to the 'erformance Control 3egister ='.35CCT31> in
order to initiate a transition to the performance state.
tatus; %ndicates the value that 2!'M will compare to a value read from the Throttle !tatus
3egister =T@32TT1.C!TAT,!> to ensure that the transition to the throttling state was successful.
2!'M ma( alwa(s place the C', in the lowest power state, 0ut additional states are onl( availa0le
when indicated 0( the CT'C method. A value of Hero indicates the transition to the Throttling state is
as(nchronous, and as such no status value comparison is re:uired.
When providing the CT!!, the platform must suppl( a CT!! entr( whose )re:Percentage field value is
4. This provides a means for 2!'M to disa0le throttling.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"2+ Advanced Configuration and 'ower %nterface !pecification
9.4.3.3
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "29
_TPC (Throttling Present Capabilities)
This optional o0#ect is a method that d(namicall( indicates to 2!'M the num0er of throttling states
currentl( supported 0( the platform. This method returns a num0er that indicates the CT!! entr( num0er of
the highest throttling state that 2!'M can use at a given time. 2!'M ma( choose the corresponding state
entr( in the CT!! as indicated 0( the value returned 0( the CT'C method or an( lower power =higher
num0ered> state entr( in the CT!!.
Arguments<
None
3eturned Dalue<
Num0er of states supported =integer>
I states .. n
th
state availa0le =all states availa0le>
4 I state 4 .. n
th
state availa0le
2 I state 2 .. n
th
state availa0le
N
n I state n availa0le onl(
%n order to support d(namic changes of CT'C o0#ect, Notif( events on the processor o0#ect of t(pe /82
will cause 2!'M to reevaluate an( CT'C o0#ect in the processor o0#ect list. This allows AM1 code to
notif( 2!'M when the num0er of supported throttling states ma( have changed as a result of an
as(nchronous event.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"28 Advanced Configuration and 'ower %nterface !pecification
9.4.3.4
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "26
_TSD (T-State Dependency)
This optional o0#ect provides T&state control cross logical processor dependenc( information to 2!'M. The
CT!- o0#ect evaluates to a packaged list of information that correlates with the T&state information returned
0( the CT!! o0#ect. .ach packaged list entr( identifies a dependenc( domain num0er for the logical
processorMs T&states, the coordination t(pe for that T&state and the num0er of logical processors 0elonging to
the domain.
S)ntax
_<SD LB 9#DPac%a&e
"eturn 7alue
9#DPac%a&e< Pac+a,e =9#tateDep,N, 9#tateDep>
Where<
TState5ep< Pac+a,e =Nu24er6fEntr1es, Re1s1on. Do2a1n. Coor"9:pe. Nu2Processors>
Where<
Nu24er6fEntr1es< B1te)on2t
The num0er of entries in the 9#tateDep package including this field. Current value is *.
Re1s1on< B1te)on2t
The revision num0er of the 9#tateDep package format. Current value is .
Do2a1n< DWord)on2t
The dependenc( domain num0er to which this T&state entr( 0elongs.
Coor"9:pe< DWord)on2t
The t(pe of coordination that e/ists =hardware> or is re:uired =software> as a result of the
underl(ing hardware dependenc(. Could 0e either /5C =!WCA11>, /5- =!WCANS>
or /5. =@WCA11> indicating whether 2!'M is responsi0le for coordinating the T&state
transitions among processors with dependencies =and needs to initiate the transition on all
or an( processor in the domain> or whether the hardware will perform this coordination.
Nu2Processors< DWord)on2t
The num0er of processors 0elonging to the domain for this logical processorMs T&states.
2!'M will not start performing power state transitions to a particular T&state until this
num0er of processors 0elonging to the same domain have 0een detected and started.
1=AMPL1
This is an e/ample usage of the CT!- structure in a 'rocessor structure in the name space. The e/ample
represents a two processor configuration with three T&states per processor. 5or all T&states, there e/ists
dependence 0etween the two processors, such that one processor transitioning to a particular T&state, causes
the other processor to transition to the same T&state. 2!'M will 0e re:uired to coordinate the T&state
transitions 0etween the two processors and can initiate a transition on either processor to cause 0oth to
transition to the common target T&state.
Proce22or (
\_SB.)PX($ // Proce22or !ame
4$ // &)P# Proce22or number
(-43($ // PBl+ 212tem #0 addre22
I) // PBl+6en
//0b9ect 6i2t
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"3 Advanced Configuration and 'ower %nterface !pecification
!ame(_P<)$ Re2ource<emplate()

Re,i2ter (S12tem#0$ F3$ ($ (-43()


Re,i2ter (S12tem#0$ F3$ ($ (-43()
/) //%nd of _P<) 0b9ect
!ame (_<SS$ Pac+a,e()

Pac+a,e()
(-I.$ // 5re8uenc1 Percenta,e (4((^$ <hrottlin, 055 2tate)
(-($ // Power
(-($ // <ran2ition 6atenc1
(-T$ // )ontrol <"<_%!>( <"<6_D<S>444
(-($ // Statu2
/
Pac+a,e()
(-G=$ // 5re8uenc1 Percenta,e (=T.G^)
(-($ // Power
(-($ // <ran2ition 6atenc1
(-5$ // )ontrol <"<_%!>4 <"<6_D<S>444
(-($ // Statu2
/
Pac+a,e()
(-.B$ // 5re8uenc1 Percenta,e (TG^)
(-($ // Power
(-($ // <ran2ition 6atenc1
(-%$ // )ontrol <"<_%!>4 <"<6_D<S>44(
(-($ // Statu2
/
/)
!ame (_<SD$ Pac+a,e()

Pac+a,e()G$ ($ ($ (-5D$ 3/ // G entrie2$ Revi2ion ($ Domain ($ 0SP;


)oordinate$ 3 Proc2
/) // %nd of _<SD ob9ect
;ethod (_<P)$ () // <hrottlin, Pre2ent )apabilitie2 method

#f (\_SB.&))

Return(() // &ll <hrottle State2 are available for u2e.


/
%l2e

Return(3) // <hrottle State2 ( an 4 won]t be u2ed.


/
/ // %nd of _<P) method
/ // %nd of proce22or ob9ect li2t
Proce22or (
\_SB.)PX4$ // Proce22or !ame
3$ // &)P# Proce22or number
$ // PBl+ 212tem #0 addre22
) // PBl+6en
//0b9ect 6i2t
!ame(_P<)$ Re2ource<emplate()

Re,i2ter (S12tem#0$ F3$ ($ (-43()


Re,i2ter (S12tem#0$ F3$ ($ (-43()
/) //%nd of _P<) 0b9ect
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "34
!ame (_<SS$ Pac+a,e()

Pac+a,e()
(-I.$ // 5re8uenc1 Percenta,e (4((^$ <hrottlin, 055 2tate)
(-($ // Power
(-($ // <ran2ition 6atenc1
(-T$ // )ontrol <"<_%!>( <"<6_D<S>444
(-($ // Statu2
/
Pac+a,e()
(-G=$ // 5re8uenc1 Percenta,e (=T.G^)
(-($ // Power
(-($ // <ran2ition 6atenc1
(-5$ // )ontrol <"<_%!>4 <"<6_D<S>444
(-($ // Statu2
/_
Pac+a,e()
(-.B$ // 5re8uenc1 Percenta,e (TG^)
(-($ // Power
(-($ // <ran2ition 6atenc1
(-%$ // )ontrol <"<_%!>4 <"<6_D<S>44(
(-($ // Statu2
/
/)
!ame (_<SD$ Pac+a,e()

Pac+a,e()G$ ($ ($ (-5D$ 3/ // G entrie2$ Revi2ion ($ Domain ($ 0SP;


)oordinate$ 3 Proc2
/) // %nd of _<SD ob9ect
;ethod (_<P)$ () // <hrottlin, Pre2ent )apabilitie2 method

#f (\_SB.&))

Return(() // &ll <hrottle State2 are available for u2e.


/
%l2e

Return(3) // <hrottle State2 ( an 4 won]t be u2ed.


/
/ // %nd of _<P) method
/ // %nd of proce22or ob9ect li2t
9.4.4 Processor Performance Control
'rocessor performance control is implemented through three optional o0#ects whose presence indicates to
2!'M that the platform and C', are capa0le of supporting multiple performance states. The platform must
suppl( all three o0#ects if processor performance control is implemented. The platform must e/pose
processor performance control o0#ects for either all or none of its processors. The processor performance
control o0#ects define the supported processor performance states, allow the processor to 0e placed in a
specific performance state, and report the num0er of performance states currentl( availa0le on the s(stem.
%n a multiprocessing environment, all C',s must support the same num0er of performance states and each
processor performance state must have identical performance and power&consumption parameters.
'erformance o0#ects must 0e present under each processor o0#ect in the s(stem for 2!'M to utiliHe this
feature.
'rocessor performance control o0#ects include the OC'CTM package, OC'!!M package, and the OC''CM
method as detailed 0elow.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"32 Advanced Configuration and 'ower %nterface !pecification
9.4.4.1
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "33
_PCT (Performance Control)
This optional o0#ect declares an interface that allows 2!'M to transition the processor into a performance
state. 2!'M performs processor performance transitions 0( writing the performance stateIspecific control
value to a 'erformance Control 3egister ='.35CCT31>.
2!'M ma( select a processor performance state as indicated 0( the performance state value returned 0(
the C''C method, or an( lower power =higher num0ered> state. The control value to write is contained in
the corresponding C'!! entr(Ms JControlL field.
!uccess or failure of the processor performance transition is determined 0( reading a 'erformance !tatus
3egister ='.35C!TAT,!> to determine the processorMs current performance state. %f the transition was
successful, the value read from '.35C!TAT,! will match the J!tatusL field in the C'!! entr( that
corresponds to the desired processor performance state.
This o0#ect evaluates to a package that declares the a0ove&mentioned transition control and status addresses
as follows<
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"3" Advanced Configuration and 'ower %nterface !pecification
!ame (_P)<$ Pac+a,e()

Perf_Ctrl_Register$ //Re2ource<emplate<ermE:eneric Re,i2ter De2criptor


Perf_Status_Register //Re2ource<emplate<ermE:eneric Re,i2ter De2criptor
/) // %nd of _P)<
9.4.4.2 Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "3*
_PSS (Performance Supported States)
This optional o0#ect indicates to 2!'M the num0er of supported processor performance states that an(
given s(stem can support. This o0#ect evaluates to a packaged list of information a0out availa0le
performance states including internal C', core fre:uenc(, t(pical power dissipation, control register values
needed to transition 0etween performance states, and status register values that allow 2!'M to verif(
performance transition status after an( 2!&initiated transition change re:uest. The list is sorted in
descending order 0( t(pical power dissipation. As a result, the Heroth entr( descri0es the highest
performance state and the OnthM entr( descri0es the lowest performance state.
!ame (_PSS$ Pac+a,e()
// 5ield !ame 5ield <1pe
Pac+a,e () // Performance State ( Definition W P(

CoreFreq$ // DWord)on2t
Power$ // DWord)on2t
TransitionLatency$ // DWord)on2t
BusMasterLatency$ // DWord)on2t
Control$ // DWord)on2t
Status // DWord)on2t
/$
.
.
.
Pac+a,e () // Performance State n Definition W Pn

CoreFreq$ // DWord)on2t
Power$ // DWord)on2t
TransitionLatency$ // DWord)on2t
BusMasterLatency$ // DWord)on2t
Control$ // DWord)on2t
Status // DWord)on2t
/
/) // %nd of _PSS ob9ect
.ach performance state entr( contains si/ data fields as follows<
Core)re: %ndicates the core C', operating fre:uenc( =in M@H>.
Power %ndicates the t(pical power dissipation =in milliWatts>.
'ransitionLatenc&; %ndicates the worst&case latenc( in microseconds that the C', is unavaila0le
during a transition from an( performance state to this performance state.
#usMasterLatenc&; %ndicates the worst&case latenc( in microseconds that ;us Masters are
prevented from accessing memor( during a transition from an( performance state to this performance
state.
Control; %ndicates the value to 0e written to the 'erformance Control 3egister ='.35CCT31> in
order to initiate a transition to the performance state.
tatus; %ndicates the value that 2!'M will compare to a value read from the 'erformance !tatus
3egister ='.35C!TAT,!> to ensure that the transition to the performance state was successful. 2!'M
ma( alwa(s place the C', in the lowest power state, 0ut additional states are onl( availa0le when
indicated 0( the C''C method.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"3+ Advanced Configuration and 'ower %nterface !pecification
9.4.4.3
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "39
_PPC (Performance Present Capabilities)
This optional o0#ect is a method that d(namicall( indicates to 2!'M the num0er of performance states
currentl( supported 0( the platform. This method returns a num0er that indicates the C'!! entr( num0er of
the highest performance state that 2!'M can use at a given time. 2!'M ma( choose the corresponding
state entr( in the C'!! as indicated 0( the value returned 0( the C''C method or an( lower power =higher
num0ered> state entr( in the C'!!.
Arguments<
None
3eturned Dalue<
Num0er of states supported =integer>
states .. n
th
state availa0le =all states availa0le>
4 state 4 .. n
th
state availa0le
2 state 2 .. n
th
state availa0le
N
n state n availa0le onl(
%n order to support d(namic changes of C''C o0#ect, Notif( events on the processor o0#ect. Notif( events
of t(pe /8 will cause 2!'M to reevaluate an( C''C o0#ects residing under the particular processor
o0#ect notified. This allows AM1 code to notif( 2!'M when the num0er of supported states ma( have
changed as a result of an as(nchronous event =AC insertionFremoval, docked, undocked, and so on>.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"38 Advanced Configuration and 'ower %nterface !pecification
9.4.4.4
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ "36
Processor Performance Control Example
1=AMPL1H
This is an e/ample of processor performance control o0#ects in a processor o0#ect list.
%n this e/ample, a uniprocessor platform that has processor performance capa0ilities with support for three
performance states as follows<
4. * M@H =8.2W> supported at an( time
2. + M@H =4".6W> supported onl( when AC powered
3. +* M@H =24.*W> supported onl( when docked
%t takes no more than * microseconds to transition from one performance state to an( other performance
state.
-uring a performance transition, 0us masters are una0le to access memor( for a ma/imum of 3
microseconds.
The '.35CCT31 and '.35C!TAT,! registers are implemented as 5unctional 5i/ed @ardware.
The following A!1 o0#ects are implemented within the s(stem<
BC!;.-2CE< .valuates to 4 if s(stem is docked, Hero otherwise.
BC!;.AC< .valuates to 4 if AC is connected, Hero otherwise.
Proce22or (
\_SB.)PX($ // Proce22or !ame
4$ // &)P# Proce22or number
(-43($ // PBl+ 212tem #0 addre22
I ) // PBl+6en

!ame(_P)<$ Pac+a,e () // Performance )ontrol ob9ect

Re2ource<emplate()Re,i2ter(55i-ed"W$ ($ ($ ()/$ // P%R5_)<R6


Re2ource<emplate()Re,i2ter(55i-ed"W$ ($ ($ ()/ // P%R5_S<&<XS
/) // %nd of _P)< ob9ect
!ame (_PSS$ Pac+a,e()

Pac+a,e()IG($ 34G(($ G(($ F(($ (-(($ (-(=/$ // Performance State Cero (P()
Pac+a,e()I(($ 4.H(($ G(($ F(($ (-(4$ (-(G/$ // Performance State one (P4)
Pac+a,e()G(($ =3(($ G(($ F(($ (-(3$ (-(I/ // Performance State two (P3)
/) // %nd of _PSS ob9ect
;ethod (_PP)$ () // Performance Pre2ent )apabilitie2 method

#f (\_SB.D0)A)

Return(() // &ll _PSS 2tate2 available (IG($ I(($ G(().


/
#f (\_SB.&))

Return(4) // State2 4 and 3 available (I(($ G(().


/
%l2e

Return(3) // State 3 available (G(()


/
/ // %nd of _PP) method
/ // %nd of proce22or ob9ect li2t
The platform will issue a 0otif)=BC!;.C',, /8> to inform 2!'M to re&evaluate this o0#ect when the
num0er of availa0le processor performance states changes.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
"" Advanced Configuration and 'ower %nterface !pecification
9.4.4.5
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ ""4
_PSD (P-State Dependency)
This optional o0#ect provides '&state control cross logical processor dependenc( information to 2!'M. The
C'!- o0#ect evaluates to a packaged list of information that correlates with the '&state information returned
0( the C'!! o0#ect. .ach packaged list entr( identifies a dependenc( domain num0er for the logical
processorMs '&states, the coordination t(pe for that '&state and the num0er of logical processors 0elonging
to the domain.
S)ntax
_PSD LB P#DPac%a&e
"eturn 7alue
P#DPac%a&e< Pac+a,e =P#tateDep,N, P#tateDep>
Where<
PState5ep< Pac+a,e =Nu24er6fEntr1es, Re1s1on. Do2a1n. Coor"9:pe. Nu2Processors>
Where<
Nu24er6fEntr1es< B1te)on2t
The num0er of entries in the P#tateDep package including this field. Current value is *.
Re1s1on< B1te)on2t
The revision num0er of the P#tateDep package format. Current value is .
Do2a1n< DWord)on2t
The dependenc( domain num0er to which this '&state entr( 0elongs.
Coor"9:pe< DWord)on2t
The t(pe of coordination that e/ists =hardware> or is re:uired =software> as a result of the
underl(ing hardware dependenc(. Could 0e either /5C =!WCA11>, /5- =!WCANS>
or /5. =@WCA11> indicating whether 2!'M is responsi0le for coordinating the '&state
transitions among processors with dependencies =and needs to initiate the transition on all
or an( processor in the domain> or whether the hardware will perform this coordination.
Nu2Processors< DWord)on2t
The num0er of processors 0elonging to the domain for this logical processorMs '&states.
2!'M will not start performing power state transitions to a particular '&state until this
num0er of processors 0elonging to the same domain have 0een detected and started.
1=AMPL1
This is an e/ample usage of the C'!- structure in a 'rocessor structure in the name space. The e/ample
represents a two processor configuration with three performance states per processor. 5or all performance
states, there e/ists dependence 0etween the two processors, such that one processor transitioning to a
particular performance state, causes the other processor to transition to the same performance state. 2!'M
will 0e re:uired to coordinate the '&state transitions 0etween the two processors and can initiate a transition
on either processor to cause 0oth to transition to the common target '&state.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
""2 Advanced Configuration and 'ower %nterface !pecification
Proce22or (
\_SB.)PX($ // Proce22or !ame
4$ // &)P# Proce22or number
(-43($ // PBl+ 212tem #0 addre22
I ) // PBl+6en

!ame(_P)<$ Pac+a,e () // Performance )ontrol ob9ect

Re2ource<emplate()Re,i2ter(55i-ed"W$ ($ ($ ()/$ // P%R5_)<R6


Re2ource<emplate()Re,i2ter(55i-ed"W$ ($ ($ ()/ // P%R5_S<&<XS
/) // %nd of _P)< ob9ect
!ame (_PSS$ Pac+a,e()

Pac+a,e()IG($ 34G(($ G(($ F(($ (-(($ (-(=/$ // Performance State Cero (P()
Pac+a,e()I(($ 4.H(($ G(($ F(($ (-(4$ (-(G/$ // Performance State one (P4)
Pac+a,e()G(($ =3(($ G(($ F(($ (-(3$ (-(I/ // Performance State two (P3)
/) // %nd of _PSS ob9ect
;ethod (_PP)$ () // Performance Pre2ent )apabilitie2 method

/ // %nd of _PP) method


!ame (_PSD$ Pac+a,e()

Pac+a,e()G$ ($ ($ (-5D$ 3/ // G entrie2$ Revi2ion ()$ Domain ($ 0SP;


// )oordinate$ #nitiate on an1 Proc$ 3 Proc2
/) // %nd of _PSD ob9ect
/ // %nd of proce22or ob9ect li2t
Proce22or (
\_SB.)PX4$ // Proce22or !ame
3$ // &)P# Proce22or number
$ // PBl+ 212tem #0 addre22
) // PBl+6en

!ame(_P)<$ Pac+a,e () // Performance )ontrol ob9ect

Re2ource<emplate()Re,i2ter(55i-ed"W$ ($ ($ ()/$ // P%R5_)<R6


Re2ource<emplate()Re,i2ter(55i-ed"W$ ($ ($ ()/ // P%R5_S<&<XS
/) // %nd of _P)< ob9ect
!ame (_PSS$ Pac+a,e()

Pac+a,e()IG($ 34G(($ G(($ F(($ (-(($ (-(=/$ // Performance State Cero (P()
Pac+a,e()I(($ 4.H(($ G(($ F(($ (-(4$ (-(G/$ // Performance State one (P4)
Pac+a,e()G(($ =3(($ G(($ F(($ (-(3$ (-(I/ // Performance State two (P3)
/) // %nd of _PSS ob9ect
;ethod (_PP)$ () // Performance Pre2ent )apabilitie2 method

/ // %nd of _PP) method


!ame (_PSD$ Pac+a,e()

Pac+a,e()G$ ($ ($ (-5D$ 3/ // G entrie2$ Revi2ion ($ Domain ($ 0SP;


// )oordinate$ #nitiate on an1 Proc$ 3 Proc2
/) // %nd of _PSD ob9ect
/ // %nd of proce22or ob9ect li2t
10 ACPI-Devices and Device Specifc Objects
This section descri0es AC'% defined devices and device&specific o0#ects. The s(stem status indicator
o0#ects, declared under the BC!% scope in the AC'% Namespace, are also specified in this section.
Hewlett-Packard@Intel@Microsoft@Phoenix@Toshi!a
%nde/ ""3
10.1 \_SI System Indicators
AC'% provides an interface for a variet( of simple and icon&st(le indicators on a s(stem. All indicator
controls are in the BC!% portion of the namespace. The following ta0le lists all defined s(stem indicators.
=Notice that there are also per&device indicators specified for 0atter( devices>.
Ta!le ,-+ S)ste% Indicator Control Methods
3!Cect 5escription
C!!T !(stem status indicator
CM!$ Messages waiting indicator
10.1.1 _SST (System Status)
This optional o0#ect is a control method that 2!'M invokes to set the s(stem status indicator as desired.
Arguments<
No s(stem state indication. %ndicator off.
4 Working
2 Waking
3 !leeping. ,sed to indicate s(stem state !4, !2 or !3.
" !leeping with conte/t saved to non&volatile storage.
10.1.2 _MSG (Message)
This control method sets the s(stemMs message&waiting status indicator.
Arguments<
Num0er of messages waiting
10.1.3 BLT (Battery Level Threshold)
This optional control method is used 0( 2!'M to indicate to the platform the userMs preference for various
0atter( level thresholds. This method allows platform 0atter( indicators to 0e s(nchroniHed with 2!'M
provided 0atter( notification levels. Note that if C;1T is implemented on a multi&0atter( s(stem, it is
re:uired that the power unit for all 0atteries must 0e the same. !ee section 4.2 for more details on 0atter(
levels.
Arguments<
Argument 4< -W23-<
/4 I /95555555 =in units of mWh or mAh, depending on the Power Bnits value>
,serMs preference for 0atter( warning level. %f the level specified is less than the design capacit( of
warning, it ma( 0e ignored 0( the platform so that the platform can ensure a successful wake on low
0atter(.
Argument 2< -W23-<
/4 I /95555555 =in units of mWh or mAh, depending on the Power Bnits value>
,serMs preference for 0atter( low level. %f this level is less than the design capacit( of low, it ma(
0e ignored 0( the platform.
Argument 3< -W23-<
/4 I /95555555 =in units of mWh or mAh, depending on the Power Bnits value>
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""" Advanced Configuration and 'ower %nterface !pecification
,serMs preference for 0atter( wake level. %f this level is less than the platformMs current wake on low
0atter( level, it ma( 0e ignored 0( the platform. %f the platform does not support a configura0le
wake on low 0atter( level, this ma( 0e ignored 0( the platform..
10.2 Control Method Ambient Light Sensor Device
The following section illustrates the operation and definition of the Control Method Am0ient 1ight !ensor
=A1!> device.
The am0ient light sensor device can optionall( support power management o0#ects =e.g. C'!, C'!3> to
allow the 2! to manage the deviceMs power consumption.
The 'lug and 'la( %- of an AC'% control method am0ient light sensor device is AC'%8.
Ta!le ,-&H Control Method A%!ient Light Sensor 5evice
3!Cect 5escription
CA1% The current am0ient light illuminance reading in lu/ =lumen per s:uare meter>. V3e:uiredW
CA1C The current am0ient light color chromacit( reading, specified using / and ( coordinates per the
C%. S/( color model. V2ptionalW
CA1T The current am0ient light color temperature reading in degrees Eelvin. V2ptionalW
CA13 3eturns a set of am0ient light illuminance to displa( 0rightness mappings that can 0e used 0(
an 2! to cali0rate its am0ient light polic(. V3e:uiredW
CA1' Am0ient light sensor polling fre:uenc( in tenths of seconds. V2ptionalW
10.2.1 Overview
This definition provides a standard interface 0( which the 2! ma( :uer( properties of the am0ient light
environment the s(stem is currentl( operating in, as well as the a0ilit( to detect meaningful changes in
these values when the environment changes. Two am0ient light properties are currentl( supported 0( this
interface< ill'minance and color.
Am0ient light illuminance readings are o0tained via the CA1% method. %lluminance readings indicate the
amount of light incident upon =falling on> a specified surface area. Dalues are specified in l'x =lumen per
s:uare meter> and give an indication of how J0rightL the environment is. 5or e/ample, an overcast da( is
roughl( 4 lu/, a t(pical office environment 3&" lu/, and a diml(&lit conference room around 4
lu/.
A possi0le use of am0ient light illuminance data 0( the 2! is to automaticall( ad#ust the 0rightness =or
l'minance> of the displa( device I e.g. increase displa( luminance in 0rightl(&lit environments and
decrease displa( luminance in diml(&lit environments. Note that 1uminance is a measure of light radiated
=reflected, transmitted, or emitted> 0( a surfac