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Table Of Contents
Please Read This
Chapter 2: VLSI Testing Process and Test Equipment
Chapter 3: Test Economics and Product Quality
Chapter 4: Fault Modeling
Chapter 5: Logic and Fault Simulation
Chapter 6: Testability Measures
Chapter 7: Combinational Circuit ATPG
Chapter 8: Sequential Circuit ATPG
Chapter 9: Memory Test
Chapter 10: DSP-Based Analog and Mixed-Signal Test
Chapter 11: Model-Based Analog and Mixed-Signal Test
Chapter 12: Delay Test
Chapter 13: IDDQ Test
Chapter 14: Digital DFT and Scan Design
Chapter 15: Built-In Self-Test
Chapter 16: Boundary Scan Standard

Chapter 17: Analog Test Bus Standard


Chapter 18: System Test and Core-Based Design
Problem 1: Fault Modeling and Simulation (11 Points)
Solution to Problem 1
Problem 2: Combinational ATPG (11 Points)
Solution to Problem 2
Problem 3: Testability Measures (11 Points)
Solution to Problem 3
Problem 4: Delay Test
Solution to Problem 4
Problem 5: Memory Test (11 Points)
Solution to Problem 5
Problem 6: Analog Test (11 Points)
Problem 7: DFT (11 Points)
Solution to Problem 7
Problem 8: BIST (12 Points)
Solution to Problem 8
Problem 9: Boundary Scan (11 Points)
Solution to Problem 9
Problem 1: Fault Modeling (16 Points)
Problem 2: Testability Measures (16 Points)
Problem 3: Logic Simulation (17 Points)
Problem 4: Podem (17 points)
<http://www.scribd.com/doc/223237891/39/Problem-4-Podem-17-points?sh=e16565057f7
84b14>
Problem 5: Delay Test (17 points)
<http://www.scribd.com/doc/223237891/40/Problem-5-Delay-Test-17-points?sh=28c3ee
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Problem 6: DFT (17 Points)
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Solution to Problem 6
<http://www.scribd.com/doc/223237891/42/Solution-to-Problem-6?sh=e06a9969381cd0e
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Problem 1: Fault Modeling (20 Points)
Problem 2: Testability Measures (20 Points)
Problem 3: ATPG and fault simulation (20 Points)
Problem 4: Fault diagnosis (20 points)
Problem 5: Scan design (20 Points)
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Solutions to Problems
from Essentials of Electronic Testing
c
M. L. Bushnell and V. D. Agrawal, 2002
February 10, 2006
Please Read This
This manual contains solutions to all problems that appear at the end of
the chaptersin the book. At the end of the manual we have included the
solutions to problemswe used for the examinations in the Spring 2002
course at Rutgers University, andSpring 2004 and Spring 2005 courses at
Auburn University.In spite of all the care taken to ensure accuracy, we
caution the user that someanswers may contain errors as it is the rst
release of this manual. We will appreciateif any errors or comments are
forwarded to us by email:
vagrawal@eng.auburn.edu
or
bushnell@caip.rutgers.edu
.This manual has been created as teaching material that accompanies the
book.To preserve its e ectiveness, it should not be distributed. If
necessary, only a verysmall set of solutions can be copied for
distribution in the class. Please do not passyour copy on to others and
ask any one requesting it to contact the authors.Teachers can also use
the presentation slides for 31 lectures (or an alternativesequence of
23-lectures), based on the book and available at the following websites:
http://www.eng.auburn.edu/

vagrawal/COURSE/lectures.html http://www.caip.rutgers.edu/

bushnell/rutgers.html

We hope the readers of our book, both teachers and students, will bene t
fromthis work. We acknowledge the help from colleagues and students in
completingthis solution manual and the assistance of the University of
Wisconsin-Madison inits initial distribution.
Solution Manual V1.4
c
M. L. Bushnell and V. D. Agrawal
For Teachers only
Page 1
Chapter 1: Introduction
1.1 Chip testing
The events of Example 1.1 are rede ned as follows:PQ: chip is good P:
chip passes the testFQ: chip is bad F: chip fails the testA 70% yield
means,
Prob
(
PQ
) = 0
.
7 and
Prob
(
FQ
) = 0
.
3. Following the analysisof Example 1.1,
Prob
(
P
) = 0
.
68. Then,Defect level = Bad chips that pass testsAll chips that pass tests=
Prob
(
FQ
|
P
)=
Prob
(
P
|
FQ
)
Prob
(
FQ
)
Prob
(
P
)= 0
.
05

0
.
30

.
68 = 0
.
022
The defect level is 22
,
000 ppm (parts per million).
1.2 Chip testing
Let
x
denote the escape probability,
Prob
(
P
|
FQ
). Referring to the formula derivedin Problem 1.1, a defect level of 500
ppm
means,
Prob
(
P
|
FQ
)
Prob
(
FQ
)
Prob
(
P
) =
x

0
.
30
.
95

0
.
7 +
x

0
.
3 = 0
.
0005This gives,
x
= 0
.
00033250
.
29985Next, we obtain,Defect coverage =
Prob
(
F

|
FQ
) = 1

Prob
(
P
|
FQ
)= 1

x
= 0
.
99889
The required defect coverage is 99.889%.
This represents the capability of thetest in detecting the actual
defects that occur and should not be confused withthe fault
coverage, which is de ned for the single stuckat fault model.
1.3 Test cost
Assuming that one vector is applied per clock cycle during the digital
test, the rateof test application is 200 million vectors per second.
Therefore,Digital test time = 1000

10
6
200

10
6
= 5
s
Solution Manual V1.4
c
M. L. Bushnell and V. D. Agrawal
For Teachers only
Page 2
Adding the analog test time, we getTotal test time = 1
.
5 + 5
.
0 = 6
.
5
s
The testing cost for a 500
MHz
, 1,024 pin tester was obtained as 4
.
56
cents
inExample 1.2 (see page 11 of the book.) Thus,Cost of testing a chip = 6
.
5

4
.
56 = 29

.
64
cents
The cost of testing bad chips should also be recovered from the price of
good chips.Since the yield of good chips is 70%, we obtainTest cost in
the price of a chip = 29
.
640
.
7

42
cents
41.8 cents should be included as the cost of testing while guring out
theprice of chips
.
1.4 Test cost and selftest
Following Example 1.2 of the book (pp. 1011), we obtainATE purchase
price = $1
.
2
M
+ 256

$3
,
000 = $1
.
968
M
Assuming a 20% per year linear rate of depreciation, a maintenance cost
of 2% of the price, and an annual operating cost of $0
.
5
M
,Running cost = $1
.
968
M

0
.
2 + $1
.
968
M

0
.
02 + $0
.
5
M
= $932
,
960
/year
Testing cost = $932
,
960365


24

3600 = 2
.
96
cents/second
Testing cost of the selftest design is 2.96 cents per second, down
from4.56 cents per second calculated in Example 1.2
1.5 Test complexity
Consider a cube of side
d
. The number of transistors (
N
t
) is proportional to thevolume
d
3
, and the number of pins (
N
p
) is proportional to the surface area 6
d
2
.Thus, the Rents rule for the cube can be expressed as,
N
p
=
K

N
t
2
/
3
where
K
is a constant, which depends on such technology parameters as the
minimum feature spacing. For simplicity, we will assume that this
constant is the samefor the at and cubic chips. Following Example 1.3
(pp. 1213 of book), we de nethe test complexity,
TC
, as transistors per pin, or
TC
=
N
t
/N
p
. For the cube,
TC
cube
=
N
t
N
p
=
N
t

KN
t
2
/
3
= 1
K N
t
1
/
3
Solution Manual V1.4
c
M. L. Bushnell and V. D. Agrawal
For Teachers only
Page 3
Using the Rents rule for a at chip (Equation 1.5 on page 13 of book),
we obtain
TC
square
=
N
t
KN
t
1
/
2
= 1
K N
t
1
/
2
Therefore,
TC
square
TC
cube
=
N
t
1
/
6
This ratio of test complexities continues to increase as the number of
transistors (
N
t
)on the VLSI device grows. For example, for
N
t
= 1
million
, the squarechip testcomplexity is ten times greater than that of the
cubicdevice.
The test problemof the cubic con guration is less complex than that for
the at chip.

Note
: Although chips at present are not designed as threedimensional
objects,threedimensional packages and interconnects are in use. An
interested reader maysee the article: H. Goldstein, Packages Go Vertical,
IEEE Spectrum
, vol. 38,no. 8, pp. 4651, August 2001. Recently, Matrix Semiconductor
announced plansto produce a threedimensional memory chip. See, Adding
a Third Dimension toChips,
Computer
, vol. 35, no. 3, p. 29, March 2002.
Solution Manual V1.4
c
M. L. Bushnell and V. D. Agrawal
For Teachers only
Page 4
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<#>
Chapter 2: VLSI Testing Process and Test Equipment
2.1 Test types
To reduce the warranty and product liability costs, the manufacturer
must adopt athorough but coste ective test plan. A low failure rate,
which may be as low as 100parts per million, means that among one
million chips shipped by the manufacturerthere should be no more than
100 defective chips. A suitable test strategy requiresadjustments to
tests as the production ramps up. A realistic plan is as follows:

Initial production: The manufacturer uses parametric tests and vector


tests,the latter with coverage in the 95100% stuckat fault range. For
highspeedmicroprocessor chips, atspeed critical path tests are run.
The chips shouldbe subjected to burnin test for infant mortality.

Matured production: If burnin failures are lower than the required


defect levelthen that test is eliminated or reduced to a sample basis.
Any eld returnsare retested by the manufacturing tests. If these pass
then the manufacturingtests are augmented, when necessary, by
customersupplied tests.

Test optimization: Tests are optimized to reduce the manufacturing


cost.First, test sequences that fail a larger number of devices are
moved to thebeginning. Second, test sequences that do not fail any
devices are dropped.Such modi cations change the emphasis from detection of
modeled faults
todetection of actual
defects
.

Process monitoring: Once the chip goes into highvolume production,


themanufacturing process and the outgoing product (chips) should be
monitored to keep any variations within
statistical limits
. This means that various parameters, such as metal resistivity,
polysilicon conductivity, transistorparameters, etc., should be within
their threesigma range (
average

3


standard deviation
). Any excursions outside such a range are immediatelydiagnosed and the
causes remedied.
2.2 Contact test
Assume a diode drop of 0
.
7
V
. Then, the pin voltage range for contact test is givenby:Upper range :
V
pin
= 0
V

0
.
7
V

100
A

2000=

0
.
9
V
Lower range :
V
pin
= 0
V

0
.
7
V

250
A

2000=

1
.
2
V
2.3 Setup time test
To test a setup time,
t
set

up
= 360
ps
, apply the following waveforms to the chip (aclockto
Q
delay of 400

ps
is assumed):
Solution Manual V1.4
c
M. L. Bushnell and V. D. Agrawal
For Teachers only
Page 5
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ps MC Q CLK D
400360
ps
450
ps Measure Q Inputs Output
At an interval of 450
ps
after the rising
CLK
edge, measure
Q
on the ATE.If
Q
= 1, the device passes, otherwise it fails. Using
MS
instead of
MC
, repeatthe above waveform sequence, but with
D
inverted and the expected
Q
signal alsoinverted. At an interval of 450
s
after the rising
CLK
edge, again measure
Q
onthe ATE. If
Q
= 0, the device passes, otherwise it fails. The same waveforms
areapplied simultaneously to all ve
D
lines, and ve simultaneous measurements aremade on the ve
Q
lines.
2.4 Hold time test
To test a hold time,
t
hold
= 120
ps
, apply the following waveforms to the chip (aclockto
Q
delay of 400

ps
is assumed):
400
ps MC Q CLK D Output
120
ps
400
ps Inputs Measure Q ps
450
At an interval of 120
ps
after the rising
CLK
edge, we lower the
D
line. If
Q
= 1450
ps
after the rising
CLK
edge, the device passes, otherwise it fails. Using
MS
instead of
MC
, repeat the above waveform sequence, but with
D
inverted and theexpected
Q
signal also inverted. At an interval of 450
s
after the rising
CLK
edge,again measure
Q
on the ATE. If
Q
= 0, the device passes, otherwise it fails. Thesame waveforms are
applied simultaneously to all ve
D
lines, and ve simultaneousmeasurements are made on the ve
Q
lines.
Solution Manual V1.4
c
M. L. Bushnell and V. D. Agrawal
For Teachers only
Page 6
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2.5 Threshold test
Perform the threshold test as given on page 32 of the book, but with the
followingchanges: Assume a 5

V
supply, and perform binary search to nd
V
IL
and
V
IH
. Thefollowing procedure determines
V
IL
:
Incorrect Incorrect Incorrect Incorrect Incorrect Incorrect Incorrect Incorrect
Read output pin.
Correct Correct Correct Correct Correct Correct Correct Correct
input pin and a propagating pattern.
Read input voltage as V If it is 0.8V or greater,the chip passes.
IL
Read the expected output
Correct Incorrect
Write a 1.25V signal to theSubtract 0.6V to input pin.Read output
pin.Subtract 0.3V to input pin.Read output pin.Read output pin.Subtract
0.1V to input pin.Read output pin.Subtract 0.15V to input pin.Add 0.6V
to input pin..Read output pin.Read output pin.Add 0.1V to input pin.Add
0.15V to input pin.Add 0.3V to input pin.Read output pin.
The advantage of this procedure is that it greatly speeds up the test.
The testfor
V
IH
is analogous.
Solution Manual V1.4
c
M. L. Bushnell and V. D. Agrawal
For Teachers only
Page 7
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Chapter 3: Test Economics and Product Quality
3.1 Economic decision
We start with the following formula for the price of the car deriven by
John (Equation 3.2 on page 38 of the book):
P
= 20
,
000 + 20
,
000
n dollars
where
n
is the number of breakdowns per 15,000 miles since Johns car is
driven15,000 miles in a year. Because Laura drives only 5,000 miles per
year, her car isexpected to have
n/

3 breakdowns per year. Assuming a linear depreciation to zerovalue over


20 years and an average repair cost of $250 per breakdown, the
annualcost of driving is
C
=
P
20 +
K
+ 250
n/
3
dollars
= 1
,
000 + 1
,
000
n
+
K
+ 250
n/
3
dollars
where
K
is the cost of gasoline and regular maintenance, assumed to be the
samefor all models. To minimize this cost, we write
dC dn
=

1
,
000
n
2
+ 2503 = 0 or
n
=

12This is a minimum because


d
2
C dn
2
>
0. The price of a car for minimum transportationcost is,
P
= 20
,
000 + 20
,
000

12= 25
,
774
dollars
Laura should invest in a car priced around 25,774 dollars
.

3.2 Economic decision


(a) Let
x
be the daily wages of a technician and
c
be the cost of components on aboard. When
n
technicians work in the assembly shop, the cost of one board is,
C
(
n
) =
Warehouse costn
+
technician
s wages
+
component cost
+
workspace cost
= 10
,
000
n
+
x
+
c
+ 500
n
2
n
To minimize this cost, we write
dC
(
n
)
dn
=

10
,
000
n
2
+ 1
,
000
n
= 0 or
n
=

20 = 4
.
47
Solution Manual V1.4
c

M. L. Bushnell and V. D. Agrawal


For Teachers only
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