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8-bit Atmel Microcontroller with 8KB In-System Programmable Flash ATmega8A Features • High-performance, Low-power

8-bit Atmel Microcontroller with 8KB In-System Programmable Flash

ATmega8A

Features

High-performance, Low-power Atmel ® AVR ® 8-bit Microcontroller

Advanced RISC Architecture

– 130 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16MIPS Throughput at 16MHz

– On-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments

– 8KBytes of In-System Self-programmable Flash program memory

– 512Bytes EEPROM

– 1KByte Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85C/100 years at 25C (1)

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Programming Lock for Software Security

Atmel QTouch® library support

– Capacitive touch buttons, sliders and wheels

– Atmel QTouch and QMatrix acquisition

– Up to 64 sense channels

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Three PWM Channels

– 8-channel ADC in TQFP and QFN/MLF package

• Eight Channels 10-bit Accuracy

– 6-channel ADC in PDIP package

• Six Channels 10-bit Accuracy

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby

I/O and Packages

– 23 Programmable I/O Lines

– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF

Operating Voltages

– 2.7 - 5.5V

– 0 - 16MHz

Power Consumption at 4MHz, 3V, 25C

– Active: 3.6mA

– Idle Mode: 1.0mA

– Power-down Mode: 0.5µA

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Pin Configurations

(AIN1) PD7

(MISO) PB4

(MOSI/OC2) PB3

(ICP1) PB0

(AIN0) PD6

(T1) PD5

(SS/OC1B) PB2

(OC1A) PB1

Figure 1-1.

PB0 (AIN0) PD6 (T1) PD5 (SS/OC1B) PB2 (OC1A) PB1 Figure 1-1. Pinout ATmega8A PDIP    

Pinout ATmega8A

PDIP

 
   
 

(RESET) PC6

1 28

PC5 (ADC5/SCL)

(RXD) PD0

2 27

PC4 (ADC4/SDA)

(TXD) PD1

3 26

PC3 (ADC3)

(INT0) PD2

4 25

PC2 (ADC2)

(INT1) PD3

5 24

PC1 (ADC1)

(XCK/T0) PD4

6 23

PC0 (ADC0)

VCC

7 22

GND

GND

8 21

AREF

(XTAL1/TOSC1) PB6

9 20

AVCC

(XTAL2/TOSC2) PB7

10 19

PB5 (SCK)

(T1) PD5

11 18

PB4 (MISO)

(AIN0) PD6

12 17

PB3 (MOSI/OC2)

(AIN1) PD7

13 16

PB2 (SS/OC1B)

(ICP1) PB0

14 PB1 (OC1A)

15

(INT1) PD3

(XCK/T0) PD4

GND

VCC

GND

VCC

(XTAL1/TOSC1) PB6

(XTAL2/TOSC2) PB7

(INT1) PD3

(XCK/T0) PD4

GND

VCC

GND

VCC

(XTAL1/TOSC1) PB6

(XTAL2/TOSC2) PB7

TQFP Top View

1 24 2 23 3 22 4 21 5 20 6 19 7 18 8
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
(T1) PD5
32
(AIN0) PD6
9
10
PD2 (INT0)
31
PD1 (TXD)
(AIN1) PD7
11
12
30
29
PD0 (RXD)
(ICP1) PB0
PC6 (RESET)
(OC1A) PB1
13
14
28
27
PC5 (ADC5/SCL)
(SS/OC1B) PB2
PC4 (ADC4/SDA)
(MOSI/OC2) PB3
15
16
26
PC3 (ADC3)
(MISO) PB4
25
PC2 (ADC2)

PC1 (ADC1)

PC0 (ADC0)

ADC7

GND

AREF

ADC6

AVCC

PB5 (SCK)

MLF Top View

1 24 PC1 (ADC1) 2 23 PC0 (ADC0) 3 22 ADC7 4 21 GND 5
1
24
PC1 (ADC1)
2
23
PC0 (ADC0)
3
22
ADC7
4
21
GND
5
20
AREF
6
19
ADC6
7
18
AVCC
8
17
PB5 (SCK)
NOTE:
9
10
32
PD2 (INT0)
31
PD1 (TXD)
11
12
30
29
PD0 (RXD)
PC6 (RESET)
13
14
28
27
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
15
16
26
PC3 (ADC3)
25
PC2 (ADC2)

The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB.

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2.

Overview

The Atmel ® AVR ® ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8A achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram XTAL1 RESET PC0 - PC6 PB0 - PB7 VCC XTAL2 PORTC
Figure 2-1.
Block Diagram
XTAL1
RESET
PC0 - PC6
PB0 - PB7
VCC
XTAL2
PORTC DRIVERS/BUFFERS
PORTB DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
PORTB DIGITAL INTERFACE
GND
MUX &
ADC
TWI
ADC
INTERFACE
AGND
AREF
TIMERS/
OSCILLATOR
PROGRAM
STACK
COUNTERS
COUNTER
POINTER
PROGRAM
INTERNAL
SRAM
FLASH
OSCILLATOR
INSTRUCTION
WATCHDOG
GENERAL
OSCILLATOR
REGISTER
TIMER
PURPOSE
REGISTERS
X
INSTRUCTION
MCU CTRL.
Y
DECODER
& TIMING
Z
CONTROL
INTERRUPT
LINES
UNIT
ALU
STATUS
AVR CPU
EEPROM
REGISTER
PROGRAMMING
SPI
USART
LOGIC
+ COMP.
- INTERFACE
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
COMP. - INTERFACE PORTD DIGITAL INTERFACE PORTD DRIVERS/BUFFERS PD0 - PD7 ATmega8A [DATASHEET] 8159E–AVR–02/2013 3

PD0 - PD7

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The Atmel ® AVR ® AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega8A provides the following features: 8K bytes of In-System Programmable Flash with Read-While- Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial pro- grammable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with 10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asyn- chronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up com- bined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash Program mem- ory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash Section will con- tinue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embed- ded control applications.

The Atmel AVR ATmega8A is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program simulators and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buf- fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1 input for the Asyn- chronous Timer/Counter2 if the AS2 bit in ASSR is set.

input for the Asyn- chronous Timer/Counter2 if the AS2 bit in ASSR is set. ATmega8A [DATASHEET]

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The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 56 and “System Clock and Clock Options” on page 24.

2.2.4 Port C (PC5:PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buf- fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

2.2.5 PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 dif- fer from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 26-3 on page 228. Shorter pulses are not guaranteed to generate a Reset.

The various special features of Port C are elaborated on page 59.

2.2.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buf- fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8A as listed on page 61.

2.2.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 26-3 on page 228. Shorter pulses are not guaranteed to generate a reset.

2.2.8 AV CC AV CC is the supply voltage pin for the A/D Converter, Port C (3:0), and ADC (7:6). It should be externally connected to V CC , even if the ADC is not used. If the ADC is used, it should be connected to V CC through a low-pass filter. Note that Port C (5:4) use digital supply voltage, V CC .

2.2.9 AREF AREF is the analog reference pin for the A/D Converter.

2.2.10 ADC7:6 (TQFP and QFN/MLF Package Only) In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels.

pins are powered from the analog supply and serve as 10-bit ADC channels. ATmega8A [DATASHEET] 8159E–AVR–02/2013

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3.

Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

Note:

1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

5. About Code Examples

This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

6. Capacitive touch sensing

The Atmel ® QTouch ® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR ® microcontrollers. The QTouch Library includes support for the QTouch and QMatrix ® acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Micro- controller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states.

The QTouch Library is FREE and downloadable from the Atmel website at the following location:

www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website.

Library User Guide - also available for download from the Atmel website. ATmega8A [DATASHEET] 8159E–AVR–02/2013 6

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7.

AVR CPU Core

7.1

Overview

This section discusses the Atmel ® AVR ® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Figure 7-1.

Block Diagram of the AVR MCU Architecture

Data Bus 8-bit Program Status Flash Counter and Control Program Memory 32 x 8 General
Data Bus 8-bit
Program
Status
Flash
Counter
and Control
Program
Memory
32 x 8
General
Purpose
Registrers
Interrupt
Unit
Instruction
Register
SPI
Unit
Instruction
Watchdog
Decoder
Timer
ALU
Analog
Comparator
Control Lines
i/O Module1
Data
i/O Module 2
SRAM
i/O Module n
EEPROM
I/O Lines
Direct Addressing
Indirect Addressing

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two oper- ands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

are the 16-bit X-, Y-, and Z-register, described later in this section. ATmega8A [DATASHEET] 8159E–AVR–02/2013 7

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The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot program section and the Application program section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack

is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total

SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before sub-

routines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in

the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the

priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Reg- ister File, 0x20 - 0x5F.

7.2 Arithmetic Logic Unit – ALU

The high-performance Atmel ® AVR ® ALU operates in direct connection with all the 32 general purpose working reg- isters. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

7.3 Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

7.3.1 SREG – The AVR Status Register

Bit

7

6

5

4

3

2

1

0

I

T

H

S

V

N

Z

C

SREG

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ATmega8A [DATASHEET] 8159E–AVR–02/2013

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• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the inter- rupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the Instruction Set Reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the oper- ated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Descrip- tion” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

7.4 General Purpose Register File

The Register File is optimized for the Atmel ® AVR ® Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input.

• Two 8-bit output operands and one 8-bit result input.

• Two 8-bit output operands and one 16-bit result input.

• One 16-bit output operand and one 16-bit result input.

Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.

shows the structure of the 32 general purpose working registers in the CPU. ATmega8A [DATASHEET] 8159E–AVR–02/2013

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Figure 7-2.

AVR CPU General Purpose Working Registers

 

7

0

Addr.

R0

0x00

R1

0x01

R2

0x02

R13

0x0D

General

R14

0x0E

Purpose

R15

0x0F

Working

R16

0x10

Registers

R17

0x11

R26

0x1A

X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte

R27

0x1B

R28

0x1C

R29

0x1D

R30

0x1E

R31

0x1F

Most of the instructions operating on the Register File have direct access to all registers, and most of them are sin- gle cycle instructions.

As shown in Figure 7-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.

7.4.1 The X-register, Y-register and Z-register The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as described in Figure 7-3.

Figure 7-3.

The X-, Y- and Z-Registers

 

15

XH

XL

0

X-register

7

0

7

0

R27 (0x1B)

R26 (0x1A)

15

YH

YL

0

Y-register

7

0

7

0

R29 (0x1D)

R28 (0x1C)

15

ZH

ZL

0

Z-register

7

0

7

0

R31 (0x1F)

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic incre- ment, and automatic decrement (see the Instruction Set Reference for details).

7.5 Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory

Note that the Stack is implemented as growing from higher to lower memory ATmega8A [DATASHEET] 8159E–AVR–02/2013

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locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.

The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure 8-2 on page 16.

See Table 7-1 for Stack Pointer details.

Table 7-1.

Stack Pointer instructions

Instruction

Stack pointer

Description

PUSH

Decremented by 1

Data is pushed onto the stack

CALL

Decremented by 2

Return address is pushed onto the stack with a subroutine call or interrupt

ICALL

RCALL

 

POP

Incremented by 1

Data is popped from the stack

RET

Incremented by 2

Return address is popped from the stack with return from subroutine or return from interrupt

RETI

The Atmel ® AVR ® Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

7.5.1 SPH and SPL – Stack Pointer High and Low Register

Bit

15

14

13

12

11

10

9

8

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

SPH

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

SPL

76543210

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

00000000

7.6 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The Atmel ® AVR ® CPU is driven by the CPU clock clk CPU , directly generated from the selected clock source for the chip. No internal clock division is used.

Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

for functions per cost, functions per clocks, and functions per power-unit. ATmega8A [DATASHEET] 8159E–AVR–02/2013 11

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11

Figure 7-4.

The Parallel Instruction Fetches and Instruction Executions

clk

CPU

1st Instruction Fetch

1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch

T1 T2 T3 T4
T1
T2
T3
T4

Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 7-5.

Single Cycle ALU Operation

clk CPU Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

T1 T2 T3 T4
T1
T2
T3
T4

7.7 Reset and Interrupt Handling

The Atmel ® AVR ® provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Mem- ory Programming” on page 207 for details.

The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of Vectors is shown in “Interrupts” on page 44. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the boot Flash sec- tion by setting the Interrupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 44 for more information. The Reset Vector can also be moved to the start of the boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 194.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user soft- ware can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt

is vectored to the actual Interrupt Vector in order to execute the interrupt ATmega8A [DATASHEET] 8159E–AVR–02/2013

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handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writ- ing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not nec- essarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

 
 

in r16, SREG

; store SREG value

cli

; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE

out SREG, r16

; restore SREG value (I-bit)

C

Code Example

 
 

char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pend- ing interrupts, as shown in the following example.

Assembly Code Example

 

sei ; set global interrupt enable

sleep;

enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C

Code Example

 
 

_SEI(); /* set global interrupt enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */

interrupt */ /* note: will enter sleep before any pending interrupt(s) */ ATmega8A [DATASHEET] 8159E–AVR–02/2013 13

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7.7.1 Interrupt Response Time The interrupt execution response for all the enabled Atmel ® AVR ® interrupts is four clock cycles minimum. After four clock cycles, the Program Vector address for the actual interrupt handling routine is executed. During this 4-clock cycle period, the Program Counter is pushed onto the Stack. The Vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the I-bit in SREG is set.

Stack, the Stack Pointer is incremented by 2, and the I-bit in SREG is set. ATmega8A

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8.

AVR Memories

8.1 Overview

This section describes the different memories in the Atmel ® AVR ® ATmega8A. The AVR architecture has two main memory spaces, the Data memory and the Program Memory space. In addition, the ATmega8A features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

8.2 In-System Reprogrammable Flash Program Memory

The ATmega8A contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16- or 32-bits wide, the Flash is organized as 4K x 16 bits. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8A Program Counter (PC) is 12 bits wide, thus addressing the 4K Program memory locations. The operation of Boot Program section and associated Boot Lock Bits for software protection are described in detail in “Boot Loader Support – Read-While- Write Self-Programming” on page 194. “Memory Programming” on page 207 contains a detailed description on Flash Programming in SPI- or Parallel Programming mode.

Constant tables can be allocated within the entire Program memory address space (see the LPM – Load Program memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 11.

Figure 8-1.

“Instruction Execution Timing” on page 11 . Figure 8-1. Program Memory Map Application Flash Section Boot

Program Memory Map

Application Flash Section Boot Flash Section
Application Flash Section
Boot Flash Section

$000

$FFF

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8.3

SRAM Data Memory

Figure 8-2 shows how the Atmel ® AVR ® ATmega8A SRAM Memory is organized.

The lower 1120 Data memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 1024 locations address the internal data SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indi- rect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z- register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega8A are all accessible through all these addressing modes. The Register File is described in “General Pur- pose Register File” on page 9.

Figure 8-2.

Data Memory Map

Register File

Data Address Space

R0

$0000

R1

$0001

R2

$0002

R29

$001D

R30

$001E

R31

$001F

I/O Registers

$00

$0020

$01

$0021

$02

$0022

$3D

$005D

$3E

$005E

$3F

$005F

Internal SRAM

$0060

$0061

$045E

$045F

8.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk CPU cycles as described in Figure 8-3.

is performed in two clk C P U cycles as described in Figure 8-3 . ATmega8A

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Figure 8-3.

On-chip Data SRAM Access Cycles

clk

CPU

Address

Data

WR

Data

RD

8.4 EEPROM Data Memory

T1 T2 T3 Compute Address Address Valid WriteRead
T1
T2
T3
Compute Address
Address Valid
WriteRead
Memory T1 T2 T3 Compute Address Address Valid WriteRead Memory Vccess Instruction N e x t

Memory Vccess Instruction

Next Instruction

The Atmel ® AVR ® ATmega8A contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described bellow, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

“Memory Programming” on page 207 contains a detailed description on EEPROM Programming in SPI- or Parallel Programming mode.

8.4.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 8-4 on page 20. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as mini- mum for the clock frequency used. See “Preventing EEPROM Corruption” on page 22. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

8.5 I/O Memory

The I/O space definition of the ATmega8A is shown in “” on page 301.

All ATmega8A I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these regis- ters, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must

the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must ATmega8A [DATASHEET]

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be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

8.6 Register Description

8.6.1 EEARH and EEARL – The EEPROM Address Register

Bit

15

14

13

12

11

10

9

8

EEAR8

EEARH

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

EEARL

76543210

Read/Write

R

R

R

R

R

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

X

XXXXXXXX

• Bits 15:9 – Res: Reserved Bits

These bits are reserved bits in the ATmega8A and will always read as zero.

• Bits 8:0 – EEAR8:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

8.6.2 EEDR – The EEPROM Data Register

Bit

7

6

5

4

3

2

1

0

MSB

           

LSB

EEDR

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

8.6.3 EECR – The EEPROM Control Register

Bit

7

6

5

4

3

2

1

0

EERIE

EEMWE

EEWE

EERE

EECR

Read/Write

R

R

R

R

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

X

0

• Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATmega8A and will always read as zero.

These bits are reserved bits in the ATmega8A and will always read as zero. ATmega8A [DATASHEET]

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• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero dis- ables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are cor- rectly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following pro- cedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software con- tains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” on page 194 for details about boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

it is neither possible to read the EEPROM, nor to change the EEAR Register. ATmega8A [DATASHEET]

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The calibrated Oscillator is used to time the EEPROM accesses. Table 8-4 lists the typical programming time for EEPROM access from the CPU.

Figure 8-4.

EEPROM Programming Time

Symbol

Number of Calibrated RC Oscillator Cycles (1)

Typ Programming Time

EEPROM Write (from CPU)

8448

8.5ms

Note:

Time EEPROM Write (from CPU) 8448 8.5ms Note: 1. Uses 1MHz clock, independent of CKSEL Fuse

1.

Uses 1MHz clock, independent of CKSEL Fuse settings.

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The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash boot loader is present in the soft- ware. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

;

Wait for completion of previous write

sbic EECR,EEWE rjmp EEPROM_write

Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17

;

Write data (r16) to data register out EEDR,r16

;

;

Write logical one to EEMWE

sbi EECR,EEMWE

Start eeprom write by setting EEWE sbi EECR,EEWE ret

;

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEWE))

 

;

/* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE);

}

/* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } ATmega8A [DATASHEET] 8159E–AVR–02/2013 21

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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

 

Wait for completion of previous write sbic EECR,EEWE

;

rjmp EEPROM_read

Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17

;

Start eeprom read by writing EERE sbi EECR,EERE

;

Read data from data register in r16,EEDR ret

;

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

 

/* Wait for completion of previous write */ while(EECR & (1<<EEWE))

;

/* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR;

}

8.6.4 EEPROM Write during Power-down Sleep Mode When entering Power-down sleep mode while an EEPROM write operation is active, the EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation is completed, the Oscillator continues running, and as a consequence, the device does not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down.

8.6.5 Preventing EEPROM Corruption During periods of low V CC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Second, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the

(BOD). If the detection level of the internal BOD does not match the ATmega8A [DATASHEET] 8159E–AVR–02/2013

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needed detection level, an external low V CC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

will be completed provided that the power supply voltage is sufficient. ATmega8A [DATASHEET] 8159E–AVR–02/2013 23

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9.

System Clock and Clock Options

9.1 Clock Systems and their Distribution

Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 32. The clock systems are detailed Figure 9-1.

Figure 9-1. Clock Distribution Asynchronous General I/O Flash and ADC CPU Core RAM Timer/Counter Modules
Figure 9-1.
Clock Distribution
Asynchronous
General I/O
Flash and
ADC
CPU Core
RAM
Timer/Counter
Modules
EEPROM
clk ADC
clk I/O
AVR Clock
clk CPU
Control Unit
clk ASY
clk FLASH
Reset Logic
Watchdog Timer
Source Clock
Watchdog Clock
Clock
Watchdog
Multiplexer
Oscillator
Timer/Counter
External RC
Crystal
Low-Frequency
Calibrated RC
Oscillator
Oscillator
External Clock
Oscillator
Crystal Oscillator
Oscillator

9.1.1 CPU Clock – clk CPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such mod- ules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

9.1.2 I/O Clock – clk I/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchronously when clk I/O is halted, enabling TWI address reception in all sleep modes.

I / O is halted, enabling TWI address reception in all sleep modes. ATmega8A [DATASHEET] 8159E–AVR–02/2013

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9.1.3

Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

9.1.4 Asynchronous Timer Clock – clk ASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. The Asynchronous Timer/Counter uses the same XTAL pins as the CPU main clock but requires a CPU main clock frequency of more than four times the Oscillator frequency. Thus, asynchronous operation is only available while the chip is clocked on the Internal Oscillator.

9.1.5 ADC Clock – clk ADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

9.2 Clock Sources

The device has the following clock source options, selectable by Flash Fuse Bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 9-1.

Device Clocking Options Select (1)

Device Clocking Option

CKSEL3:0

External Crystal/Ceramic Resonator

1111

- 1010

External Low-frequency Crystal

1001

External RC Oscillator

1000

- 0101

Calibrated Internal RC Oscillator

0100

- 0001

External Clock

0000

Note:

1.

For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator oper- ation before instruction execution starts. When the CPU starts from reset, there is as an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 9-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in “Typical Characteristics – TA = -40°C to 85°C”. The device is shipped with CKSEL = “0001” and SUT = “10” (1MHz Internal RC Oscillator, slowly rising power).

Table 9-2.

Number of Watchdog Oscillator Cycles

Typical Time-out (V CC = 5.0V)

Typical Time-out (V CC = 3.0V)

Number of Cycles

4.1 ms

4.3 ms

4K (4,096)

65 ms

69 ms

64K (65,536)

9.3 Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 9-2. Either a quartz crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator amplifier modes. When CKOPT is programmed, the Oscilla- tor output will oscillate a full rail-to-rail swing on the output. This mode is suitable when operating in a very noisy environment or when the output from XTAL2 drives a second clock buffer. This mode has a wide frequency range.

XTAL2 drives a second clock buffer. This mode has a wide frequency range. ATmega8A [DATASHEET] 8159E–AVR–02/2013

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When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces power consumption con- siderably. This mode has a limited frequency range and it cannot be used to drive other clock buffers.

For resonators, the maximum frequency is 8MHz with CKOPT unprogrammed and 16 MHz with CKOPT pro- grammed. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 9-3. For ceramic resonators, the capacitor values given by the manufacturer should be used.

Figure 9-2.

Crystal Oscillator Connections

C2 XTAL2 C1 XTAL1 GND
C2
XTAL2
C1
XTAL1
GND

The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3:1 as shown in Table 9-3.

Table 9-3.

Crystal Oscillator Operating Modes

   

Frequency

Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF)

CKOPT

CKSEL3:1

Range(MHz)

1

101

(1)

0.4

- 0.9

 

1

 

110 0.9

- 3.0

12

- 22

1

 

111 3.0

- 8.0

12

- 22

0

101, 110, 111

1.0

12

- 22

Note:

1.

This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in Table 9-4.

with the SUT1:0 Fuses select the start-up times as shown in Table 9-4 . ATmega8A [DATASHEET]

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Table 9-4.

Start-up Times for the Crystal Oscillator Clock Selection

   

Start-up Time

Additional Delay from Reset (V CC = 5.0V)

   

from Power-down

CKSEL0

SUT1:0

and Power-save

Recommended Usage

0

00

258

CK (1)

4.1

ms

Ceramic resonator, fast rising power

0

01

258

CK (1)

65

ms

Ceramic resonator, slowly rising power

   

1K CK (2)

 

Ceramic resonator, BOD

0

10

 

enabled

0

11

1K CK (2)

4.1

ms

Ceramic resonator, fast rising power

1

00

1K CK (2)

65

ms

Ceramic resonator, slowly rising power

   

16K CK

 

Crystal Oscillator, BOD

1

01

 

enabled

1

10

16K CK

4.1

ms

Crystal Oscillator, fast rising power

1

11

16K CK

65

ms

Crystal Oscillator, slowly rising power

Notes:

1.

These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2.

These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency sta- bility at start-up is not important for the application.

9.4 Low-frequency Crystal Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The crystal should be connected as shown in Figure 9-2. By pro- gramming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The internal capacitors have a nominal value of 36 pF.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 9-5.

Table 9-5.

Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

SUT1:0

Start-up Time from Power-down and Power-save

Additional Delay from Reset (V CC = 5.0V)

Recommended Usage

00

1K CK (1)

4.1 ms

Fast rising power or BOD enabled

01

1K CK (1)

65

ms

Slowly rising power

10

32K CK

65

ms

Stable frequency at start-up

11

 

Reserved

Note:

1.

These options should only be used if frequency stability at start-up is not important for the application.

9.5 External RC Oscillator

For timing insensitive applications, the external RC configuration shown in Figure 9-3 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, thereby removing the need for an exter- nal capacitor.

XTAL1 and GND, thereby removing the need for an exter- nal capacitor. ATmega8A [DATASHEET] 8159E–AVR–02/2013 27

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Figure 9-3.

External RC Configuration

VCC

Figure 9-3. External RC Configuration V CC R C NC XTAL2 XTAL1 GND The Oscillator can

R

C

Figure 9-3. External RC Configuration V CC R C NC XTAL2 XTAL1 GND The Oscillator can
Figure 9-3. External RC Configuration V CC R C NC XTAL2 XTAL1 GND The Oscillator can

NC

XTAL2

XTAL1

GND

The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3:0 as shown in Table 9-6.

Table 9-6.

External RC Oscillator Operating Modes

CKSEL3:0

Frequency Range (MHz)

0101

0.1

- 0.9

0110

0.9

- 3.0

0111

3.0

- 8.0

1000

8.0 - 12.0

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 9-7.

Table 9-7.

Start-up Times for the External RC Oscillator Clock Selection

SUT1:0

Start-up Time from Power-down and Power-save

Additional Delay from Reset (V CC = 5.0V)

Recommended Usage

00

18

CK

BOD enabled

01

18

CK

4.1

ms

Fast rising power

10

18

CK

65 ms

Slowly rising power

11

6 CK (1)

4.1

ms

Fast rising power or BOD enabled

Note:

1 ) 4.1 ms Fast rising power or BOD enabled Note: 1. This option should not

1.

This option should not be used when operating close to the maximum frequency of the device.

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9.6

Calibrated Internal RC Oscillator

The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0MHz clock. All frequencies are nominal values at 5V and 25C. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 9-8. If selected, it will operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clock option. During reset, hardware loads the 1MHz calibration byte into the OSC- CAL Register and thereby automatically calibrates the RC Oscillator. At 5V, 25C and 1.0MHz Oscillator frequency selected, this calibration gives a frequency within ± 3% of the nominal frequency. Using run-time calibration meth- ods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 1% accuracy at any given V CC and Temperature. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 209.

Table 9-8.

Internal Calibrated RC Oscillator Operating Modes

CKSEL3:0

Nominal Frequency (MHz)

0001

(1)

1.0

0010

2.0

0011

4.0

0100

8.0

Note:

1.

The device is shipped with this option selected.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 9-9. PB6 (XTAL1/TOSC1) and PB7(XTAL2/TOSC2) can be used as either general I/O pins or Timer Oscillator pins:

Table 9-9.

Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

SUT1:0

Start-up Time from Power-down and Power- save

Additional Delay from Reset (V CC = 5.0V)

Recommended Usage

 

00 6

CK

BOD enabled

 

01 6

CK

4.1 ms

Fast rising power

10

(1)

6

CK

65 ms

Slowly rising power

11

 

Reserved

Note:

65 ms Slowly rising power 11   Reserved Note: 1. The device is shipped with this

1.

The device is shipped with this option selected.

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9.7

External Clock

To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 9-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, and XTAL2 and GND.

Figure 9-4.

External Clock Drive Configuration

EXTERNAL CLOCK SIGNAL
EXTERNAL
CLOCK
SIGNAL

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-10.

Table 9-10.

Start-up Times for the External Clock Selection

SUT1:0

Start-up Time from Power-down and Power-save

Additional Delay from Reset (V CC = 5.0V)

Recommended Usage

00

6

CK

BOD enabled

01

6

CK

4.1 ms

Fast rising power

10

6

CK

65 ms

Slowly rising power

11

 

Reserved

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency.

9.8 Timer/Counter Oscillator

For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not recommended.

Note:

an external clock source to TOSC1 is not recommended. Note: The Timer/Counter Oscillator uses the same

The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36 pF.

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9.9

Register Description

9.9.1 OSCCAL – Oscillator Calibration Register

Bit

7

6

5

4

3

2

1

0

CAL7

CAL6

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

OSCCAL

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

Device Specific Calibration Value

 

• Bits 7:0 – CAL7:0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the Internal Oscillator to remove process variations from the Oscillator frequency. During Reset, the 1MHz calibration value which is located in the signature row High byte (address 0x00) is automatically loaded into the OSCCAL Register. If the internal RC is used at other frequencies, the calibration values must be loaded manually. This can be done by first reading the signature row by a program- mer, and then store the calibration values in the Flash or EEPROM. Then the value can be read by software and loaded into the OSCCAL Register. When OSCCAL is zero, the lowest available frequency is chosen. Writing non- zero values to this register will increase the frequency of the Internal Oscillator. Writing 0xFF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 9-11.

Table 9-11.

Internal RC Oscillator Frequency Range

OSCCAL Value

Min Frequency in Percentage of Nominal Frequency (%)

Max Frequency in Percentage of Nominal Frequency (%)

0x00

50

100

0x7F

75

150

0xFF

100

200

(%) 0x00 50 100 0x7F 75 150 0xFF 100 200 ATmega8A [DATASHEET] 8159E–AVR–02/2013 31

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10. Power Management and Sleep Modes

10.1 Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.

Figure 9-1 on page 24 presents the different clock systems in the ATmega8A, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 10-1 shows the different clock options and their wake-up sources.

Table 10-1.

Active Clock Domains and Wake-up Sources in the Different Sleep Modes

 

Active Clock Domains

 

Oscillators

 

Wake-up Sources

 

Sleep Mode

clk CPU

clk FLASH

clk IO

clk ADC

 

clk ASY

Main Clock Source Enabled

 

Timer Osc. Enabled

 

INT1/ INT0

TWIAddress

Match

 

Timer2

SPM/ EEPROM Ready

ADC

Other I/O

Idle

   

X

X

X

X

X

(2)

X

X

X

 

XXX

 

ADC Noise

       

XX

X

X

(2)

X

(3)

X

X

 

XX

 

Reduction

   

Power-down

             

X

(3)

X

       

Power-save

       

X

(2)

 

X

(2)

X

(3)

X

X

(2)

     

Standby (1)

         

X

 

X

(3)

X

       

Notes:

1.

External Crystal or resonator selected as clock source.

2.

If AS2 bit in ASSR is set.

3.

Only level interrupt INT1 and INT0.

To enter any of the five sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be activated by the SLEEP instruction. See Table 10- 1 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and resumes execution from the instruc- tion following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

Note that the Extended Standby mode present in many other AVR MCUs has been removed in the ATmega8A, as the TOSC and XTAL inputs share the same physical pins.

10.2 Idle Mode

When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and

Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and ATmega8A [DATASHEET] 8159E–AVR–02/2013 32

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the interrupt system to continue operating. This sleep mode basically halts clk CPU and clk FLASH , while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conver- sion starts automatically when this mode is entered.

10.3 ADC Noise Reduction Mode

When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk I/O , clk CPU , and clk FLASH , while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, or an external level interrupt on INT0 or INT1, can wake up the MCU from ADC Noise Reduction mode.

10.4 Power-down Mode

When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the External Oscillator is stopped, while the external interrupts, the Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, or an external level interrupt on INT0 or INT1, can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 64 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in “Clock Sources” on page 25.

10.5 Power-save Mode

When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 is clocked asynchronously, i.e. the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK, and the global interrupt enable bit in SREG is set.

If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power- save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in Power-save mode if AS2 is 0.

This sleep mode basically halts all clocks except clk ASY , allowing operation only of asynchronous modules, includ- ing Timer/Counter 2 if clocked asynchronously.

modules, includ- ing Timer/Counter 2 if clocked asynchronously. ATmega8A [DATASHEET] 8159E–AVR–02/2013 33

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10.6

Standby Mode

When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in 6 clock cycles.

10.7 Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

10.7.1 Analog-to-Digital Converter (ADC) If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to “Analog-to-Digital Converter” on page 182 for details on ADC operation.

10.7.2 Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 179 for details on how to configure the Analog Comparator.

10.7.3 Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detec- tor is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detec- tion” on page 38 for details on how to configure the Brown-out Detector.

10.7.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detector, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Voltage Reference” on page 39 for details on the start-up time.

10.7.5 Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 40 for details on how to configure the Watchdog Timer.

10.7.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where the both the I/O clock (clk I/O ) and the ADC clock (clk ADC ) are stopped, the input buffers of the device will be disabled. This ensures that no power is con- sumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 53 for

to the section “Digital Input Enable and Sleep Modes” on page 53 for ATmega8A [DATASHEET] 8159E–AVR–02/2013

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details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V CC /2, the input buffer will use excessive power.

10.8 Register Description

10.8.1 MCUCR – MCU Control Register The MCU Control Register contains control bits for power management.

Bit

7

6

5

4

3

2

1

0

SE

SM2

SM1

SM0

ISC11

ISC10

ISC01

ISC00

MCUCR

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

• Bit 7 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is exe- cuted. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the execution of the SLEEP instruction.

• Bits 6:4 – SM2:0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 10-2.

Table 10-2.

Sleep Mode Select

SM2

SM1

SM0

Sleep Mode

0

0

0

Idle

0

0

1

ADC Noise Reduction

0

1

0

Power-down

0

1

1

Power-save

1

0

0

Reserved

1

0

1

Reserved

1

1

0

Standby (1)

Note:

0 1 Reserved 1 1 0 Standby ( 1 ) Note: 1. Standby mode is only

1.

Standby mode is only available with external crystals or resonators.

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11. System Control and Reset

11.1 Resetting the AVR

During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vec- tor. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the boot section or vice versa. The circuit diagram in Figure 11-1 shows the Reset Logic. Table 26-3 on page 228 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 25.

11.2 Reset Sources

The ATmega8A has four sources of Reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V POT ).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V CC is below the Brown-out Reset threshold (V BOT ) and the Brown-out Detector is enabled.

Reset threshold (V B O T ) and the Brown-out Detector is enabled. ATmega8A [DATASHEET] 8159E–AVR–02/2013

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Figure 11-1.

Reset Logic

DATA BUS MCU Control and Status Register (MCUCSR) Brown-Out BODEN Reset Circuit BODLEVEL Pull-up Resistor
DATA BUS
MCU Control and Status
Register (MCUCSR)
Brown-Out
BODEN
Reset Circuit
BODLEVEL
Pull-up Resistor
SPIKE
FILTER
Watchdog
Oscillator
Delay Counters
Clock
CK
TIMEOUT
Generator
CKSEL[3:0]
SUT[1:0]
PORF
BORF
EXTRF
WDRF

11.2.1 Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table

26-3 on page 228. The POR is activated whenever V CC is below the detection level. The POR circuit can be used

to trigger the Start-up Reset, as well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset

threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V CC rise.

The RESET signal is activated again, without any delay, when V CC decreases below the
The RESET signal is activated again, without any delay, when V CC decreases below the detection level.
Figure 11-2.
MCU Start-up, RESET Tied to V CC
V POT
V
CC
V RST
RESET
t
TIME-OUT
TOUT
INTERNAL
RESET
Tied to V CC V POT V CC V RST RESET t TIME-OUT TOUT INTERNAL RESET

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Figure 11-3.

MCU Start-up, RESET Extended Externally

V CC

RESET

TIME-OUT

INTERNAL

RESET

V POT V RST t TOUT
V POT
V RST
t TOUT

11.2.2 External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 26-3 on page 228) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V RST on its posi- tive edge, the delay counter starts the MCU after the time-out period t TOUT has expired.

Figure 11-4.

External Reset During Operation CC
External Reset During Operation
CC

11.2.3 Brown-out Detection ATmega8A has an On-chip Brown-out Detection (BOD) circuit for monitoring the V CC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V BOT+ = V BOT

+ V HYST /2 and V BOT- = V BOT - V HYST /2.

The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed), and V CC decreases to a value below the trigger level (V BOT- in Figure 11-5), the Brown-out Reset is immediately activated. When V CC increases above the trigger level (V BOT+ in Figure 11-5), the delay counter starts the MCU after the time-out period t TOUT has expired.

The BOD circuit will only detect a drop in V CC if the voltage stays below the trigger level for longer than t BOD given in Table 26-3 on page 228.

level for longer than t B O D given in Table 26-3 on page 228 .

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Figure 11-5.

Brown-out Reset During Operation

V CC

RESET

TIME-OUT

INTERNAL

RESET

V BOT+ V BOT- t TOUT
V BOT+
V BOT-
t TOUT

11.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period t TOUT . Refer to page 40 for details on operation of the Watchdog Timer.

Figure 11-6.

Watchdog Reset During Operation

CC
CC
CK
CK

11.3 Internal Voltage Reference

ATmega8A features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference.

11.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 26-3 on page 228. To save power, the reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODEN Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power con- sumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

to ensure that the reference is turned off before entering Power-down mode. ATmega8A [DATASHEET] 8159E–AVR–02/2013 39

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11.4

Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at V CC = 5V. See characterization data for typical values at other V CC levels. By controlling the Watchdog Timer pres- caler, the Watchdog Reset interval can be adjusted as shown in Table 11-7 on page 40. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega8A resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to “Watchdog Reset” on page 39.

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watch- dog is disabled. Refer to the description of the Watchdog Timer Control Register for details.

Figure 11-7. Watchdog Timer WATCHDOG OSCILLATOR
Figure 11-7.
Watchdog Timer
WATCHDOG
OSCILLATOR

11.5 Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing the Watchdog Timer configuration differs slightly between the safety levels. Separate procedures are described for each level.

Assembly Code Example

Separate procedures are described for each level. Assembly Code Example ATmega8A [DATASHEET] 8159E–AVR–02/2013 40

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WDT_off:

 

;

reset WDT

WDR

;

Write logical one to WDCE and WDE

in

r16, WDTCR

ori r16, (1<<WDCE)|(1<<WDE)

out WDTCR, r16

;

Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example