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Code No: B6801

Jawaharlal Nehru Technological University Hyderabad
M.Tech II Semester Regular Examinations September-2009
(Common to VLSI and Embedded Systems and
Embedded Systems and VLSI Design)

Time: 3 Hours Max. Marks: 60
Answer any Five Questions
All Questions Carry Equal Marks

1. a] Draw and explain the VLSI system design cycle flow chart.
b] Explain the process steps for nMOS fabrication process.

2. a] Discuss on aspects of MOS transistor Threshold voltage and Body effect.
b] Explain the design considerations of CMOS inverter with relevant circuit diagram
and transfer characteristics.

3. a] Explain the design rules for Wires of nMOS and CMOS circuits with suitable
b] What are the general CMOS logic-gate layout guidelines? Draw the layout
diagram of an inverter.

4. a] Draw the structure of a DCVS logic gate and give an example circuit for the
b] Explain the power consumption analysis of static complementary gates with the
aid suitable circuit diagram.

5. a] Explain the terms ‘Fan out’ and ‘Path delay’ relevant to combinational network
b] Perform the Power analysis of combinational logic networks with suitable

6. a] Explain about Power optimization and Design validation of sequential systems.
b] Draw the circuit which introduces signal skew and explain its operation with
timing diagrams.

7. a] Explain the terms ‘Power distribution’ and ‘Clock distribution’ with respect to
floor planning methods.
b] Explain with suitable example how the controller changes with the data path

8. a] Write notes on Layout synthesis and analysis.
b] Draw and explain the generic integrated circuit design flow.