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Code No: 54124/MT

M.Tech. I-Semester Examinations, February-2007.
CPLD AND FPGA ARCHITECTURE AND APPLICATIONS
(VLSI System Design)
Time: 3 hours Max. Marks: 60
All questions carry equal marks
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1.a) What is an erasable PROM/
b) Implement the logic functions
F1 = ( x1 + x3 )( x1 + x 2 )( x1 + x 2 + x 3 )
and F2 = ( x1 + x 3 )( x 1 + x 2 )( x1 + x 2 ) using a NOR – NOR PLA.

2.a) When is CPLD better suited than SPLD?
b) Implement the logic functions
F 1 = x1 x2 x 3 + x1 x 2 x 3
And F2 = x2 x 3 + x1 x 3 using a PAL

3.a) Describe the pass transistor switch in a FPGA.
b) Draw any sketch showing an FPGA programmed to implement a
switching function F. One pin should be used for F and there
should be several pins that are unused without changing the
programming of any switch that is turned on in the FPGA in your
figure, list other logic functions that can be implemented on the
unused pins.

4.a) Why is it that PLDs are better than LCAs where the number of
variables is large?
b) Describe the Xilinx 4000 series FPGAs.

5.a) Distinguish between combinational logic circuits and sequential
logic circuits.
b) Derive the state diagram for an FSM that has an input w and an
output Z. The machine has to generate 1 when the previous four
values of w are 1001 or 1111, otherwise Z = 0. Overlapping input
patterns are allowed.

6.a) The reduced state table of a sequential machine has 12 rows.
What is the minimum number of flip-flops needed to implement
the machine?
b) Using Rs flip-flops, design a counter which displays count in the
sequence 0,2,1,3,0,2,…

7.a) What is a shift register?
b) With the help of a suitable example, describe state machine design
centered around shift registers.

8. Write explanatory notes on:
(a) Petrinets (b) Mentor Graphics EDA tool (c) Multiplexers.
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