You are on page 1of 3

Code No: B6804

Jawaharlal Nehru Technological University Hyderabad
M. Tech II-Semester Regular Examinations September-2009
CPLD & FPGA ARCHITECTURE & APPLICATIONS
(VLSI & Embedded Systems and Embedded Systems & VLSI Design)
Time : 3 Hours Max. Marks: 60
Answer Any Five Questions
All Questions Carry Equal Marks
----

1.a] What are the differences between Xilinx 4000 series FPGA to 3000 series. Draw a
neat block diagram of 4000 series configurable logic block.
b] Draw a diagram showing the basic configuration and symbalogy for a PLD sum-
of-products away.

2.a] What is the purpose of the carry chain in a FLEX10K CPLD?
b] State the possible reset configurations of a MAX 700s macrocell.

3. For the given state graph; derive the simplified next state and output equations.
Use the following one-hot state assignment for flip flops
Q0Q1Q2Q3 : S 0 , 1000; S1 ; 0100; S 2 ; 0010; S3 ; 0001. How many 4000 series
CLDS required to implant there equations. What is the maximum clock rate for
this implementation if interconnect delay is 2 ns between CLDS.

Cont….2
Code No: B6804 ::2::

4. The SM charts for two linked state machines are given below. Complete timing
chart. Initially A=0 and B=1. Realize the two SM charts using a PLA and D flip-
flops.

5. The following SM chart is to be realized using PLA, 4 to 1 MUX, and a 3-bit
binary counter. Draw the block diagram of the system, make state assignment and
give PLA table.

Cont….3
Code No: B6804 ::3::

6. Design a binary multiplier using PAL, MUX and other logic gates.

7. Write a brief explanation of FSM top down design steps with an example.

8. Write a brief note on:
a) Design of digital(binary) counter using EDA tool.
b) AMD’s – CPLD (mach 1 to 5) feature.

---ooo---