You are on page 1of 2

Code No: B5503

Jawaharlal Nehru Technological University Hyderabad
M. Tech II-Semester Regular Examinations September – 2009
CPLD & FPGA ARCHITECTURE & APPLICATIONS
(Embedded Systems)
Time : 3 Hours Max. Marks: 60
Answer Any Five Questions
All Questions Carry Equal marks
----

1.a] Dynamic RAM technology offers considerable density improvements over static
RAM used in FPGAs. Explain and what are the limitations of DRAM in FPGA
used designs?
b] How do you provide a synchronizer circuit for an asynchronous input to a Xilinx
XC3000 design?

2.a] The Actel ACT1 FPGA uses the following circuit shown below. How would you
implement the function Y = A+B+C?

b] Mention three advantages of in-circuit reprogrammable FPGAs over fuse
programmable FPGAs.

3.a] What are the advantages in optimized reconfigurable all ways?
b] Draw a neat routing architecture of FLEX 8000 FPGA and briefly explain the
same.
Contd -2-
Code No: B5503 -2-

4. Design a sequence detector circuit which can detect 1111 sequence with overlap.
Realize the design using one-hot state machine.

5.a] What is meta stability? Discuss a case to explain meta stability.
b] What are the basic properties of petrivets of state machines.

6. Design a 4-bit parallel adder with carry look ahead principle. Realize it through
ASM charts with a PAL.

7. Design a 8:1 Mux using “FPGA advantage” EDA tool. Write code for the design
and realize its ASIC.

8. Write short notes on:
a. Linked state machines.
b. CYPRES FLASH 370 device technology.

--ooOoo--