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Exam 2 EE 371 Winter 1998

University of Washington
Department of Electrical Engineering

Name____________________________

To receive credit on a problem, you must show all of your work (as appropriate). Please state
any assumptions.


1. (25) We wish to have a counter that operates according to the following sequence,
a. Please draw a timing diagram for such a counter.


b. What is the period of the counter

8

c. Please give the flip-flop input equations if the counter is to be implemented using a D flip
flop for A, an R-S for B, and a J-K for C.







A B C

DA = BC+AB+AC

SB = A!B + !BC
RB = B!C + !AB

JC = !A!B
KC = AB
A B C
0 0 0
0 0 1
0 1 1
1 0 1
1 1 1
1 1 0
1 0 0
0 1 0

A B 0 1 C
0 0 0 0
0 1 0 a
1 1 1 1
1 0 b 1
A B 0 1 C
0 0 0 a
0 1 b b
1 1 b 1
1 0 a a
A B 0 1 C
0 0 a 1
0 1 0 1
1 1 0 b
1 0 0 1
2. (30) You've just been hired by the Really Fast Design Company to replace an engineer who
designed the following circuit. This circuit is intended to provide an output signal on QC with
a frequency of 500 KHz. However, the signal QC had a frequency of 1 MHz instead.

The flip flops have the following characteristics:
dHL
= 20ns,
dLH
= 10ns where
dHL
and
dLH

are the high to low and low to high propagation delays respectively.

a. Can you explain why? Please use a timing diagram as necessary for illustration.



b. How would you modify the design to work properly?









Q
Q
SET
CLR
D J
Q
Q
K
SET
CLR
J
Q
Q
K
SET
CLR
A B
C
QC
clock
4 MHz
Vcc


J
Q
Q
K
SET
CLR
C
QC
clock
4 MHz

3. (40) A system is designed to accept serial data on its input. If the bits at times t, t
-1
and t
-2

contain either 1 or 3 one bits, the output of the circuit is to be a 0 otherwise it is to be a 1.

a. Please draw a state diagram for such a system.

b. Please give the state and output table for such a system.

c. Please provide a state assignment for such a system.
0
1
2
3 4 5 6
0/0 1/0
0/0
1/0
1/0
0/0
0/0
1/0
1/0
0/1
1/1
0/1
0/0
1/1

Present Next

Output

x = 0 x = 1 x = 0 x = 1
0 1 2 0 0
1 3 4 0 0
2 5 6 0 0
3 3 4 0 1
4 5 6 1 0
5 3 4 1 0
6 5 6 0 1
7 x x 0 0
A B 0 1 C
0 0 0 1
0 1 2 3
1 1 5 -
1 0 6 4
Prev Pres Next
- 0 1,2
0 1 3,4
0 2 5,6
1,5 3 4
1,5 4 5,6
2,4,6 5 3,4
2 6 4,5
- 7 -


d. Please give the J-K flip - flop equations for such a system





JA = B!C + CX JB = A!X + C!X + A!CX JC = AB + !A!B!X
KA = B!X KB = X KC = A



e. Please give the output equation for such a system










Out = BCD + AC!D + A!B!CD + AB!D
Present Next

Output

ABC ABC x = 0 ABC x = 1 x = 0 x = 1
000 0 001 1 010 2 0 0
001 1 011 3 101 4 0 0
010 2 110 5 100 6 0 0
011 3 011 3 101 4 0 1
101 4 110 5 100 6 1 0
110 5 011 3 101 4 1 0
100 6 110 5 100 6 0 1
111 7 x x 0 0
0 1 1 0 X
A B 0 0 1 1 C
0 0 0 0 a 0
0 1 a a a 0
1 1 b 1 x x
1 0 1 1 1 1 A
0 1 1 0 X
A B 0 0 1 1 C
0 0 0 a 0 a
0 1 1 b b 1
1 1 1 b x x
1 0 a 0 0 a B
0 1 1 0 X
A B 0 0 1 1 C
0 0 a 0 1 1
0 1 0 0 1 1
1 1 a a x x
1 0 0 0 b b C
0 1 1 0 X
A B 0 0 1 1 C
0 0
0 1 1
1 1 1 x x
1 0 1 1 C
4. For the following two devices and their inputs data and sigIn,

a. (10) Please draw the corresponding output signals












b. (10) Please justify your answer

Device A is a latch, thus, the output will follow the input as long as the input is high.

Device B is an edge triggered device and will only change state on the rising edge.
Q
Q
SET
CLR
D
QA
QB
data
sigIn
Q
Q
SET
CLR
D
data
sigIn

data
sigIn
QB
QA