Layout Design Rules

EN 315 VLSI Design Dr. Gil B. Barte, Ph.D.

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

Cell Design
Standard Cells
General purpose logic Can be synthesized Same height, varying width

Datapath Cells
For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width

EN315_6_layout design rules/gbbarte

Standard Cell Layout Methodology – 1980s

Routing channel VDD

signals

GND

EN315_6_layout design rules/gbbarte

Standard Cell Layout Methodology – 1990s
Mirrored Cell

No Routing channels

VDD VDD

M2

M3
Mirrored Cell
EN315_6_layout design rules/gbbarte

GND GND

Standard Cells
N Well VDD

Cell height 12 metal tracks Metal track is approx. 3λ + 3λ Pitch = repetitive distance between objects Cell height is “12 pitch”

In

Out

Cell boundary

GND

Rails ~10λ

EN315_6_layout design rules/gbbarte

Standard Cells
With minimal diffusion routing
VDD

With silicided diffusion

VDD

V DD

M2 In M1 Out
In

Out

In

Out

GND

GND

EN315_6_layout design rules/gbbarte

Standard Cells
VDD

2-input NAND gate
V DD

B
A B

Out

A

GND

EN315_6_layout design rules/gbbarte

Stick Diagrams

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

Stick Diagrams
Contains no dimensions Represents relative positions of transistors
VDD VDD

Inverter

NAND2
Out Out

In GND GND

A

B

EN315_6_layout design rules/gbbarte

CMOS Inverter

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

Exercise 1

EN315_6_layout design rules/gbbarte

Exercise 2
Describe the function of the circuit

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

Why Have Design Rules?
1. 2. 3. 4. To be able to tolerate some level of fabrication errors such as Mask misalignment Dust Process parameters Rough surfaces (e.g., lateral diffusion)

EN315_6_layout design rules/gbbarte

Why Have Design Rules?
Designed

Result

decreasing dimension

EN315_6_layout design rules/gbbarte

Design Rules
Interface between the circuit designer and process engineer Guidelines for constructing process masks Unit dimension: minimum line width
scalable design rules: lambda parameter absolute dimensions: micron rules

Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur A complete set includes
set of layers intra-layer: relations between objects in the same layer inter-layer: relations between objects on different layers

EN315_6_layout design rules/gbbarte

Printing
Layout 0.25µ 0.18µ

0.13µ

90-nm

65-nm

Figures courtesy EN315_6_layout design rules/gbbarte

Synopsys Inc.

Intra-Layer Design Rule Origins
Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab
minimum line width is set by the resolution of the patterning process (photolithography)

Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab
0.3 micron
0.15 0.15

0.3 micron

EN315_6_layout design rules/gbbarte

Inter-Layer Design Rule Origins
1.

Transistor rules – transistor formed by overlap of active and poly layers Transistors
Catastrophic error

Unrelated Poly & Diffusion
Thinner diffusion, but still working

EN315_6_layout design rules/gbbarte

Transistor Layout
Transistor

1

3

2

5

EN315_6_layout design rules/gbbarte

Inter-Layer Design Rule Origins, Con’t
2.

Contact and via rules
M1 contact to p-diffusion M1 contact to n-diffusion M1 contact to poly Mx contact to My

Contact Mask Via Masks mask misaligned

both materials

0.3

Contact: 0.44 x 0.44

0.14

EN315_6_layout design rules/gbbarte

Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um

EN315_6_layout design rules/gbbarte

Metal Fills
Layout Density Control for Improved VLSI Manufacturability
Manufacturing steps involving chemicalmechanical planarization (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. Layout must be made uniform with respect to certain density criteria, by inserting "fill" geometries into the layout.
EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

The design rules are usually described in two ways : Micron rules, in which the layout constraints such as minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute dimensions in micrometers, or, Lambda rules, which specify the layout constraints in terms of a single parameter (?) and, thus, allow linear, proportional scaling of all geometrical constraints.
EN315_6_layout design rules/gbbarte

Lambda-based layout design rules were originally devised to simplify the industry- standard micronbased design rules and to allow scaling capability for various processes. It must be emphasized, however, that most of the submicron CMOS process design rules do not lend themselves to straightforward linear scaling. The use of lambda-based design rules must therefore be handled with caution in sub-micron geometries.

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

LAYOUT DESIGN RULES (LDR)
SPECIFIES MIN. ALLOWABLE VALUES FOR:Widths, separations, extensions, overlaps of features at various mask levels. LDR’S DEVELOPED TO TAKE ACCOUNT OF:MINIMUM FEATURE SIZE: This is limited by:min feature on a mask that can be routinely resolved in resist - Mask quality, litho tool, litho process, topography of wafer, wafer diameter. the change that a resist feature undergoes to define the feature on the wafer - Type of etching or LOCOS or lateral diffusion etc. electrical effects - Depletion spread, current density etc. ALIGNMENT: Minimum distances required to allow nesting (alignment) between features on different mask levels. Dependent upon:Alignment accuracy possible - Litho tool, operator ability. Variation in size or position of finished feature - Litho tool, type of etching, lateral diffusion, wafer diameter. Alignment sequence.
EN315_6_layout design rules/gbbarte

LAYOUT DESIGN RULES (LDR)
Alignment sequence (cont)
1. 2. 3. 4. 5. 6. 7. 8. 9. MASK DEVICE P-WELL POLY N+ P+ CONTACT METAL TOP-COAT SEQUENCE A SEQUENCE B

Sequence A results in a large cumulative misalignment between critical layers. i.e. 6 → 3 ∴ misalignment = 3δ Where δ= misalignment between 2 masks
EN315_6_layout design rules/gbbarte

Mead - Conway LDR’s
Above process factors - complex and interelated. Hence IC designer uses a single set of LDR’s that take into account all of these factors for each feature. An IC process will have a set of LDR’s expressed in microns. However, features are getting smaller and thus LDR’s will be in a continual state of flux. The one parameter that characterises any process is the “minimum feature size routinely produced by a process”. A set of LDR’s expressed in terms of this feature will survive the longest. Mead-Conway uses such an approach. They express the LDR’s in terms of a unit length λ. Where λ is the maximum deviation of a feature on the wafer that strays from another feature on the same layer or on another layer. 1978 λ ~ 3µm 1983 λ ~ 2µm 1986 λ ~ 1.5µm 1987 λ ~ 1.2µm 1994 λ ~ 0.5µm
EN315_6_layout design rules/gbbarte

Mead - Conway LDR’s (cont)
Two features on different mask levels will therefore be misaligned by as much as 2λ on the final wafer. M-C compromise this misalignment by stating quite reasonably:If overlapping of two features is catastrophic for the design then they must be separated by at least 2λ on the original artwork. If the overlapping is undesirable but not catastrophic (i.e. an increase in C or R results) then they should be separated by at least λ. Using this approach the LDR’s are greatly simplified although possibly at the expense of increased Si area and reduced circuit performance.
EN315_6_layout design rules/gbbarte

SCMOS Design Rule (see Principle of CMOS VLSI Design, by Weste, page 144 – 151)

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

Gate Layout
Layout can be very time consuming
Design gates to fit together nicely Build a library of standard cells

Standard cell design methodology
VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts
EN315_6_layout design rules/gbbarte

Stick Diagrams
Stick diagrams help plan layout quickly
Need not be to scale Draw with color pencils or dry-erase markers

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

Wiring Tracks
A wiring track is the space required for a wire
4 λ width, 4 λ spacing from neighbor = 8 λ pitch

Transistors also consume one wiring track

EN315_6_layout design rules/gbbarte

Well spacing
Wells must surround transistors by 6 λ
Implies 12 λ between opposite transistor flavors Leaves room for one wire track

EN315_6_layout design rules/gbbarte

Area Estimation
Estimate area by counting wiring tracks
Multiply by 8 to express in λ

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

Example: Inverter

EN315_6_layout design rules/gbbarte

Example: NAND3
Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 λ by 40 λ

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte

EN315_6_layout design rules/gbbarte