1

NuMicro
Flash Memory Controller (FMC)
NuMicro@nuvoton.com
2
Agenda
Flash Memory Features
Flash Memory Architecture
Flash Memory Structure
User Configuration
Boot Selection
ISP Operation Flow
ISP Sample Code


3
Flash Memory Features
128/64/32/16/8 KB application program memory (APROM)
4KB in system programming memory (LDROM)
for ISP loader
Configurable data flash address and size for
128KB system
Fixed 4KB data flash size for 64/32/16/8 KB system
512 bytes page erase unit




4
User Configuration
Application Program Memory
ISP Loader Program Memory
Data Flash
0x0000_0000
0x0010_0000
Reserved
0x0001_FFFF
0x0030_0000
0x0030_03FF
CONFIG0
CONFIG1
0x0030_0000
0x0030_0004
0x0010_0FFF
1
M
B
User Configuration
LDROM (4KB)
APROM and Data Flash
Flash Memory Architecture
5
Flash Memory Structure
4K bytes
Application Program
64/32/16/8 K bytes
128Kbyte Flash Memory Device 64/32/16/8 Kbyte Flash Memory Device
Reserved
Data Flash
4k bytes
Programmable start
address
Fixed start adrress
Application Program
(128-0.5*N)K bytes
128/64//32/16/8 Kbyte Flash Memory Structure
0x0001_F000
DFBADR[31:0]
0x0001_FFFF
DataFlash
0.5*N k bytes
0x0001_FFFF
DFEN
Enable
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Bits Descriptions
[31:29] Reserved Reserved
[28] CKF XT1 Clock Filter Enable
0 = Disable XT1 clock filter
1 = Enable XT1 clock filter
[27] Reserved Reserved
[26:24] CFOSC2-0 CPU Clock Source Select After Reset
000: External 12MHz crystal clock,
111: Internal RC 22MHz oscillator clock
Others: Reserved
[23] CBODEN Brown Out Detector Enable
0= Enable brown out detect after power on
1= Disable brown out detect after power on
[22:21] CBOV1-0 Brown Out Voltage Selection
11:4.5V, 10:3.8V, 01:2.7V, 00:2.2V
User Configuration (1/4) - Config 0 (1/2)
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Bits Descriptions
[20] CBORST Brown Out Reset Enable
0 = Enable brown out reset after power on
1 = Disable brown out reset after power on
[19:8] Reserved Reserved
[7] CBS Config Boot Selection
0 = Chip boot from LDROM
1 = Chip boot from APROM
[6:2] Reserved Reserved
[1] LOCK Security Lock
0 = Flash data is locked
1 = Flash data is not locked.
When flash data is locked, only device ID, Config0 and
Config1 can be read by writer and ICP thru serial debug
interface. Others data is locked as 0xFFFFFFFF. ISP
can read data anywhere regardless of LOCK bit value.
[0] DFEN Data Flash Enable
0 = Enable data flash
1 = Disable data flash
User Configuration (2/4) - Config 0 (2/2)
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User Configuration (3/4) - Config 1
Bits Descriptions
[31:20] Reserved Reserved
[19:0] DFBA Data Flash Base Address
For 128kB flash device, its data flash base address is
defined by user. Since on chip flash erase unit is 512
bytes. This configuration is only valid for 128KB flash device.
P.S. Only for NUC100 series
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User Configuration (4/4) - Comments
Brown Out Detect
Voltage detect level ?
Config Boot Selection
Code in APROM or LDROM ?
Security Lock




Flash data
unlocked
Flash data
locked
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Boot Selection (1/3)
Boot mode1
Boot in APROM, CBS(Config Boot
Selection) is 1 and user can update Data
Flash, LDROM or Config bits.
Limitation,
1. Cant update APROM.
2. Must enable LDROM Update
function to update LDROM.
3. Must enable Config-bits Update
function to
modify Config bits.

LDROM
APROM
Data Flash
Config bits
Update
Boot in APROM
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Boot Selection (2/3)
Boot mode2
Boo in LDROM, CBS(Config Boot
Selection) is 0, and user can update
APROM, Data Flash and Config bits.

Limitation,
1. Cant update LDROM.

LDROM
APROM
Data Flash
Config bits
Boot in LDROM
Update
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User Configuration
Application Program Memory
ISP Loader Program Memory
Data Flash
0x0000_0000
0x0010_0000
Reserved for Future Used
0x0001_FFFF
0x0030_0000
0x0030_03FF
0x0010_0FFF
1
M
B
Memory map of FMC
Boot Selection (3/3)
Flash Memory Space
(128KB)
System memory map
0x0000_0000
Boot in APROM
Boot in LDROM
SRAM Memory Space
(16KB)
0x0001_FFFF
0x2000_0000
0x0000_3FFF
System Global Control
Registers
......
......
......
13
ISP Operation Flow
Power On
Enable ISPEN
Write Data Flash ?
or
Update LDROM ?
1. ISPADR
2. ISPCMD
(3. ISPDATA)
Set ISPGO = 1
Check ISPFF = 1?
(or Read ISPDAT)
End of
ISP Operation
End of
Flash Operation
Enable
DFEN/LDUEN
5 Commamds :
1. Read
2. Program
3. Page Erase
4. Read CID
5. Read DID
If ISPFF(Fail Flag) = 1,
it means the one of the follow conditions.
1. APROM writes to itself.
2. LDROM writes to itself.
3. CONFIG is erased/programmed when
the MCU is running in APROM if
CFGUEN is set to 0.
4. Destination address is illegal,
such as over an available range.
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ISP Sample Code (1/5)
Read Company ID(CID)
Read Device ID(DID)
Read Data Flash Base Address
Erase Data Flash
Read Data Flash
Program Data Flash
Read/Write User Configuration


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ISP Sample Code (2/5)

#define PAGE_SIZE 512
#define DATA_FLASH_SIZE 4*1024
/*---------------------------------------------------------------------------------------------------------*/
/* Main Function */
/*---------------------------------------------------------------------------------------------------------*/
int32_t main (void)
{
int32_t i32Ret, i32Err;
uint32_t u32Data, DID, CID, Base_Adress;

/* Unlock protected registers to write ISP Control Register (ISPCON) */
UNLOCKREG();

/* Enable ISP function */
DrvFMC_EnableISP(1);

/* Read Company ID */
CID = DrvFMC_ReadCID(&u32Data);

/* Read Device ID */
DID = DrvFMC_ReadDID(&u32Data);

/* Read Data Flash base address */
Base_Address = DrvFMC_ReadDataFlashBaseAddr();

Enable ISP
Read Company ID
Read Device ID
Read Data Flash Base Address
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ISP Sample Code (3/5)

/* Erase Data Flash*/
for(i=0; i<DATA_FLASH_SIZE; i+=PAGE_SIZE)
{
i32Ret = DrvFMC_Erase(Base_Address + i);
if(i32Ret < 0)
{
i32Err = 1; /* Erase Failed */
}
}

/* Erase Verify */
i32Err = 0;
for(i=Base_Address; i<(Base_Address+DATA_FLASH_SIZE); i+=4)
{
i32Ret = DrvFMC_Read(i, &u32Data);
if(i32Ret >= 0)
{
if(u32Data != 0xFFFFFFFF)
{
i32Err = 1; /* Compare Failed */
}
}else
{
i32Err = 1; /* Read Failed */
}
}
Erase Data Flash
Read Data Flash
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ISP Sample Code (4/5)

/* Program Data Flash */
for(i=Base_Adress; i<(Base_Address+DATA_FLASH_SIZE); i+= 4)
{
i32Ret = DrvFMC_Write(i, i);
if(i32Ret < 0)
{
i32Err = 1; /* Write Failed */
}
}

/* Read out data to compare it */
i32Err = 0;
for(i=Base_Address; i<(Base_Address+DATA_FLASH_SIZE); i += 4)
{
i32Ret = DrvFMC_Read(i, &u32Data);
if(i32Ret >= 0)
{
if(u32Data != i)
{
i32Err = 1; /* Compare Failed */
}
}else
{
i32Err = 1; /* Read Failed */
}
}


Program Data Flash
Read Data Flash
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ISP Sample Code (5/5)

/* Read Configuration, Config0 & Config1*/
DrvFMC_Read(Cfg0Addr, &Cfg0Data);
DrvFMC_Read(Cfg1Addr, &Cfg1Data);

DrvFMC_EnableConfigUpdate(TRUE);

/* Write new Config0 & Config1 */
DrvFMC_Erase(Cfg0Addr);
DrvFMC_WriteConfig(Cfg0Write, Cfg1Write);

/* Read out to compare it */
DrvFMC_Read(Cfg0Addr, &Cfg0Read);
DrvFMC_Read(Cfg1Addr, &Cfg1Read);
if((Cfg0Read != Cfg0Write) || (Cfg1Read != Cfg1Write))
i32Err = 1; /* Compare Config0&1 Failed */

/* Restore Config0 & Config1*/
DrvFMC_Erase(Cfg0Addr);
DrvFMC_WriteConfig(Cfg0Data, Cfg1Data);

DrvFMC_EnableConfigUpdate(FALSE);

/* Lock protected registers */
LOCKREG();


Backup Config0&1
Write new Config0&1
Enable the Config-bits Update function
if system is running in APROM
Read Config0&1 and compare it
Restore Config0&1
Disable the Config-bits Update function
FMC Sample Code
MCU boot in APROM
LED rotates left
Press SW_INT to ISP function and Boot from
LD
MCU boot in LDROM
MCU reset, after MCU boot in LDROM
LED rotates right and flash

Run Smpl_Flash and LED Code
Customer_CD
Readme.txt
NUC1xx BSP
Driver Reference Guide
NUC1xx_BSP
NuvotonPlatform_Keil
NUC1xx-LB_002
Sample
Smpl_DrvFMC. uvproj
Smpl_Flash and LED
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Thank You