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You are on page 1of 4

Compensation Scheme

J oiio Ramos, Michiel Steyaert

K U Leuven, ESAT-MICAS

Leuven.

Abstract- A CMOS opamp that can drive large ca-

pacitive loads is presented. The technique employs a

positive feedback compensation (PFC) t o improve fre-

quency response as compared to nested Miller compen-

sation (NMC), allowing the circuit to occupy less silicon

area and straightforward design.

At 1.5 V, the circuit dissipates 275 pW, has more than

100 dB gain, a gain bandwidth of 2. 7 MHz and 1.0 V / p

average slew rate while driving a 130 pF load.

I. I NTRODUCTI ON

The driving force behind technology development -

digital CMOS design, demands high integration to lower

fabrication costs, and lower voltage to decrease power

consumption, which in turn allows reduction of thermal

dissipation, and in portable electronics ensures a reason-

able battery lifetime. This trend, makes everyone working

with integrated circuits aware of the constrains that low

voltages poses, especially in the case of analog design.

Given current standard CMOS fabrication processes

cannot withstand supply voltages higher that 1.5 V [l],

this is a strong push to do research in circuits able to

operate at this voltages, but without decrease in perfor-

mance.

For the specific case of analog design, the basic building

block nowadays continues to be the operational amplifier.

The literature, aware of this fact continues to publish new

solutions that try to mitigate the ongoing needs, such as

operation at lower supply voltages [2-41, higher gain [3-51,

bandwidth and efficiency. Particularly at low voltages,

cascoding is no longer an advisable technique to achieve

high gain, as stacked transistors limit the available voltage

swing at the output. As a result the multistage amplifiers

is under research as a technique to overcome this limita-

tion.

For the CMOS operational amplifier presented in this

paper, a three stage (good compromise between a high

voltage gain, complexity of the circuit and power dissipa-

tion) amplifier is developed that offers simultaneously op-

eration at low voltages (1.5 V), rail-to-rail output swing,

high gain (>l o0 dB) and good bandwidth to power dis-

sipation efficiency. This is a result of the new proposed

compensation technique.

The goal of this work is to realize a three stage amplifier

with a better bandwidth to power efficiency and suitable

Belgium

Fig. 1. Block diagram of a typical NMC amplifier.

Fig. 2. Block diagram of the newly proposed PFC amplifier.

for driving high capacitive loads such as high accuracy EA

modulators, pipeline A/D converters, linear regulators,

etc.

I n the next section we will briefly review the NMC

topology, the starting point for multistage amplifiers. The

PFC amplifier and some of its characteristics are then in-

troduced, before presenting, in section 111, the measured

results from a test chip that was fabricated and measured

to show the effectiveness of the compensation scheme. Fi-

nally, some conclusions are draw.

11. PROPOSED COMPENSATION

With the NMC compensation (Figure 1) for every new

gain stage added, a new Miller capacitor is added for com-

pensation purposes. However this new capacitor reduces

the bandwidth by a factor of two [6]. Moreover both ca-

pacitors load the output, and thus, increasing the power

requirements for the last stage in order to fulfill the band-

333

width and slew requirements. If capacitor Cm2 is not

present, a higher bandwidth is possible, but not without

having an instable amplifier as now a pair of complex

poles with sinall damping factor appear close to the unity

gain frequency. If we can conceive a circuit that allows

to: control the damping factor, does not load the output

and does not increase the circuit consumption, we would

have eliminated the peaking while having a wider band-

width. The proposed solution for frequency Compensation

is depicted in Figure 2.

The feed-forward transconductance gmf bypasses all

but the first stage at high frequencies to provide a direct

path to the output, consequently, this boosts the band-

width of the PFC amplifier. This block, is implemented

using a single MOS transistor (gmf in Figure 3) , driven

by the output of the first stage and connected to the out-

put node. By using this approach to implement g mf , it

is ensured that there is no increase in power consump-

tion and silicon area, when comparing it to the NMC [6]

counterpart.

A positive feedback around gm2 allows to effectively

control the damping factor of the complex poles, and ca-

pacitor Cm2 fulfill this condition. This capacitor is pre-

dominantly smaller than Cm, , and thus, not limiting the

slew rate of the first stage.

A. Theoretical Analysis of Frequency Response

It can be shown that, for the arrangement of Figure 2,

the open loop gain is given by

With the purpose of having symmetrical current capa-

bility in the output stage of Figure 3 and noting that gm3

and gmJ are in the same branch, both transconductances

are set to have equal values: gmf =gm3. After simplifica-

tion, the DC gain is given by

with a dominant pole at

The determination of the values for the second-order

system in the denominator of H( s ) follows the assumption

that the amplifier has third order Butterworth response

with unity gain feedback [6]. This assumption does not

take into account the presence of the zeros in the transfer

function and implies that the poles will be complex with

the damping ratio I equal to 1/ d, leading tc a phase

margin of 60.

The overall transfer function includes two zeros: one

LHP zero and one RHP zero. Given the constrains of

(4) applied in (1): the RHP zero will have a value one

magnitude order higher than the GBW minimizing the

degradation in the phase margin; a value smaller but close

to WO for the zero in the LHP enhances the overs11 phase

margin. The location of the zeros in the PFC amplifier

is translated into a gain in stability.

From (1) to ( 5 ) , the unity gain frequency of the PFC

amplifier can be found to be

GBW =0.875 x w,

( 6)

Solving the previous system with the result from (4) in

order to obtain GBW as function of circuit small signal

parameters, and using the approach presented in [4]

GBW( ~FC) = (e) x 1.46

where

I n the case P being greater than one, the proposed tech-

nique achieves higher bandwidth than the NMC for the

same power consumption. However, ,Bcan be made larger,

which is the case when loaded by large capacitances, as it

is proportional to a. Maximizing gm2 with respect to

gm3 and minimizing parasitic capacitors at the output of

the second stage also makes this approach more ejficient.

I n the case /3 is greater than 4, the bandwidth of the PFC

amplifier may be even wider than a single stage amplifier

141.

334 19-3-2

AVDD

AVSS

Fig. 3. Schematic diagram of the PFC amplifier.

B. Circuit Implementation

The circuit of Figure 3, intended to demonstrate the

proposed compensation scheme of Figure 2, has been fab-

ricated and tested. The typical threshold voltage for the

NMOS and PMOS transistors is 0.59 V and -0.57 V, re-

spect ively.

With the purpose of maximizing the efficiency of the

amplifier, a small signal equivalent of the circuit from Fig-

ure 3 was created in order to wrap around it an optimiza-

tion routine in Matlab. All parameters were optimized

with the exception of capacitor Cml r that had its value

set to be one order of magnitude higher than the parasitic

capacitors of the nodes it connects to. For the optimiza-

tion algorithm, a simple brute force approach was chosen,

being easy to implement and still fast to run, giving the

results in less than one minute.

111. EXPERIMENTAL RESULTS

A microphotograph of the PFC amplifier designed in

a 0.35 pm CMOS technology with five metal layers and

double poly capacitors is shown in Figure 6.

A. Measured Results

The bandwidth of the amplifier was chosen to be within

the range of the testset for automatic characterization of

opamps [ 7] . The frequency response is shown in Figure 4

and the measurement of the slew rate is shown in Figure 5

and was done with a Tektronix TDS680B oscilloscope.

The performances are summarized in Table I.

B. Performance Comparison

Considering that each amplifier has its own character-

istics, comparing them requires a figure of merit (FOM)

that weights the trade-off between the bandwidth, load

capacitance, slew rate and power consumption. Two of

them will be used: one for small signal [3] and one for

large signal performance [4].

4 0 -qi__L F,q" e" q

Fig. 4 Measured frequency response of the PFC amplifier.

-0 1 *I_ T l W .to-

Fig. 5. Measured transient response (130 pF//24 kR)

(10)

G B W [ M H z ] . Cr . [ p F]

FOMs =

power [mw]

The units are shown between brackets and the average

value of the SR is used for the calculations. From (10)

and (11) the higher the FOM, the better is the amplifier.

Table I1 presents an overview of multistage amplifiers

present in the open literature. Based on measured data,

both figures of merit are also presented. As can be seen,

TABLE I

MEASURED PERFORMANCE

Parameter

Technology

Low Frequency Gain

Unity Gain Requency

Phase Margin

Positive Slew Rate

Negative Slew Rate

Power Consumption

Power Supply

Load Condition

Area

Measured

0.35 pm CMOS

>l o0 dB

2. 7 MHz

52"

1.0 v/ps

1.0 v/ps

275 pW

3r0.75 V

130 pF / /24 kR

0.03 mm2

19-3-3

335

(dB) (MHz) (mW@Vdd)

Fig. 6. Microphotograph of the realized amplifier.

( V/ p s ) (pF) (MEyF) (w)

the figure of merit varies by more than one order of

magnitude. Different topologies and how much empha-

sis has been devoted to the optimization can justify this

effect. Especially note that the different load capacitors

are within a close range, so their weight in the calculations

is minimized.

From the results presented in Table 11, it can be con-

clude that the PFC amplifier is two times more efficient

in the case of small signal. In the case of large signal, the

best result is obtained. As indicated by equations (7) and

(9), a higher load capacitor will allow a higher FOMs [4].

I V. CONCLUSI ON

A new compensation scheme for a three stage ampli-

fier has been presented. The compensation capacitors

are small which allows the circuit to occupy less silicon.

The poles and zeros depend on ratios of currents and ca-

pacitors, making the stability less sensitive to matching

and thus making it suitable for integration in commercial

CMOS processes.

Measured results shows that this work outperforms the

other referenced amplifiers for a similar load capacitor.

This can be explained by the newly proposed topology

and a proper optimization of the overall circuit.

ACKNOWLEDGMENTS

J . Ramos gratefully acknowledges the financial support

from Fundapio para a Cicncia e a Tecnologiii and the

computer facilities provided by Ajuda a Igreja que Sofre

in the beginning of this work, both from Portugal.

REFERENCES

111 Overall Roadmap Technology Characteristics (ORTC), http:

//public.itrs.net/Files/2000UpdateFinal/ORTC2OOOfinal.

pdf.

[2] J . Fonderie and J . H. Huijsing, Operational Amplifier with 1-V

Rail-to-Rail Multipath-Driven Output Stage, IEEE J. Solid-

State Circuits, vol. 26, no. 12, pp. 1817-1824, Dec. 1.991.

131 H. T. Ng, R. M. Ziazadeh, and D. J. Allstot, A Muhistage Am-

plifier Technique with Embedded Frequency Compensation,

IEEE J . Solid-State Circuits, vol. 34, no. 3, pp. 339-347, Mar.

1999.

[4] K. N. Leung, P. K. T. Mok, W. 1. Ki, and J . K. 0. Sin, Three-

Stage Large Capacitive Load Amplifier with Damping-Factor-

Control Frequency Compensation, IEEE J . Solid-State Cir-

cuits, vol. 35, no. 2, pp. 221-229, Feb. 2000.

[5] K. Bult and G. J . G. M. Geeleri, A Fast-Settling CMOS Op

Amp for SC Circuits with 90-dB .DC Gain, IEEE J . Solid-State

Circuits, vol. 25, no. 6, pp. 1379--1384, Dec. 1990.

[6] R. G. H. Eschauzier, L. P. T. Kerklaan, and J . H. Huijsing,

100-MHz 100-dB Operational Amplifier with Multipath Nested

Miller Compensation Structure, IEEE J . Solid-Stai!e Circuits,

vol. 27, no. 12, pp. 1709-1717, Dec. 1992.

[7] C. Van Grieken and W. Sansen, A testset for automatic char-

acterisation of opamps in the frequency domain, in IEEE

International Conference on Microelectronic Test Structures,

Barcelona, Spain, Mar. 1993, vol. 6, pp. 83-88.

A CPdOS Low-

Distortion Fully Differential Power Amplifier with doc ble Nested

Miller Compensation, IEEE J . Solid-State Circuits, vol. 28, no.

7, pp. 758-763, J uly 1993.

[8] S . Pernici, S. Nicollini, and R. Castello,

336

19-3-4

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